1. Field of the Invention
This invention relates to the field of output buffers, and particularly to output buffers used to drive AC-coupled terminated transmission lines.
2. Description of the Related Art
There are many applications in which output buffers drive respective transmission lines to convey data to one or more devices connected to the transmission lines. In such applications, it is important that the integrity of the data on the transmission lines be maintained, so that it can be accurately detected by the receiving devices.
One such application is a random access memory (RAM) system. Dual-Inline Memory Modules (DIMMs) are the industry-standard platform on which RAM is provided for digital computers. Each DIMM is a printed-circuit board which contains a number of individual RAM integrated circuits (ICs) or “chips.” DIMMs typically contain address and/or control registers which distribute data bits to each of the DIMM's RAM chips via transmission lines driven by respective output buffers.
A typical DIMM arrangement is shown in
The use of termination resistors in this way can have an undesirable side effect, however, in that they tend to increase the DIMM's power consumption. For example, assuming that the output impedance of drive circuit 12 is ˜0Ω, V+ is 0.75 volts, and Rt is 30Ω, then the static power dissipation Pdiss associated with one transmission line is: Pdiss=(V+)2/Rt=18.75 mW/transmission line. There are typically 20-30 transmission lines on a DIMM, such that power dissipation due to Rt can be 500 mW or more.
An output buffer for driving AC-coupled resistively terminated transmission lines is presented which overcomes the problems noted above, by reducing power dissipation that would otherwise arise due to the termination resistor, while still maintaining the integrity of data being conveyed.
A capacitor is connected in series with each termination resistor such that each transmission line is AC-coupled to its termination voltage, thereby blocking DC current which would otherwise be dissipated in the resistor. Then, an output buffer in accordance with the present invention is used to drive each AC-coupled resistively terminated transmission line, with the buffer arranged to ensure the integrity of the data conveyed.
The present output buffer comprises at least two drive circuits coupled to an input signal; for purposes of illustration, first and second drive circuits are assumed, which provide respective drive signals that transition between ‘low’ and ‘high’ states in response to respective transitions of the input signal. The buffer is arranged such that, in response to a given input signal transition, the second drive signal transitions a predetermined amount of time after the first drive signal. The first and second drive signals are summed together to provide the buffer's output signal.
The first and second drive circuits are arranged such that, during output signal transitions of at least one polarity, the output signal has a first slew rate prior to the transition of the second drive signal, and a second, faster slew rate during the transition of the second drive signal. The drive circuits are preferably arranged such that the output signal's first and second slew rates act to reduce ringing on the transmission line in comparison with an output signal which transitions exclusively at a slew rate greater than the first slew rate. The delay between the first and second drive signal transitions and the output strengths of the respective drive signals may be made adjustable, such that the shape of the output signal waveform can be tailored as needed for a particular application.
As noted above, the present output buffer can include more than two drive circuits, each of which contributes to the buffer's output signal transitions. As above, the delays and output strengths associated with the respective drive signals can be made adjustable to further shape the output signal waveform.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.
a is a block diagram of one possible embodiment of an output buffer per the present invention which has more than two drive circuits.
b is a block diagram of another possible embodiment of an output buffer per the present invention which has more than two drive circuits.
The present output buffer is intended for use driving AC-coupled resistively terminated transmission lines, particularly when power consumption is a concern. The invention employs a capacitor connected in series with each lines' termination resistor Rt, to reduce power consumption that might otherwise occur due to the resistor. AC-coupling the transmission line to termination voltage V+ in this way also eliminates restrictions that may be imposed on V+.
The invention also includes an output buffer having at least two drive circuits, the outputs of which are summed to provide the buffer's output signal. For purposes of illustration, an output buffer with first and second drive circuits is described below, followed by a discussion of buffers with more than two drive circuits. The first drive circuit is coupled to an input signal, and provides a first drive signal which transitions between ‘low’ and ‘high’ states in response to respective transitions of the input signal. The second drive circuit is also coupled to the input signal, and provides a second drive signal which transitions between ‘low’ and ‘high’ states in response to respective transitions of the input signal. The buffer is arranged such that, in response to a given input signal transition, the second drive signal transitions a predetermined amount of time after the first drive signal. The first and second drive signals are summed together to provide the buffer's output signal, which is intended for driving an AC-coupled resistively terminated transmission line.
The first and second drive circuits are arranged such that, during output signal transitions of at least one polarity, the output signal has a first slew rate prior to the transition of the second drive signal, and a second, faster slew rate during the transition of the second drive signal. The drive circuits are preferably arranged such that their respective slew rates produce an output signal waveform which maintains the integrity of the data being conveyed on the transmission line. For example, the use of first and second slew rates as described herein can reduce the amplitude and duration of ringing on the driven transmission line, in comparison with an output signal which transitions exclusively at a slew rate greater than the first slew rate.
Though the present buffer is generally applicable to any AC-coupled terminated transmission line application, a primary application is in a memory system, in which each buffer drives a terminated address or control line routed to multiple. RAM chips populating a DIMM memory module. For example, for DIMMs in compliance with the DDR3 specifications promulgated by JEDEC, each address and control line is routed to multiple DRAM chips on the DIMM, and each line is terminated with a termination resistor having a resistance Rt. For purposes of illustration, this application is described throughout, though the invention is in no way limited to use with DIMMs.
A block diagram of an output buffer per the present invention, as it might be employed in a memory system application, is shown in
When terminated in accordance with JEDEC requirements (i.e., without AC-coupling), power is continuously dissipated in termination resistor Rt, even when output buffer 20 is not switching the state of transmission line 24. As noted above, under these conditions, static power dissipation Pdiss due to Rt is given by: Pdiss=(V+)2/Rt=18.75 mW/signal line, assuming Rt=30Ω and V+=0.75 volts. As noted above, a capacitor C is connected in series with Rt, to reduce Pdiss (note that C can be connected on either side of Rt; it only needs to block buffer 20 from seeing V+) . With transmission line 24 AC-coupled in this way, DC current which would otherwise be dissipated in the resistor is blocked; power is only dissipated in Rt when output signal 22 transitions between ‘high’ and ‘low’ states.
However, though capacitor C acts to reduce Pdiss, it may degrade the integrity of the data being conveyed on transmission line 24. The invention overcomes this problem with the use of an output buffer which produces a drive signal designed to maintain the integrity of data so conveyed.
The output buffer 20 includes a first drive circuit 30 and a second drive circuit 32. As noted above, the drive circuits' inputs are both coupled to an input signal IN, and their outputs are connected together to provide output signal 22, which is connected to drive AC-coupled resistively terminated transmission line 24. Drive circuits 30 and 32 produce respective drive signals (identified as signals ‘B’ and ‘C’, respectively) which transition between ‘low’ and ‘high’ states in response to respective transitions of input signal IN.
Note that, with the outputs of drive circuits 30 and 32 tied together, signals ‘B’ and ‘C’ are actually the same signal and must transition as one. As used herein, drive signal ‘B’ refers to the component of output signal 22 originating from drive circuit 30, and drive signal ‘C’ refers to the component of output signal 22 originating from drive circuit 32.
Second drive circuit 32 is arranged such that, in response to a given input signal transition, its drive signal ‘C’ transitions a predetermined amount of time after drive signal ‘B’; this transition delay is represented in
The operation of buffer 20 is illustrated in the timing diagram shown in
In the timing diagram of
Output buffer 20 can be arranged such that one or more aspects of the waveform of output signal 22 are adjustable: in particular, the delay between the ‘B’ and ‘C’ transitions and/or the strength output signal 22 can be made tunable. These options are discussed in more detail below.
An output buffer capable of producing an output signal as described herein could be implemented in many different ways. One possible implementation of an output buffer in accordance with the present invention is shown in
Note that the delay in the transition of the second drive signal can be implemented in many ways; the method shown in
When implemented as shown in
Another way in which the waveform of output signal 22 might be adjusted is to make the output impedance of one or both of drive circuits 30 and 32 tunable, as both the slew rate and drive strength of a drive circuit's drive signal vary with its output impedance. The output impedance of a drive circuit may be made variable by a wide variety of means; one exemplary implementation is shown in
For the exemplary embodiment shown in
As noted above, an output buffer in accordance with the present invention can have more than two drive circuits. Such a buffer could be implemented in many different ways; one possible embodiment is illustrated in
Another possible embodiment of an output buffer having more than two drive circuits is shown in
Note that the circuits and methods shown in
Note that, though the schematics contained herein depict the use of field-effect transistors (FETs), bipolar transistors or other state-of-the-art current switching integrated circuit devices could also be used.
While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.