Output buffer with voltage sustainer circuit

Abstract

There is provided a dynamic output buffer useful for providing output data from a memory. The output buffer includes a cross coupled sense amplifier having inputs and outputs. The outputs of this sense amplifier are coupled by output transistors to the output of the dynamic output buffer. The outputs of the cross coupled sense amplifier are also coupled to dynamic load devices which are used to prevent the outputs from deteriorating when the inputs are shunted or clamped to ground. The inputs are clamped to ground by transistors which are controlled by timing signals and thereby insure that data stored by the cross coupled sense amplifier will not be lost.

Description

This invention relates, in general, to output buffers, and more particularly, to output buffers useful in digital memories.

Buffers are used to buffer data from a memory to outside circuitry. The most common type of buffer used includes a cross coupled sense amplifier. In MOS circuitry it is common to have the cross coupled sense amplifier enabled by one clock signal. However, because of the bidirectional conductivity of MOS transistors it is necessary to take special precautions with the clock signal, and the circuitry providing the clock signal, to insure that data stored in the cross coupled sense amplifier is not lost or discharged back through the clock signal circuitry when the clock signal is in a nonenabling state.

Accordingly, it is an object of the present invention to provide an improved dynamic output buffer which is capable of holding output data for long periods of time without appreciable deterioration of the data.

Another object of the present invention is to provide an improved dynamic output buffer wherein the output data is maintained at substantially a constant amplitude even during switching of internal transistors of the buffer itself.

SUMMARY OF THE INVENTION

In carrying out the above and other objects of the present invention, there is provided in one form, a dynamic output buffer having a cross coupled sense amplifier which is used to receive the input data so that it can be outputted by output driver transistors upon command. Field effect transistors, which are controlled by timing signals, are used to disconnect the cross coupled sense amplifier inputs from external circuitry. The circuit also includes additional dynamic loads coupled to the outputs of the cross coupled sense amplifier to restore or boost the output at the same time that the inputs are being disconnected from the external circuitry thereby preventing outputs of the cross coupled sense amplifier from decreasing substantially in amplitude.

The subject matter which is regarded as the invention is set forth in the appended claims. The invention itself, however, together with further objects and advantages thereof, may be better understood by referring to the following detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates, in schematic form, an embodiment of the invention; and

FIG. 2 is a timing diagram useful in understanding the operation of the circuitry of FIG. 1.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a dynamic output buffer useful for receiving data from within a memory and coupling it to the output of the memory itself. The dynamic output buffer receives data on lines 17 and 21 and stores the data in a cross coupled sense amplifier having transistors 10, 11, 12, and 13. Transistors 10 and 12 are coupled in series between an output latch clock signal OL and a reference terminal illustrated as ground. Transistors 11 and 13 are coupled in parallel with transistors 10 and 12. A node 15 which is formed between transistors 10 and 12 serves as one output for the cross coupled sense amplifier, and node 16 formed between transistors 11 and 13 serves as another output for the cross coupled sense amplifier. Transistor 12 has its gate electrode coupled to node 16, and transistor 13 has its gate electrode coupled to node 15. Transistor 10 has its gate electrode coupled to node 19 which serves as an input for the cross coupled sense amplifier, and transistor 11 has its gate electrode coupled to node 23 which serves as another input for the cross coupled sense amplifier. Node 19 is coupled to line 17 by transistor 18. Transistor 18 is enabled by a column address strobe CAS applied to its gate electrode. Node 23 is coupled to line 21 by transistor 22 which has its gate electrode enabled by the same timing signal CAS as transistor 18.

The input signals to the cross coupled sense amplifier are complements of each other. If it is assumed that node 19 has an input signal sitting at a high level, which would mean the input signal at node 23 would be at a low level, then when clock signal OL goes high, transistor 10 would conduct thereby driving node 15 high. Since node 15 is coupled to the gate electrode of transistor 13, transistor 13 would conduct thereby placing node 16 at a low level. Transistor 12 would remain in a non-conducting state since its gate electrode is coupled to node 16. Node 15 is also coupled to a gate electrode of transistor 25. Transistor 25 is coupled between input node 23 and ground. Since node 15 was assumed to be at a high level, transistor 25 will conduct thereby maintaining input node 23 at a low level. As long as clock signal OL is high, and timing signals RAS and CAS are low, node 15 will remain high and OUTPUT data will be valid. Before clock signal OL goes low, timing signals CAS and RAS go high which causes node 19 to discharge to ground and effectively turns off transistor 10 thereby isolating node 15 from the circuitry which provides clock signal OL. This insures that node 15 remains at a high level.

Transistor 28 is in parallel with transistor 25 and has its gate electrode coupled to the complement column address strobe timing signal CAS. Another transistor 31 is in parallel with transistor 28 and has its gate electrode coupled to a complement row address strobe timing signal RAS. Transistors 28 and 31 will maintain node 23 at a low level when their gate electrodes are enabled. In certain situations, timing signal CAS may be delayed and therefore timing signal RAS will insure that node 23 is maintained at a low level. Input node 19 also has three transistors 26, 27, and 30 coupling it to ground. Transistor 26 has its gate electrode coupled to node 16, transistor 27 has its gate electrode coupled to timing signal CAS, and transistor 30 has its gate electrode coupled to timing signal RAS. Transistors 26, 27 and 30 operate in a similar manner to that explained, hereinbefore, for transistors 25, 28 and 31 serve to shunt or clamp input 19 to ground.

Output node 15 is coupled to a gate electrode of transistor 33, and output node 16 is coupled to a gate electrode of transistor 32. Transistors 32 and 33 are in series between a voltage potential terminal V.sub.DD and ground. The output for the dynamic output buffer is provided from an OUTPUT node between transistors 32 and 33. If node 16 goes high transistor 32 conducts and the OUTPUT node goes high. If output node 15 goes high, transistor 33 will conduct thereby providing a low level at the OUTPUT node. Transistor 34 is coupled from output node 16 to ground, and transistor 36 is coupled from output node 15 to ground. Transistors 34 and 36 both have their gate electrodes coupled to a control signal which is used as an output disable OD. When control signal OD is at a high level, transistors 34 and 36 will conduct thereby discharging output nodes 15 and 16 and rendering transistors 32 and 33 non-conductive which causes the OUTPUT node to float or go to a high impedance state. The output transistors are in a state to be enabled when output disable OD is at a low level.

Output node 16 has a voltage restorer comprising transistors 41 and 42 and capacitor 40 coupled to it. If node 16 is sitting at a high level and timing signal RAS goes high thereby enabling transistor 31, input node 23 can be caused to move to a low level which can be capacitively coupled through transistor 11 to output node 16 causing a decrease in the signal level at output node 16. To alleviate this potential problem, a restorer circuit or glitch eliminator is coupled to output node 16. Transistor 41 is coupled between voltage terminal V.sub.DD and output node 16. Transistor 42 is coupled between the gate electrode of transistor 41 and output node 16. Transistor 42 has its gate electrode coupled to voltage potential V.sub.DD and therefore transistor 42 will be enabled. When the timing signal RAS goes high, capacitor 40 will couple this high level to the gate electrode of transistor 41 causing transistor 41 to conduct thereby boosting output node 16. If output node 16 is sitting at a low level, this low level would be reflected through transistor 42 to the gate electrode of transistor 41 and when capacitor 40 couples an increasing RAS to the gate electrode of transistor 41, transistor 42 will tend to keep the gate electrode at a low level thereby preventing transistor 41 from conducting. Output node 15 also has a voltage restoring circuit coupled to it which operates in the same manner as does the voltage restoring circuit for output node 16. Transistor 45 is coupled from voltage V.sub.DD to output node 15, and transistor 46 is coupled from the gate electrode of transistor 45 to output node 15. A coupling capacitor 44 is coupled from the gate electrode of transistor 45 to timing signal RAS. Capacitors 40 and 44 can be implemented as MOS transistors. For example, the capacitors can be field effect transistors having their drain and source electrodes connected together to input timing signal RAS while their gate electrode is coupled to the gate electrode of transistor 41 or 45.

Timing waveforms found in the circuitry of FIG. 1 are illustrated in FIG. 2. The top waveform is timing signal RAS and generally leads timing signal CAS by a short period of time. When input control signal CAS (not shown) goes high data sitting on line 17 and 21 are coupled to input nodes 19 and 23 respectively. As illustrated in FIG. 2, it is assumed that node 23 goes high. When node 23 goes high, transistor 11 is enabled and therefore output node 16 will go high when output latch clock signal OL goes high. When output disable signal OD goes low transistors 34 and 36 are no longer conductive and therefore no longer holding output nodes 15 and 16 at a low level, therefore, the high on output node 16 will cause transistor 32 to conduct thereby driving the OUTPUT node between transistors 32 and 33 to a high level which is indicated in FIG. 2 as DATA VALID. Note that when RAS goes high a slight glitch 50 is caused on the signal at output node 16 but because of the restoring circuit coupled to output node 16, output node 16 is not permanently deteriorated.

By now it should be appreciated that there has been provided a dynamic output buffer having a cross coupled sense amplifier which is effectively isolated from the memory or external circuit once the cross coupled sense amplifier is in a latched state thereby preventing any loss of data contained in the cross coupled sense amplifier. The cross coupled sense amplifier also has voltage restoring circuits coupled to its output so that as its input is pulled low the output will not be deteriorated.

Claims

a first transistor having a control electrode for receiving a first input data signal, a first current electrode for receiving the clock signal, and a second current electrode coupled to the first output node;

a second transistor having a control electrode for receiving a second data signal which is complementary to said first data signal, a first current electrode for receiving the clock signal, and a second current electrode coupled to the second output node;

a third transistor having a control electrode coupled to the second output node, a first current electrode coupled to the first output node, and a second current electrode coupled to a first power supply terminal;

a fourth transistor having a control electrode coupled to the first output node, a first current electrode coupled to the second output node, and a second current electrode coupled to the first power supply terminal;

a fifth transistor having a first current electrode coupled to a second power supply terminal, a second current electrode coupled to said first output node, and a control electrode;

a sixth transistor having a first current electrode coupled to the control electrode of the fifth transistor, a second current electrode coupled to said first output node, and a control electrode coupled to the second power supply terminal;

a first coupling capacitor coupled between the control electrode of the fifth transistor and the enabling signal;

a seventh transistor having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to said second output node, and a control electrode;

an eighth transistor having a first current electrode coupled to the control electrode of the seventh transistor, a second current electrode coupled to the second output node, and a control electrode coupled to the second power supply terminal; and

a second coupling capacitor coupled between the control electrode of the seventh transistor and the enabling signal. .Iaddend..Iadd. 8. The circuit of claim 7 further comprising:

a ninth transistor having a control electrode coupled to the second output node, a first current electrode coupled to the first power supply terminal, and a second current electrode; and

a tenth transistor having a control electrode coupled to the first output node, a first current electrode coupled to the second power supply terminal, and a second current electrode coupled to the second current electrode of the ninth transistor. .Iaddend. .Iadd. 9. The circuit of claim 8 further comprising:

an eleventh transistor having a first current electrode coupled to the control electrode of the first transistor, a control electrode coupled to the second output node, and a second current electrode coupled to the first power supply terminal; and

a twelfth transistor having a first current electrode coupled to the control electrode of the second transistor, a control electrode coupled to the first output node, and a second current electrode coupled to the first power supply terminal. .Iaddend..Iadd. 10. The circuit of claim 9 further comprising disable means for coupling said first and second nodes to the first power supply terminal so long as a disable signal is present. .Iaddend.