Patent Application
20160073466
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-180992, filed Sep. 5, 2014, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to an output circuit and a light coupling device.
In general, various functional blocks are included in a mixed signal circuit in which a logic circuit and an analog-digital circuit are combined. For improved integration and function of a semiconductor integrated circuit device, there is a strong preference for transmitting digital data within the functional block, between the functional blocks, or even between devices in a system, at a high speed and at a low noise level. Also, there is a strong demand for low power consumption. In order to achieve signal transmission at a high speed and at a low noise level across various interfaces, a slew rate control output circuit that outputs a signal at a constant slew rate (a maximum rate of voltage change per unit time) is proposed. However, it is difficult to drive a wide range of load capacitors with low power consumption in such a device.
Example embodiments provide an output circuit and a light coupling device that drive a wide range of load capacitors with low power consumption.
In general, according to one embodiment, an output circuit for receiving an input signal and transmitting an output signal is provided. The output circuit includes an input terminal, an output terminal, a power supply terminal, a reference potential terminal, an output unit, a first drive circuit, and a second drive circuit. The output unit includes a first transistor of a first conductivity type including a drain and a source which are connected between the power supply terminal and the output terminal. The output unit further includes a first capacitance element connected between a gate and the drain of the first transistor. The output unit further includes a second transistor of a second conductivity type including a drain and a source which are connected between the reference potential and the output terminal. The output unit further includes a second capacitance element connected between a gate and the drain of the second transistor. The first drive circuit is configured to detect when the second transistor is turned off by a gate voltage of the second transistor, wherein the first drive circuit is configured to drive the first transistor to an on state. The second drive circuit is configured to detect when the first transistor is turned off by a gate voltage of the first transistor, wherein the second drive circuit is configured to drive the second transistor to an on state.
Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings.
As illustrated in
The output unit 2 includes an N channel MOSFET 3 (second transistor) and a P channel MOSFET 4 (first transistor). Drain terminals of the N channel MOSFET 3 and the P channel MOSFET 4 are connected to each other. A source terminal of the N channel MOSFET 3 is connected to the ground terminal 46, and a source terminal of the P channel MOSFET 4 is connected to the power supply terminal 45. The output unit 2 that includes the N channel MOSFET 3 and the P channel MOSFET 4 forms an output circuit of a CMOS type. A capacitor 5 (second capacitor, also referred to as second capacitance element) is connected between a gate and a drain of the N channel MOSFET 3. A capacitor 6 (first capacitor, also referred to as first capacitance element) is connected between a gate and a drain of the P channel MOSFET 4. The capacitors 5 and 6 form mirror capacitors of the N channel MOSFET 3 and the P channel MOSFET 4, respectively, and determine a turn-on time and a turn-off time of the N channel MOSFET 3 and the P channel MOSFET 4, respectively. During a period in which the P channel MOSFET 4 turns on, the output signal Vout rises with a substantially constant slope. During a period in which the N channel MOSFET 3 turns on, the output signal Vout falls with a substantially constant slope. Thus, slew rates SRr and SRf at a rising time and a falling time respectively of the slew rate control output circuit 1 are substantially constant. In addition, since the N channel MOSFET 3 is connected to a low potential side with respect to the P channel MOSFET 4, the N channel MOSFET 3 may be also referred to as a low side transistor. Since the P channel MOSFET 4 is connected to a high potential side with respect to the N channel MOSFET 3, the P channel MOSFET 4 may be also referred to as a high side transistor.
The low side transistor drive unit 10 includes an N channel MOSFET 11 (sixth transistor), a P channel MOSFET 12 (fifth transistor), and a speed adjusting resistor 13 (second output resistor). The P channel MOSFET 12, the speed adjusting resistor 13, and the N channel MOSFET 11 are connected in series in this sequence between the power supply terminal 45 and the ground terminal 46. Anode that is between the speed adjusting resistor 13 and the N channel MOSFET 11 is connected to a gate terminal of the N channel MOSFET 3 in the output unit 2. Gate terminals of the N channel MOSFET 11 and the P channel MOSFET 12 are connected to each other, and are also connected to an output of the high side monitoring unit 25. The high side monitoring unit 25 and the low side transistor drive unit 10 are collectively an example of a second drive circuit. The low side transistor drive unit 10 drives the N channel MOSFET 3 of the output unit 2 in response to the output of the high side monitoring unit 25. Since the speed adjusting resistor 13 is in a current path that is formed when the N channel MOSFET 3 is turned on, a time required for turn-on of the N channel MOSFET 3 is longer than a turn-off time of the N channel MOSFET. The higher the resistance of the speed adjusting resistor 13, the longer before the N channel MOSFET 3 turns on (that is, the turn-on time is longer).
The high side transistor drive unit 15 includes an N channel MOSFET 16 (fourth transistor), a speed adjusting resistor 17 (first output resistor), and a P channel MOSFET 18 (third transistor). The P channel MOSFET 18, the speed adjusting resistor 17, and the N channel MOSFET 16 are connected in series in this sequence between the power supply terminal 45 and the ground terminal 46. A node that is between the P channel MOSFET 18 and the speed adjusting resistor 17 is connected to a gate terminal of the P channel MOSFET 4 in the output unit 2. Gate terminals of the N channel MOSFET 16 and the P channel MOSFET 18 are connected to each other, and also are connected to an output of the low side monitoring unit 20. The high side transistor drive unit 15 and the low side monitoring unit 20 are collectively an example of a first drive circuit. The high side transistor drive unit 15 drives the P channel MOSFET 4 of the output unit 2 in response to the output of the low side monitoring unit 20. Since the speed adjusting resistor 17 is in a current path that is formed when the P channel MOSFET 4 is turned on, a time required for turn-on of the P channel MOSFET 4 is longer than a turn-off time. The higher a resistance of the speed adjusting resistor 17, the longer before the P channel MOSFET 4 turns on (that is, the turn-on time is longer).
In this way, in the slew rate control output circuit 1 according to the first embodiment, the N channel MOSFET 3 and the P channel MOSFET 4 that are a CMOS type in the output unit 2 are driven by the drive circuits differently from each other. In addition, in the slew rate control output circuit 1, a speed adjusting resistor (e.g., speed adjusting resistors 13, 17) is used to ensure that the turn-off time of a MOSFET thus driven is shorter than the turn-on time thereof in both the low side transistor drive unit 10 and the high side transistor drive unit 15.
The low side monitoring unit 20 includes inverters 21 and 23, and a NAND 22. The input signal Vin from the input terminal 40 is fed through inverters 31 and 33 of input unit 30 and then into the NAND 22. Furthermore, a gate voltage Vnga of the N channel MOSFET 3 is input to the NAND 22 via the inverter 21. An output of the NAND 22 is connected to the high side transistor drive unit 15 through the inverter 23, and drives the P channel MOSFET 4 in the output unit 2 via the high side transistor drive unit 15.
The high side monitoring unit 25 includes a NAND 26, and inverters 27 and 28. An inverted signal of the input signal Vin and a gate voltage Vpga of the P channel MOSFET 4 are input to the NAND 26. An inverter 32 inverts the input signal Vin. An output of the NAND 26 is connected to the low side transistor drive unit 10 via the two inverters 27 and 28, and drives the N channel MOSFET 3 in the output unit 2 via the low side transistor drive unit 10.
The NAND 22 of the low side monitoring unit 20 monitors when the gate voltage Vnga of the N channel MOSFET 3 goes to a low level. If it is determined that the gate voltage Vnga is in a low level, the NAND 22 drives the high side transistor drive unit 15 so as to output a signal that makes the P channel MOSFET 4 turn on. A threshold voltage at which the low side monitoring unit detects that the gate voltage Vnga is in a low level is, for example, (½)×power supply voltage.
The NAND 26 of the high side monitoring unit 25 monitors that the gate voltage Vpga of the P channel MOSFET 4 which is a high side transistor goes to a high level. If it is determined that the gate voltage Vpga is in a high level, the NAND 26 drives the low side transistor drive unit 10 so as to output a signal that makes the N channel MOSFET 3 turn on. A threshold voltage which detects that the gate voltage Vpga is in a high level is an input threshold voltage of the NAND 26, for example, (½)×power supply voltage.
In addition, the threshold voltages of a logic level generated by the NANDs 22 and 26 may be set by changing the threshold voltages of logic gates in the front and the rear of the NANDs 22 and 26, for example, inverters 23 and 27, or the like.
In this way, the turn-off of each of the N channel MOSFET 3 and the P channel MOSFET 4 is monitored by detecting the levels of the respective gate voltages Vnga and Vpga.
The input unit 30 distributes the input signal Vin that is input from the input terminal 40 to the low side transistor drive unit 10 and the high side transistor drive unit 15 that are described above, via inverters 31 and 32, respectively. The low side transistor drive unit 10 and the high side transistor drive unit 15 operate according to an inverted logic, and thus an inverter 33 is inserted into one of the distribution paths, shown here as an example in the path between inverter 31 and low side monitoring unit 20.
Next, an operation of the slew rate control output circuit 1 will be described.
Next, an operation sequence at the time of a rising output signal Vout will be first described.
As illustrated in
Meanwhile at (5), the input signal Vin that is input from the input terminal 40 is input to the high side transistor drive unit 15 via the low side monitoring unit 20. The signal that is input to the high side transistor drive unit 15 is also transitioned from a low level to a high level at time t0. At (6) the N channel MOSFET 16 of the high side transistor drive unit 15 thus begins turning on charging a gate capacitor of the P channel MOSFET 4, and turning the P channel MOSFET 4 on. At this time, the gate capacitor of the P channel MOSFET 4 is charged via a conductance pathway including an ON resistance of the N channel MOSFET 16 and the speed adjusting resistor 17. A total resistance of the conductance pathway including the ON-state resistance of the N channel MOSFET 16 and the speed adjusting resistor 17 is set to be sufficiently higher (e.g., at least about five times higher, or at least about 15 times higher, or at least 30 times higher in some embodiments) than the resistance of the ON-state resistance of the N channel MOSFET 11 in the low side transistor drive unit 10.
A sequence from (1) to (4) corresponds to an operation by which the N channel MOSFET 3 turns on, and a sequence from (5) to (6) corresponds to an operation by which the P channel MOSFET 4 turns on. In this way, the low side monitoring unit 20 monitors the level of the gate voltage Vnga of the N channel MOSFET 3 to detect the turn-off of the N channel MOSFET 3. When the gate voltage Vnga is detected as a low level, the P channel MOSFET 4 turns on. Furthermore, if the N channel MOSFET 3 turns off, a resistance of an output resistor of the low side transistor drive unit 10 is set so as to be lower than an output resistor of the high side transistor drive unit 15 used to turn on the P channel MOSFET 4. Thus, the N channel MOSFET 3 rapidly turns off, and the P channel MOSFET 4 turns on after the N channel MOSFET 3 turns off.
In this way, it possible to prevent the N channel MOSFET 3 and the P channel MOSFET 4 from simultaneously turning on when the output signal Vout rises. In addition, logic gates of the NANDs 22 and 26 and the like, other transistors disposed within the circuit each have an intrinsic rising time, a falling time, or a propagation delay time. Consequently, there occurs a delay time from between the time the turn-off of the N channel MOSFET 3 is detected until the P channel MOSFET 4 turns on. Thus, a sequence at the time of rising of the output signal Vout includes a dead time period in which both of the N channel MOSFET 3 and the P channel MOSFET 4 are non-conducting.
Next, an operation sequence at the time of falling of the output signal Vout will be described.
As illustrated in
Meanwhile at (11), the input signal Vin input at the input terminal 40 is input to the low side transistor drive unit 10 via the high side monitoring unit 25. The signal that is input to the low side transistor drive unit 10 is transitioned from a high level to a low level. At (12), the P channel MOSFET 12 of the low side transistor drive unit 10 turns on, whereby the gate capacitor of the N channel MOSFET 3 is charged, and the N channel MOSFET 3 turns on. At this time, the gate capacitor of the N channel MOSFET 3 is charged via a conduction pathway including the P channel MOSFET 12 and the speed adjusting resistor 13. A total resistance of the conductance pathway including the ON-resistance of the P channel MOSFET 12 and the speed adjusting resistor 13 is set to a sufficiently higher (e.g., at least about five times higher, or at least about 15 times higher, or at least 30 times higher in some embodiments) than that of an ON resistance of the P channel MOSFET 18 in the high side transistor drive unit 15.
A sequence from (7) to (10) corresponds to an operation by which the P channel MOSFET 4 turns off, and a sequence from (11) to (12) corresponds to an operation by which the N channel MOSFET 3 turns on. In this way, the high side monitoring unit 25 monitors the level of the gate voltage Vpga of the P channel MOSFET 4 and thereby detects the turn-off of the P channel MOSFET 4. When it is detected that the gate voltage Vpga goes to a high level, the N channel MOSFET 3 is turned on.
In this way, it possible to prevent the N channel MOSFET 3 and the P channel MOSFET 4 from simultaneously being in a conducting state when the output signal Vout falls. In addition, in the same manner as a case where the output signal Vout rises, due to a propagation delay time or the like of the logic gates and other circuit elements, there is a delay time between the detection of the turn-off of the P channel MOSFET 4 until the N channel MOSFET 3 turns on. Thus, even a sequence at the time of falling of the output signal Vout includes a dead time period in which both of the N channel MOSFET 3 and the P channel MOSFET 4 are non-conducting (turned off).
In the slew rate control output circuit 1 according to the first embodiment, a drive voltage to each of the gate terminal of the N channel MOSFET 3 and the gate terminal of the P channel MOSFET 4 is monitored to prevent the N channel MOSFET 3 and the P channel MOSFET 4 from simultaneously being in a conducting state (turned on). Since it is difficult here to be affected by switching noise or the like, as compared with a case where an operation state of an output unit is monitored by detecting the voltage at an output terminal, it is possible here to detect more accurately the turn-off timing of one MOSFET by monitoring the voltage at each gate terminal of the N channel MOSFET 3 and the P channel MOSFET 4. Consequently, it is possible to more consistently prevent the two MOSFETs in the output unit 2 from simultaneously being turned on, and thus to achieve lower power consumption. In addition, in the same manner as a case where the operation state of the output unit 2 is monitored by detecting the voltage at the output terminal 41, it is less necessary to control or compensate for the switching noise or the like in the output unit 2 of the first embodiment. For this reason, the slew rate control output circuit 1 does not require as complex of a circuit layout or as wide of signal wires, and nevertheless, it is possible to prevent the two MOSFETs (e.g., element 3 and element 4) in the output unit 2 from simultaneously turning on, whereby it is possible to achieve low power consumption.
Next, the setting of the slew rate SRr at the time of rising of the signal will be described.
If the gate capacitor of the P channel MOSFET 4 is referred to as Ciss(P), the mirror capacitor 6 is referred to as Cm(P), and a gate-source capacitor is referred to as Cgs(P), then Ciss(P) is represented as follows.
Ciss(P)=Cm(P)+Cgs(P)
If a gain of the P channel MOSFET 4 is referred to as A(P), Cm(P) is represented as follows.
Cm(P)=(1+A(P))·Cgr(P)
Thus,
Ciss(P)=(1+A(P))·Cgr(P)+Cgs(P) Formula (1)
For example, if a transistor with an appropriate size is considered by using a typical CMOS process using a design rule of 0.6 μm, then A(P)≈6 is satisfied. If an electrostatic capacitance value Cgr(P) of the mirror capacitor 6 that is connected between a gate and a drain of the P channel MOSFET 4 is set to 2 pF, and a parasitic capacitor Cgs between the gate and a source of the P channel MOSFET 4 is set to 1.2 pF, Ciss(P)=15.2 pF is satisfied by Formula (1).
If a charging current that charges the gate capacitor Ciss(P) of the P channel MOSFET 4 is referred to as Ich(P), the charging current Ich(P) is represented by the following formula.
Ich(P)≈Ciss(P)·dVout/dt
Here, if a desired SRr is set to, for example, a maximum of 5V/6 ns,
Ich(P)≈15.2 pF×5V/6 ns=12.7 mA
If a resistance value of the speed adjusting resistor 17 is set to 1 kΩ, Vdd/(Ron16+1 kΩ)≈5V/1 kΩ=5 mA is satisfied, and becomes a sufficiently smaller value than Ich(P). Thus, the current that passes through the speed adjusting resistor 17 may be considered to be a constant current.
In this way, a total resistance value of the ON resistance of the N channel MOSFET 16 and the speed adjusting resistor 17 is set to a sufficiently high value, and thus the gate capacitor Ciss(P) of the P channel MOSFET 4 is charged by a substantially constant current. During a period in which the gate capacitor Ciss(P) is being charged by a substantially constant current, the gate-source voltage Vpga of the P channel MOSFET 4 is a substantially constant voltage, and the output signal Vout as well as the drain-source voltage relative to the reference potential rises with a substantially constant slope as shown in
A load capacitor (load capacitance) 43 is connected to the output terminal 41 of the slew rate control output circuit 1. Therefore, a relationship between the load capacitor 43 and the slew rate SRr will be reviewed. In the transistor that is designed by the typical CMOS process described above, the ON resistor (ON-resistance) Ron(P) of the N channel MOSFET 3 is generally about 50Ω. If an electrostatic capacitance value of the load capacitor 43 is referred to as CL and CL=10 pF, a time constant τ(P) is as follows:
τ(P)=Ron(P)·CL=50Ω×10 pF=0.5 ns.
The time constant τ(P) represents that 0.5 ns is required for an increase of (5 V×0.63)=3.15 V, whereby the slew rate is 3.15V/0.5 ns=6.3 V/ns. Meanwhile, a rising time based on the slew rate SRr obtained by a manner described above requires 6 ns for Vout to increase by 5 V, and thus SRr=5V/6 ns=0.48 V/ns. This is a long time, as compared with the time constant τ(P). Thus, if the load capacitor 43 is connected to the output terminal 41, the slew rate SRr is mostly determined by a time for the gate capacitor Ciss(P) of the P channel MOSFET 4 to be charged.
In this way, the rising time of the output unit 2 is determined by the gate capacitor Ciss(P) of the P channel MOSFET 4 and not by the load capacitor CL. The gate capacitor Ciss(P) value is mostly determined by the mirror capacitor corresponding to a gate-drain capacitor (capacitance). In addition, the gate capacitor Ciss(P) is charged by a constant current in output unit 2, and thus rising of the output signal Vout from the output unit 2 provides a substantially constant slew rate SRr.
As illustrated in
Next, the slew rate SRf at the time of falling is described in the same manner as the slew rate SRr at the time of rising. If the gate capacitor of the N channel MOSFET 3 is referred to as Ciss(N), the mirror capacitor 5 is referred to as Cm(N), and the gate-source capacitor is referred to as Cgs(N), Ciss(N) is represented by the following formula.
Ciss(N)=Cm(N)+Cgs(N)
If a gain of the N channel MOSFET 3 is referred to as A(N), Cm(N) is represented by the following formula.
Cm(N)=(1+A(N))·Cgr(N)
Ciss(N)=(1+A(N))·Cgr(N)+Cgs(N) Formula (2)
By charging the gate capacitor using a constant current, the output signal may fall at a substantially constant slew rate SRf, regardless of the load capacitor 43 (CL) that is connected to the output terminal 41.
In a case of the typical transistor that is produced using a 0.6 μm design rule in the same manner as the P channel transistor discussed above, A(N)≈7 is generally satisfied. If the electrostatic capacitance value Cgr(N) of the mirror capacitor 5 that is connected between the gate and the drain of the N channel MOSFET 3 is set to 1 pF, and the gate-source capacitor Cgs is set to 0.6 pF, Ciss(N)=8.6 pF is satisfied by Formula (2). Here, if a desired slew rate SRf is set to, for example, a maximum of 5V/6 ns in the same manner as the time of rising, the charging current Ich(N) is found as follows.
Ich(N)≈Ciss(N)·SRf=8.6 pF×5V/6 ns=7.2 mA
If the resistance value of the speed adjusting resistor 13 is set to, for example, 2 kΩ, then (Vdd/(Ron13+2 kΩ))≈5V/2 kΩ=2.5 mA is satisfied, and is a sufficiently smaller value than Ich(N). Thus, the current that passes through the speed adjusting resistor 13 may be considered to be a constant current.
In this way, in the same manner as described above where the output rises, a total resistance value of the ON resistance of the P channel MOSFET 12 and the speed adjusting resistor 13 is set so as to be sufficiently high, and thus it is possible to charge the gate capacitor Ciss(N) of the N channel MOSFET 3 using a constant current. Since the gate capacitor Ciss(N) of the N channel MOSFET 3 is charged by a constant current, the slew rate SRf at the time of falling of the output signal has a substantially constant value. The slew rate SRf may be set by adjusting the total resistance value of the speed adjusting resistor 13 and the ON resistance of the P channel MOSFET 12 of the low side transistor drive unit 10. The slew rate SRf may also be adjusted by changing the gate capacitor Ciss(N) of the N channel MOSFET 3 by adjusting the capacitance value of a gate-drain capacitor 5. The slew rate SRf may also be set by adjusting the gate capacitor together with an output resistance value of the low side transistor drive unit 10.
In this way, in the slew rate control output circuit 1 according to the first embodiment, it is possible to set the slew rates SRr and SRf at the time of rising and falling of the output signal Vout. By setting the input capacitors Ciss of the MOSFETs in the output unit 2 to be the same value as the load capacitor CL, it is possible to obtain the output signal Vout with a substantially constant slew rate regardless of the load capacitor CL. In addition, in the slew rate control output circuit 1 according to the first embodiment, it is possible to set the slew rates at the time of rising and at the time of falling to be equal to each other. Thus, it is possible to set the slew rate according to a parasitic inductance that is generated by a load connected to the output terminal 41, a length of the wire connected to the load, or the like, and to configure an interface circuit with higher versatility. In addition, in the slew rate control output circuit 1, in order to charge the gate capacitors Ciss of the MOSFETs in the output unit 2, resistor elements or ON resistances of the MOSFETs for driving are used in the charging conductance pathways, whereby it is possible to reduce power consumption more than that in a case where the constant current circuit is used to drive the output unit transistors. In the slew rate control output circuit 1, the low side monitoring unit 20 and the high side monitoring unit 25 detect the turn-off of one of the MOSFETs 3, 4 in the output unit 2 and then start the turn-on of the other MOSFET. Thus, the MOSFET that is turned on rises at a constant slew rate, whereby it is possible to substantially prevent the MOSFETs in the output unit 2 from simultaneously turning on. Thus, low power consumption is achieved in the slew rate control output circuit 1 according to the first embodiment.
The slew rate control output circuit according to a second embodiment is different from the slew rate control output circuit according to the first embodiment, in that the slew rate control output circuit according to the second embodiment sets more specifically the dead timing (dead time) in which the N channel MOSFET 3 and the P channel MOSFET 4 in the output unit 2 are prevented from simultaneously turning on. Hereinafter, the same symbols or reference numerals as in the slew rate control output circuit 1 according to the first embodiment are attached to the same circuit elements and connections as in the slew rate control output circuit 1, and detailed description thereof will be omitted.
A slew rate control output circuit 1a according to the second embodiment includes the output unit 2, the low side transistor drive unit 10, the high side transistor drive unit 15, a low side monitoring unit 20a, a high side monitoring unit 25a, and an input unit 30a. The low side monitoring unit 20a, the high side monitoring unit 25a, and the input unit 30a are different from those of the slew rate control output circuit 1 according to the first embodiment, and the other units are substantially the same.
The low side monitoring unit 20a includes a NAND 22a with three inputs, and inverters 21 and 23. The gate voltage Vnga of the N channel MOSFET 3 in the output unit 2 is input to the first input of the three inputs of the NAND 22a. The input signal Vin is input to the second input of the NAND 22a. An output of a delay signal generation unit 35 is input to the third input of the NAND 22a.
The high side monitoring unit 25a includes a NAND 26a, a NOR 29 with two inputs, and an inverter 27. The input signal Vin, and the gate voltage Vpga of the P channel MOSFET 4 in the output unit 2 are input to the NAND 26a. One of the two inputs of the NOR 29 is connected to the output of the NAND 26a, and the other input of the NOR 29 is connected to the output of the delay signal generation unit 35.
The delay signal generation unit 35 is connected to the input signal Vin, and generates a signal waveform that is obtained by delaying the input signal Vin. The delay signal generation unit 35 may generate the same delay time at the times of rising and falling, and may generate different delay times from each other at the times of rising and falling. The delay signal generation unit 35 may be configured using an analog technology, such as a time constant circuit or a delay line that is configured with, for example a capacitor and a resistor, or a timer circuit, or may be configured using a digital technology such as a frequency divider. In addition, in the delay signal generation unit 35, an internal delay time may be fixed, or the delay time may be varied when connected to an external component, a variable power supply, or the like.
Referring to
In
As illustrated in
The input signal Vin and the delay signal VDLY are respectively input to the NOR 29 of the high side monitoring unit 25a. The input signal Vin is input via the NAND 26a. The gate voltage Vpga of the P channel MOSFET 4 is input to the other input of the NAND 26a, whereby a signal with a high level from the NAND 26a is input to the NOR 29, at time t0. The NOR 29 outputs an inverted signal of a logical sum of the input signal Vin and the delay signal VDLY, thereby outputting a signal with a high level, at time t0. The low side monitoring unit 20a inverts the output of the NOR 29 via the inverter 27 making the N channel MOSFET 11 of the low side transistor drive unit 10 turn on, thereby making the gate voltage Vnga (VB) of the N channel MOSFET 3 in the output unit 2 go to a low level. The N channel MOSFET 3 in the output unit 2 starts to turn off at time t0.
The input signal Vin, the delay signal VDLY, and the gate voltage Vnga of the N channel MOSFET 3 are respectively input to the NAND 22a of the low side monitoring unit 20a. The low side monitoring unit 20a outputs an inverted signal of the logical product of the signals, whereby a logic level of the output of the low side monitoring unit 20a is inverted, at time t1′ when the delay signal VDLY changes state. For this reason, the high side transistor drive unit 15 makes the gate voltage Vpga of the P channel MOSFET 4 in the output unit 2 go to a low level, at time t1′, whereby the P channel MOSFET 4 is turned on.
In this way, at time t0 when the input signal Vin rises, the N channel MOSFET 3 in the output unit 2 turns off, and at time t1′ after the delay time DLY1 passes, the P channel MOSFET 4 turns on. Thus, when the input signal Vin rises, the output signal Vout includes substantially the same dead time DT1 as the delay time DLY1.
If the delay signal generation unit 35 detects falling of the input signal Vin (e.g., at time t2), the delay signal VDLY is output as a signal with a high level. The input signal Vin, the delay signal VDLY, and the gate voltage Vnga of the N channel MOSFET 3 in output unit 2 are respectively input to the NAND 22a of the low side monitoring unit 20a. The low side monitoring unit 20a outputs the logical product of the signals, whereby at time t2, a logic level of the output of the low side monitoring unit 20a is inverted. For this reason, the high side transistor drive unit 15 makes the gate voltage Vpga of the P channel MOSFET 4 in the output unit 2 go to a high level at time t2, whereby the P channel MOSFET 4 turns off.
The input signal Vin and the delay signal VDLY are respectively input to the NOR 29 of the high side monitoring unit 25a. The input signal Vin is input via the NAND 26a, and at time t2, the input signal Vin is inverted to signal with a low level, whereby the output of the NAND 26a is a high level due to the voltage Vpga of the P channel MOSFET 4. The NOR 29 outputs an inverted signal of the logical sum of the output of the NAND 26a and the delay signal VDLY, whereby at time t2, a signal with a low level is output from the NOR 29. The low side monitoring unit 20a inverts the output of the NOR 29 via the inverter 27, and thus makes the N channel MOSFET 11 of the low side transistor drive unit 10 turn on, thereby maintaining the gate voltage Vnga of the N channel MOSFET 3 in the output unit 2 at a low level. At time t2, both of the P channel MOSFET 4 and the N channel MOSFET 3 in the output unit 2 are at an off state. Thereafter, at time t3′, the delay signal generation unit 35 inverts the output (VDLY) into a signal with a low level. For this reason, the output of the NOR 29 in the high side monitoring unit 25a changes state to a high level. The high level from the NOR 29 is then inverted to a low level through the inverter 27. The low side transistor drive unit 10 then receives the output of the high side monitoring unit 25a, makes the gate voltage Vnga of the N channel MOSFET 3 in the output unit 2 go to a high level, whereby the N channel MOSFET 3 turns on. Thereby, the output signal Vout is transitioned from a high level to a low level.
In this way, in the slew rate control output circuit 1a according to the second embodiment, the delay signal generation unit 35 is added in association with the input signal Vin, and thus it is easy to generate the dead time, and thus in an operation in a range from a low frequency to a high frequency, it is possible to prevent the MOSFETs in the output unit 2 from simultaneously turning on, whereby it is possible to reduce power consumption.
In addition, a configuration of a logic circuit for generating the dead time at the times of rising and falling of the input signal Vin, is not limited to the above description, and it is possible to perform various modification, such as to input the output signal VDLY of the delay signal generation unit to the NAND of the high side monitoring unit.
In this way, by changing the speed adjusting resistors 13 and 17, the slew rates SRr and SRf may be changed. In addition, it is possible to separately set the turn-on conditions of the P channel MOSFET 4 and the N channel MOSFET 3 in the output unit 2, using the speed adjusting resistors 13 and 17, and to configure an output circuit with more general versatility.
As described above, the slew rates SRr and SRf of the slew rate control output circuit 1a are also determined by the time required for the gate capacitors of the MOSFETs in the output unit 2 to be charged. In some embodiments, since the current that charges the gate capacitors is mostly determined by output resistors of the low side transistor drive unit 10 and the high side transistor drive unit 15, it is possible to change the slew rates SRr and SRf by respectively adjusting the ON resistance of the P channel MOSFET 12 of the low side transistor drive unit and the ON resistance of the N channel MOSFET 16 of the high side transistor drive unit 15, instead of specifically inserting the speed adjusting resistors 13 and 17.
In this way, the transistor sizes are changed without using the speed adjusting resistors, and it is possible to easily set the slew rates by adjusting the ON resistances of the MOSFETs in the drive units.
The capacitors 5 and 6 are connected between the gates and drains of the MOSFETs in the output unit 2. By setting a capacitance value in which a mirror effect is considered as well as the maximum load capacitance value, it is possible to obtain a stable operation waveform. The slew rate is little changed, even if a load capacitor with a smaller capacitance value than that which is driven is used. By setting the electrostatic capacitance values of the capacitors 5 and 6 to sufficiently high values, the slew rates SRr and SRf may be relatively little affected by the specific capacitance value CL of the load capacitor 43 that is connected to the output terminal 41 or some range of load capacitance values.
In addition, in
In the above-described slew rate control output circuits 1 and 1a, the turn-on times of the MOSFETs in the output unit 2 are controlled and the slew rates are set by drive capacities that are determined by the speed adjusting resistors 13 and 17 or the like. Since the speed adjusting resistors 13 and 17 or the like are connected between the power supply voltage and the ground, drive capacities thereof are affected by the change of the power supply voltage. If the power supply voltage significantly decreases, the charging current that charges the gate capacitors of the MOSFETs that is output from the speed adjusting resistors 13 and 17 or the like significantly decreases. For this reason, the slew rate is significantly decreased. If the slew rate of the output signal Vout is decreased, the output signal Vout with a desired operation frequency is output, but the load cannot be driven. Thus, it is preferred to monitor the power supply voltage.
A slew rate control output circuit 1b according to the third embodiment includes a low voltage protection unit 50 and a NAND 60 that are added to the slew rate control output circuit 1a according to the second embodiment. Hereinafter, the same symbols or reference numerals as in the slew rate control output circuit 1a according to the second embodiment are attached to the same circuit elements and connections as in the slew rate control output circuit 1a, and detailed description thereof will be omitted.
As illustrated in
If the power supply potential is within a normal operation range, a potential at the input terminal 53 of the comparator 52 is a voltage equal to or higher than an ON voltage of the base-emitter voltage of the input transistor 54, and the input transistor 54 is in an ON state. For this reason, a base-emitter voltage of the inverting transistor 55 is equal to or lower than the ON voltage of the input transistor 54, and the inverting transistor 55 is in an OFF state. For this reason, the first output terminal 56 of the comparator 52 outputs a signal with a high level, and the NAND 60 outputs a signal according to the input signal Vin.
Meanwhile, if the power supply voltage decreases, whereby a voltage at the input terminal 53 of the comparator 52 decreases to a voltage lower than an ON voltage between a base and an emitter of the input transistor 54, the input transistor 54 turns off. A base-emitter voltage of the inverting transistor 55 increases to an ON voltage, whereby the inverting transistor 55 turns on. For this reason, one input of the NAND 60 goes to a low level, whereby the NAND 60 outputs a signal with a high level, regardless of the input signal Vin. Then, the P channel MOSFET 4 in the output unit 2 turns off, and the N channel MOSFET 3 maintains in an ON state.
In addition, it is preferable that the low voltage protection unit 50 be configured with a bipolar transistor or a MOS transistor with a low threshold voltage, in order to ensure that the low voltage protection unit 50 operates at a lower voltage than a voltage which limits the operation of another unit in the slew rate control circuit 1b.
In this way, in the slew rate control output circuit 1b according to the third embodiment, if the power supply voltage decreases, the level of the output signal Vout is maintained in a low level, regardless of the input signal Vin.
In the slew rate control output circuit 1b according to the third embodiment, since the operation of the subsequent logic circuit can be disabled using the NAND 60 disposed in the input unit 30a, the operation up to the low voltage operation limit of the NAND circuit 60 on the input side is ensured. The NAND circuit can include the configuration of an input circuit in which two MOSFETs are connected in series to each other. In such a configuration, a power supply voltage that is more than two times a threshold voltage for turning on or off a transistor is required in order to ensure the operation of the NAND circuit. In order to ensure an operation of a remainder of the light receiving circuit at a lower power supply voltage, it is necessary to add some additional switches as discussed below.
The slew rate control output circuit according to the fourth embodiment further includes the low voltage protection unit 50, gate switches 64 and 65, low side transistor drive unit blocking switches 66 and 67, and high side transistor drive unit blocking switches 68 and 69. Hereinafter, the same symbols or reference numerals as in the slew rate control output circuit 1b according to the third embodiment are attached to the same circuit elements and connections as in the slew rate control output circuit 1b, and detailed description thereof will be omitted.
The low voltage protection unit 50 is substantially the same as that of the slew rate control output circuit 1b according to the third embodiment. The low voltage protection unit 50 according to the fourth embodiment includes a second output terminal 57. The second output terminal 57 is connected to the collector terminal of the input transistor 54.
The gate switch 64 is connected between the gate and the source of the P channel MOSFET 4 in the output unit 2. The gate switch 65 is connected in series to a resistor 65a, between the gate of the N channel MOSFET 3 in the output unit 2 and the power supply terminal 45. Gate terminals of the gate switches 64 and 65 are each connected to the first output terminal 56 of the comparator 52.
The low side transistor drive unit blocking switch 66 is connected between the power supply terminal 45 and the P channel MOSFET 12 of the low side transistor drive unit 10a. The low side transistor drive unit blocking switch 67 is connected between the N channel MOSFET 11 of the low side transistor drive unit 10a and the ground terminal 46. Gate terminals of the low side transistor drive unit blocking switches 66 and 67 are connected to the second output terminal 57 and the first output terminal 56 of the comparator 52, respectively.
The high side transistor drive unit blocking switch 68 is connected between the power supply terminal 45 and the P channel MOSFET 18 of the high side transistor drive unit 15a. The high side transistor drive unit blocking switch 69 is connected between the N channel MOSFET 16 of the high side transistor drive unit 15a and the ground terminal 46. Gate terminals of the high side transistor drive unit blocking switches 68 and 69 are connected to the second output terminal 57 and the first output terminal 56 of the comparator 52, respectively.
If the potential at the power supply terminal 45 is within a normal operation voltage range, a potential at the input terminal 53 of the comparator 52 is a voltage equal to or higher than an ON voltage of the base-emitter voltage of the input transistor 54, and the input transistor 54 is in an ON state. A base-emitter voltage of the inverting transistor 55 is equal to or lower than the ON voltage, and the inverting transistor 55 is in an OFF state. As a result, the first output terminal 56 of the comparator 52 outputs a signal with a high level, and the second output terminal 57 outputs a signal with a low level.
The gate switches 64 and 65 are both turned off by the high level from the first output terminal 56. Thus, the P channel MOSFET 4 and the N channel MOSFET 3 in the output unit 2 are in an enable state. The low side transistor drive unit blocking switches 66 and 67, and the high side transistor drive unit blocking switches 68 and 69 are all turned on by the outputs of the first output terminal 56 and the second output terminal 57. Thus, the low side transistor drive unit 10a and the high side transistor drive unit 15a are both in an enable state.
Meanwhile, if the power supply voltage decreases whereby a voltage at the input terminal 53 of the comparator 52 decreases to a voltage lower than an ON voltage between a base and an emitter of the input transistor 54, the input transistor turns off. A base-emitter voltage of the inverting transistor 55 increases to an ON voltage, whereby the inverting transistor 55 turns on. The first output terminal 56 of the comparator 52 outputs a signal with a low level, and the second output terminal 57 outputs a signal with a high level. The gate switches 64 and 65 are both turned on by the outputs of the first output terminal 56. Thus, the P channel MOSFET 4 in the output unit 2 turns off, and the N channel MOSFET 3 in the output unit 2 turns on. Thus, the output terminal 41 is maintained in a low impedance state. The low side transistor drive unit blocking switches 66 and 67, and the high side transistor drive unit blocking switches 68 and 69 are all turned off by the outputs of the first output terminal 56 and the second output terminal 57. Thus, the low side transistor drive unit 10a and the high side transistor drive unit 15a both enter a disabled operation state that is disconnected from the power supply.
In
In a range that the power supply voltage is 3 V to 5V, the output signal Vout is normally output. However, as the power supply decreases, the slew rates SRr and SRf also decrease. If the power supply voltage decreases to 2 V, the output signal Vout is fixed to a low level by the function of the low voltage protection unit 50.
The slew rate control output circuit according to the present embodiment controls ON and OFF of one MOSFET without using a NAND, thereby switching enablement and disablement of a circuit, and thus an operation is ensured down to a lower voltage than that of the slew rate control output circuit 1b according to the third embodiment.
The light receiving circuits are used together with a light transmitting circuit that transmits a light signal, and may be used for a light coupling device 110. The light coupling device 110 is used in circumstances where it may be difficult to transmit a signal with a direct connection of an electric circuit or the like because a voltage level is significantly different between an input and an output. The light coupling device 110 is, for example, a photocoupler.
As illustrated in
The light emitting element 111 is an infrared emitting diode including, for example, AlGaAs or the like. The light emitting element 111 is driven by a drive circuit 114. The drive circuit 114 is connected to an external power supply that outputs, for example, voltage Vdd1 or Vss1, and a signal is input from a signal input terminal IN. The light emitting element 111 emits light according to an input signal, and transmits a light signal to a light receiving circuit 113. Vdd1 is, for example, +5 V, and Vss1 is, for example, −5 V.
The receiving circuit 112 includes the light receiving circuit 113 and the slew rate control output circuit 1. The slew rate control output circuit is not limited to the slew rate control output circuit 1 according to the first embodiment, and may be, of course, a slew rate control output circuit according to another embodiment. The light receiving circuit 113 includes a light receiving element 113a, and a trans-impedance amplifier 113b that converts a light current output from the light receiving element 113a into a voltage signal. The light receiving circuit 113 converts an analog signal to a digital signal, and inputs the digital signal to the slew rate control output circuit 1. The slew rate control output circuit 1 transmits the digital signal to a digital signal processing circuit or the like (not illustrated) via a cable or the like. It is preferable that the light receiving circuit 113 and the slew rate control output circuit 1 operate using a common power supply, but may use a separate power supply for the slew rate control output circuit 1 in order to drive the load capacitor(s). When a single power supply is used, an operation voltage is Vdd2-Vss2, where Vdd2 is, for example, 5 V, and Vss2 is, for example, 0 V.
As illustrated in
Since the light coupling device 110 includes the slew rate control output circuit 1 that outputs an output signal which is controlled to a constant slew rate, it is possible for the light coupling device 110 to be connected to a load circuit having a wide range of capacitors, and to drive the load circuit so as to have low noise and low power consumption.
The slew rate control output circuit 1 according to the embodiment described above is used in a receiving device 140 together with a transmission device 131 that transmits a light signal, and may be used in a light communication system 130. The receiving circuit 131 receives a light signal that is transmitted via an optical fiber 135, converts the received light signal into an electrical signal, and outputs the electrical signal.
The light communication system 130 according to the present embodiment includes a transmission device 131, an optical fiber 135, and a receiving device 140. The transmission device 131 includes a drive circuit 132, and a light emitting element 133 that is driven by the drive circuit 132. The light emitting element 133 of the transmission device 131 is optically coupled to an end portion of the optical fiber 135, and transmits a light signal. The other end portion of the optical fiber 135 is optically coupled to a light receiving element 143a of a light receiving circuit 143 of the receiving device 140, and receives the light signal that is transmitted via the optical fiber 135. The receiving device 140 further includes the slew rate control output circuit 1 that drives a load using the digital signal output from the light receiving circuit 143. The light receiving element 143a receives a light signal and converts the light signal into an electric signal, and a trans-impedance amplifier 143b converts an output current from the light receiving element 143a into a voltage signal.
The light communication system 130 according to the present embodiment is connected to the load circuit with a wide range of capacitors and may drive the load circuit so as to have low loss.
According to the embodiments described above, it is possible to achieve an output circuit, a light coupling device, and a light communication system that may drive a wide range of load capacitors with low power consumption at a constant slew rate.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-180992 | Sep 2014 | JP | national |
