Patent Application
20090134933
The present invention relates to output drivers suitable for controlling electric motors or similar and to method of operating such output drivers.
It is often desired to control electric motors and particularly small electric motors with on chip transistors. Controlling small motors with on-chip transistors has specific problems. These are mainly at issue for small motors in low cost applications wherein the number of external components is minimized, meaning the chip must assure good performance regarding electromagnetic compatibility (EMC).
Useful control of motors typically requires fast switching of drivers. In implementing such a fast switched driver, it is usual to provide a dead time in the switching procedure so as to minimise ‘pass-through’ currents in the driver. Secondly, it is also usual to slowly switch the driver, so as to control the voltage gradient at the driver output, to reduce unwanted electromagnetic emissions. Thirdly, to reduce noise and dissipation, it is desirable to reduce the current flow in the parasitic diodes of the output transistors. The first two requirements above are in conflict with the third necessitating compromise in driver design and performance.
It is therefore desirable to provide a method and a driver that, at least partially, overcomes or alleviates the above problems.
According to a first aspect of the present invention there is provided a method of switching an output driver of the type comprising an n-mos transistor and a p-mos transistor configured in a push-pull arrangement, the method comprising the following steps: slowly switching off the input to the initially designated active transistor; monitoring the variation in output voltage level in response thereto; and when a desired change in output level is detected initiating a transition procedure to complete the switching.
By monitoring whether the output level is rising or falling, the direction of current flow in the driver can be inferred. Accordingly, the initiation of the transition sequence can be optimised for the present circumstances. This results in a reduction in noise and dissipation due to current flow in the parasitic diodes of the output transistors without degrading operation in terms of minimising ‘pass-through’ current and controlling the output slope.
The monitoring of the output level may be carried out by a comparator. Preferably, the comparator is a fast sense comparator. A suitable form of fast sense comparator may comprise a capacitor, an amplifier and a switch wherein the switch is arranged in parallel with the amplifier.
The method may be adapted for use in a driver for controlling an electric motor.
When switching the driver output from low to high the desired change in output level may be a falling output voltage level. The related transition procedure may be rapidly switching off the input to the initially designated active transistor and rapidly switching on the input to the initially designated inactive transistor. When switching the driver output from high to low the desired change in output level may be a non-rising output voltage level or the output voltage level dropping below a predetermined threshold. The related transition procedure may be rapidly and completely switching off the input to the initially designated active transistor. After the input to the initially designated active transistor is rapidly and completely switched off, the input to the initially designated inactive transistor may be rapidly and completely switched on. The rapid switching on of the initially designated inactive transistor may be achieved by initiating the switching on of the initially designated inactive transistor based on the monitoring of the switching off of the initially designated active transistor by use of a comparator. In some implementations, between the complete switching off of the input to the initially designated active transistor and the switching on of the input to the initially designated inactive transistor, a dead period may be provided.
The driver may be arranged such that in normal operation current flows either into or out of the driver. In the present description, for the sake of clarity, the invention is described and claimed in respect of a driver arranged such that: in normal operation, current flows out of the driver; for a low output signal, the n-mos transistor is activated and the p-mos transistor is not activated; and for a high output signal, the p-mos transistor is activated and the n-mos transistor is not activated.
By way of example, in such an arrangement, in order to switch the driver output from low to high, the method may comprise slowly switching off the input to the n-mos transistor; detecting a falling output voltage level in response thereto; and then when a desired change in output level is detected rapidly switching off the input to the n-mos transistor and rapidly switching on the input to the p-mos transistor.
In such an arrangement, in order to switch the driver output from high to low, the method may comprise slowly switching off the input to the p-mos transistor; not detecting a rising output voltage level in response thereto; and continuing to slowly switch off the input to the p-mos. After the output reaches the desired low level, the input to the p-mos transistor can be rapidly and completely switched off. Subsequently, the input to the n-mos transistor can be rapidly and completely switched on. The rapid switching on of the n-mos transistor may be achieved by initiating the switching on of the n-mos transistor based on the monitoring of the switching off of the p-mos transistor by use of a comparator. In between the complete switching off of the input to the p-mos transistor and the switching on of the input to the n-mos transistor, a dead period may be provided.
It is of course immediately obvious to the skilled man that by suitable arrangement of the driver, it can be adapted to function with an oppositely directed current or with an opposite activation regime for the transistors. These variations are hereby incorporated.
According to a second aspect of the present invention there is provided an output driver suitable for controlling an electric motor, the output driver comprising an n-mos transistor and a p-mos transistor configured in a push-pull arrangement and the driver being operable in accordance with the method of the first aspect of the present.
The driver of the second aspect of the present invention may incorporate any or all features of the first aspect of the present invention as desired or as appropriate.
According to a third aspect of the present invention there is provided an electric motor controlled by an output driver according to a second aspect of the present invention or operating according to the method of the first aspect of the present invention.
The motor of the third aspect of the present invention may incorporate any or all features of the first or second aspects of the present invention as desired or as appropriate.
In order that the invention is more clearly understood, it will be described in greater detail below, by way of example only, and with reference to the accompanying drawings in which:
Turning now to
The figure also shows a pair of diodes 101a and 102a. These diodes 101a, 102a are parasitic elements inherent to each transistor 101, 102. The diode 102a in parallel with the n-mos transistor 102 can conduct current from GND to the output; the diode 101a in parallel with the p-mos transistor 101 can conduct current from the output to the supply line.
In existing drivers, controlling the output voltage OUT (in presence of an applied current I) in the transition from low to high is achieved as is illustrated in the timing diagram of
A high to low transition is achieved essentially by the inverse process. At time 114 IN changes and in response Gp is slowly switched off, allowing a controlled fall in OUT. When it is concluded that the Gp is ‘almost’ switched off, at 115, Gp is switched off fully as fast as possible whilst the Gn is slowly switched on, allowing OUT to stabilise at the desired low level.
This method achieves control of the output voltage without monitoring the level of the output signal OUT directly. Depending on the level of the current in the output, the voltage at the output will change slower or faster, but the controlling circuit does not know. As long as a transistor is not completely switched on, there is the possibility that current will flow in the parasitic diodes 101a, 102a. As an alternative, there can be direct monitoring of the voltage across diodes 101a and 102a supply rails 104. When it is detected that current is being drawn in the parasitic diodes 101a, 102a of the transistors, the relevant transistor 101, 102 can be reactivated to try to limit diode currents. This is a first improvement, and will decrease the current in the diodes, both in time and amplitude.
Turning now to
When it is detected that OUT is falling at 122, Gn is switched off as fast as possible. Subsequently at time 123, when Gn is completely off, Gp is switched on as fast as possible whilst monitoring OUT. When OUT passes its initial level at 124, Gp holds steady then slowly switches on to its high level at 125. The steady period in Gp is due to the inherent capacitance of transistor 101 as described above.
Considering now the transition from high to low. Initially, in response to the change in IN at 126, Gp is slowly switched off whilst monitoring OUT. When it is detected that OUT is falling we know that the current is flowing out of the pin. (If is rising, the current is flowing in the other direction). When OUT has substantially reached the desired low level at 127, Gp is switched off rapidly and completely. When it is concluded that Gp is ‘almost’ switched off after 127, Gn is switched on rapidly.
A consequence of this method of actively looking at the voltage and current at the output is that, when the output has changed state, the corresponding output transistor can be switched on completely and fast. Using this method the parasitic currents in the diodes are much smaller in time and amplitude.
In order to implement the method of the present invention, it is, as described above, necessary to monitor the output level OUT. In view of the timescales involved, this need to be done with a fast sense comparator. One suitable fast sense comparator would be a fast sense comparator of the integrator type 105, as is shown in
For the avoidance of doubt, there are four possible situations: 1—transition Low to High with current into the output; 2—transition Low to High with current out of the output; 3—transition High to Low with current into the output; and 4—transition High to Low with current out of the output.
Situations 1 and 4 are very similar but ‘upside down’. The same is true for situation 2 and 3. Accordingly, for reasons of clarity and conciseness, in the present invention only two cases (2 and 4) are considered in detail. The invention is however envisaged to cover all four situations, as would be readily appreciated by the skilled man.
It is of course to be understood that the invention is not to be restricted to the details of the above embodiment which is described by way of example only.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0722730.9 | Nov 2007 | GB | national |
