BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 schematically illustrates a circuit including a power-gated subsystem and a permanently-powered subsystem with a clamp circuit therebetween;
FIG. 2 schematically illustrates at a logic gate level one example form of the clamp circuit of FIG. 2;
FIG. 3 schematically illustrates at a transistor level one example form of the clamping circuit of FIG. 2;
FIG. 4 illustrates at a transistor level an output driver circuit in accordance with a first example embodiment of the present technique; and
FIG. 5 schematically illustrates at a transistor level an output driver circuit in accordance with a second example embodiment of the present technique.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 4 illustrates an output driver circuit 18, which typically may form a standard cell to be included within an integrated circuit, such as a system-on-chip integrated circuit. This output driver circuit 18 is provided between blocks of circuits where one of the blocks is to be selectively powered down. It is desired to control an output generated by the powered down block and supplied as an input to a block which remains powered at a fixed level so as to avoid undesired and unpredictable behaviour within the active circuits to which the signal is supplied. The output driver circuit 18 is formed of a control circuit 20 and an output buffer 22. The output buffer 22 is in the form of two buffer transistors 24, 26 forming an inverter (a pullup transistor 24 and a pulldown transistor 26. These buffer transistors 24, 26 are high drive strength (high drive current) transistors chosen to be fast and powerful and accordingly typically having relatively high leakage currents. Such transistors 24, 26 are desirable for use with signals which are on a critical path. It will be appreciated that a variety of output driver circuit 18 designs could be provided with respective differing strengths of transistors 24, 26 used for the output buffer 22 to suit the particular requirements of the signal being buffered (e.g. there would be no need to use high strength transistors 24, 26 when the circuit concerned was not on a critical path and would have no performance limiting impact should weaker and lower leakage transistors be used.
The control circuit 20 includes a NAND-2 gate and is formed of four transistors 28, 30, 32, 34. The transistors 32 and 34 are controlled by an active low nCLAMP signal which signals that the output driver circuit 18 should be placed into its clamping mode. In this clamping mode the transistors 28 and 30 are isolated from the VSS line by the transistor 32 and the transistor 34 is switched on thereby generating a control signal on line 36 which is high and is supplied to the input gates (respectively a first gate input and a second gate input) of the transistors 24, 26 of the output buffer 22. This control signal is active high in that it switches on the transistor 26 and switches off the transistor 24. The virtual power supply to the output buffer on the signal line VVDD can then be powered down. The control signal on line 36 will remain high and accordingly the transistor 26 will remain conductive and the output of the output buffer 22 clamped low even-though the buffer power supply on the VVDD line is not connected.
In the operating mode, the clamping signal nCLAMP is high such that transistor 32 is switched on and transistor 34 is switched off. In this operating mode, the transistors 28 and 30 serve to supply a signal on line 36 to the gate of the transistors 24 and 26 of the output buffer 22 which is dependent upon the input signal IN. In this operating mode, the output driver circuit 18 serves as a normal buffer. The transistors 28 and 30 serve to invert the input signal and this is inverted again by the transistors 24 and 26 such that a non-inverted buffered output is produced. The dotted line in FIG. 4 shows the control path in the clamping mode by which the transistor 26 is held conductive and so reliably serves as a clamping transistor to clamp the output of the output driver circuit low.
FIG. 5 schematically illustrates another example embodiment. In this embodiment, the output driver circuit 38 is composed of a control circuit 40 and an output buffer 42. A common power supply rail VDD is coupled to both the control circuit 40 and the output buffer 42. An isolation gate 44 responsive to a sleep signal nSLEEP (which can also power down the power-gated subsystem 2) is disposed between an N-type transistor 46 of the output buffer 42 and the ground VSS (or virtual ground) line. A P-type transistor 48 completes the output buffer 42. Each of the transistors 44, 46 and 48 is a high strength, high current transistor suitable for use within an output driver circuit carrying a critical path related signal.
The control circuit 40 is similar to that illustrated in FIG. 4 with the addition of controlling a further clamping control transistor 50 within the output buffer 42, which serves as a pulldown transistor. The control signal on line 52, which is generated when in the clamping mode and serves to hold the transistor 46 conductive, also serves to hold the further clamping control transistor 50 conductive. The further clamping control transistor 50 is coupled to the output signal from the output buffer 42 and discharges this to VSS even though the isolation gate 44 may have isolated the output buffer 42 from the virtual ground level VSS. The dotted line in FIG. 5 shows the control path which serves to ensure that the output from the output driver circuit 38 is clamped low.
Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.
Patent Application
20080061848
