Patent Grant
9401678
The embodiments described herein relate to a power management system for delivering current to a linear RF power amplifier. More particularly, the embodiments relate to the use of a pseudo-envelope tracker in a power management system of mobile communications equipment.
Next-generation mobile devices are morphing from voice-centric telephones to message and multimedia-based “smart” phones that offer attractive new features. As an example, smart phones offer robust multimedia features such as web-browsing, audio and video playback and streaming, email access and a rich gaming environment. But even as manufacturers race to deliver ever more feature rich mobile devices, the challenge of powering them looms large.
In particular, the impressive growth of high bandwidth applications for radio frequency (RF) hand-held devices has led to increased demand for efficient power saving techniques to increase battery life. Because the power amplifier of the mobile device consumes a large percentage of the overall power budget of the mobile device, various power management systems have been proposed to increase the overall power efficiency of the power amplifier.
As an example, some power management systems may use a VRAMP power control voltage to control the voltage presented on a power amplifier collector of a linear RF power amplifier. As another example, other power management schemes may use a buck converter power supply and a class AB amplifier in tandem to provide power to the linear RF power amplifier.
Even so, there remains a need to further improve the power efficiency of mobile devices to provide extended battery life. As a result, there is a need to improve the power management system of mobile devices.
A switch mode power supply converter, a parallel amplifier, and a parallel amplifier output impedance compensation circuit are disclosed. The switch mode power supply converter provides a switching voltage and generates an estimated switching voltage output, which is indicative of the switching voltage. The parallel amplifier generates a power amplifier supply voltage at a power amplifier supply output based on a combination of a VRAMP signal and a high frequency ripple compensation signal. The parallel amplifier output impedance compensation circuit provides the high frequency ripple compensation signal based on a difference between the VRAMP signal and the estimated switching voltage output.
In one embodiment of the parallel amplifier output impedance compensation circuit, the parallel amplifier output impedance compensation circuit compensates for a non-ideal output impedance of the parallel amplifier by providing the combination of the VRAMP signal and a high frequency ripple compensation signal. In one embodiment of the parallel amplifier output impedance compensation circuit, the combination of the VRAMP signal and the high frequency ripple compensation signal is based on pre-filtering the VRAMP signal to equalize the overall frequency response of the switch mode power supply converter and the parallel amplifier to provide a proper transfer function of the switch mode power supply converter and the parallel amplifier.
Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.
The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
A switch mode power supply converter, a parallel amplifier, and a parallel amplifier output impedance compensation circuit are disclosed. The switch mode power supply converter provides a current to a power amplifier supply output via an inductor. The parallel amplifier generates a power amplifier supply voltage at the power amplifier supply output based on a compensated VRAMP signal. The parallel amplifier output impedance compensation circuit compensates for a non-ideal output impedance of the parallel amplifier based on a combination of a VRAMP signal and a high frequency ripple compensation signal. The high frequency ripple compensation signal is based on a difference between the VRAMP signal and an estimated switching voltage output, which is provided by the switch mode power supply converter.
In one embodiment of the parallel amplifier output impedance compensation circuit, the combination of the VRAMP signal and the high frequency ripple compensation signal is based on pre-filtering the VRAMP signal to equalize the overall frequency response of the switch mode power supply converter and the parallel amplifier to provide a proper transfer function of the switch mode power supply converter and the parallel amplifier.
The multi-level charge pump buck converter 12 may include a supply input 24, which is configured to receive a direct current (DC) voltage, VBAT, from a battery 20, and a switching voltage output 26, which is configured to provide a switching voltage, VSW. The switching voltage output 26 may be coupled to the power amplifier supply output 28 by the power inductor 16, where the power inductor 16 couples to the bypass capacitor 19 to form an output filter 29 for the switching voltage output 26 of the multi-level charge pump buck converter 12. The power inductor 16 provides an inductor current, ISW_OUT, to the power amplifier supply output 28. The parallel amplifier circuit 14 may include a parallel amplifier supply input 30, which is configured to receive the DC voltage, VBAT, from the battery 20, a parallel amplifier output 32A, a first control input 34, which is configured to receive a VRAMP signal, and a second control input configured to receive the power amplifier supply voltage, VCC. The parallel amplifier output 32A of the parallel amplifier circuit 14 may be coupled to the power amplifier supply voltage VCC, by the coupling circuit 18. A parallel amplifier output voltage, VPARA_AMP, is provided by the parallel amplifier circuit 14 via the parallel amplifier output 32A.
As an example, the parallel amplifier circuit 14 may generate the parallel amplifier output voltage, VPARA_AMP, based on the difference between the VRAMP signal and the power amplifier supply voltage, VCC. Thus, the VRAMP signal may represent either an analog or digital signal that contains the required supply modulation information for a power amplifier collector of the linear RF power amplifier 22. Typically, the VRAMP signal is provided to the parallel amplifier circuit 14 as a differential analog signal to provide common mode rejection against any noise or spurs that could appear on this signal. The VRAMP signal may be a time domain signal, VRAMP(t), generated by a transceiver or modem and used to transmit radio frequency (RF) signals. For example, the VRAMP signal may be generated by a digital baseband processing portion of the transceiver or modem, where the digital VRAMP signal, VRAMP_DIGITAL, is digital-to-analog converted to form the VRAMP signal in the analog domain. In some embodiments, the “analog” VRAMP signal is a differential signal. The transceiver or a modem may generate the VRAMP signal based upon a known RF modulation Amp(t)*cos(2*pi*fRF*t+Phase(t)). The VRAMP signal may represent the target voltage for the power amplifier supply voltage, VCC, to be generated at the power amplifier supply output 28 of the pseudo-envelope follower power management system 10A, where the pseudo-envelope follower power management system 10A provides the power amplifier supply voltage, VCC, to the linear RF power amplifier 22. Also the VRAMP signal may be generated from a detector coupled to the linear RF power amplifier 22.
For example, the parallel amplifier circuit 14 includes the parallel amplifier output 32A that provides the parallel amplifier output voltage, VPARA_AMP, to the coupling circuit 18. The parallel amplifier output 32A sources a parallel amplifier circuit output current, IPAWA_OUT, to the coupling circuit 18. The parallel amplifier circuit 14, depicted in
In some embodiments of the pseudo-envelope follower power management system 10A, depicted in
A pseudo-envelope follower power management system 10A, depicted in
The parallel amplifier circuit 14A may further include an open loop assist circuit 39 configured to receive a feed forward control signal 38, VSWITCHER, the scaled parallel amplifier output current estimate, IPARA_AMP_SENSE, and the VRAMP signal. In response to the feed forward control signal 38, VSWITCHER, the scaled parallel amplifier output current estimate, IPARA_AMP_SENSE, and the VRAMP signal; the open loop assist circuit 39 may be configured to generate an open loop assist current, IASSIST. The open loop assist current, IASSIST, may be provided to the parallel amplifier output 32A. The parallel amplifier output current, IPARA_AMP, generated by the parallel amplifier 35 and the open loop assist circuit current, IASSIST, generated by the open loop assist circuit 39, may be combined to form the parallel amplifier circuit output current, IPAWA_OUT, of the parallel amplifier circuit 14A. The parallel amplifier circuit 14A may further include a VOFFSET loop circuit 41 configured to generate a threshold offset current 42, ITHRESHOLD_OFFSET. The threshold offset current 42, ITHRESHOLD_OFFSET, may be provided from the parallel amplifier circuit 14A as a feedback signal to the multi-level charge pump buck converter 12A. The VOFFSET loop circuit 41 may be configured to provide a threshold offset current 42, ITHRESHOLD_OFFSET, as an estimate of the magnitude of the offset voltage, VOFFSET, appearing across the coupling circuit 18. In those cases where the coupling circuit is a wire trace such that the offset voltage, VOFFSET, is always zero volts, the parallel amplifier circuit 14A may not provide the threshold offset current 42, ITHRESHOLD_OFFSET, to the multi-level charge pump buck converter 12A.
Another example is the pseudo-envelope follower power management system 10B depicted in
The generation of the parallel amplifier circuit output current estimate 40, IPAWA_OUT_EST, depicted in
Returning to
As further depicted in
In addition, the parallel amplifier circuit 14A, depicted in
For example, the switcher control circuit 52 may use the parallel amplifier circuit output current estimate 40, IPAWA_OUT_EST, the threshold offset current 42, ITHRESHOLD_OFFSET, and/or a combination thereof to determine the magnitude of the voltage provided by the switching voltage, VSW, from the multi-level charge pump circuit 56.
Otherwise, when the input voltage, VIN, at the input node 642A is sufficiently high such that the input voltage, VIN is substantially equal to a logic high threshold voltage, the first PFET 644, PFET1, is configured to be in a non-conducting state and the first NFET 646, NFET1, is configured to be in a conducting state. When the first NFET 646, NFET1, is turned on, the second fixed current source 650 sinks a fixed bias current, IBIAS, from the first fixed delay capacitor 652 to generate the first fixed capacitor current, IC1, of opposite magnitude than when the first fixed delay capacitor 652 is being charged by the first fixed current source 648. Assuming that most of the fixed bias current, IBIAS, sunk through the first NFET 646, NFET1 by the second fixed current source 650 is used to discharge the first fixed delay capacitor 652, the magnitude of the first fixed capacitor current, IC1, is substantially equal to the magnitude of the fixed bias current, IBIAS, sunk by the second fixed current source 650 through the first NFET 646, NFET1. As the first fixed delay capacitor 652 is discharged, the first delay voltage, VD1, continues to decrease and eventually falls below a voltage level that is less than a logic low threshold voltage that may trigger an action by the variable delay circuitry 640A.
Because the first fixed current source 648 and the second fixed current source 650 each source and sink, respectively, a current equal to the fixed bias current, IBIAS, the first fixed delay capacitor 652 is charged and discharged at the same rate. The first fixed delay time associated with the fixed delay circuitry 635 is due to the generation of the first delay voltage, VD1. Because the current sourced by the first fixed current source 648 and sunk by the second fixed current source 650 are substantially equal, the rise time and fall time of the first delay voltage, VD1, are substantially equal. Effectively, the first fixed delay time is due to the time required to propagate the digital logic state represented by the input voltage, VIN, through the fixed delay circuitry 635 and provide the first delay voltage, VD1, that represents a digital logic state to an input stage 654 of the variable delay circuitry 640A.
The variable delay circuitry 640A includes the input stage 654 having an input node 654A coupled to the drain of the first PFET 644, PFET1, the drain of the first NFET 646, NFET1, and the first fixed delay capacitor 652. The variable delay circuitry 640A further includes a second PFET 656, PFET2, a second NFET 658, NFET2, a first variable current source 660, a second variable current source 662, and a second fixed delay capacitor 664. The second fixed delay capacitor 664 has a second delay capacitance, CDELAY2.
The input stage 654 of the variable delay circuitry 640A is formed by coupling the gate of the second PFET 656, PFET2, and the gate of the second NFET 658, NFET2, to the input node 654A. The variable delay circuitry 640A is further formed by coupling the first variable current source 660 between the circuit supply voltage, VDD, and the source of the second PFET 656, PFET2, such that the first variable current source 660 may provide a variable bias current, IBIAS_VAR, to the source of the second PFET 656, PFET2 when the second PFET 656, PFET2, is in a conducting state. In addition, the second variable current source 662 is coupled between the source of the second NFET 658, NFET2, and ground such that the second variable current source 662 may sink a variable bias current, IBIAS_VAR, from the source of the second NFET 658, NFET2, when the second NFET 658, NFET2, is in a conducting state. The second fixed delay capacitor 664 is coupled between ground and the drain of the second PFET 656, PFET2, and the drain of the second NFET 658, NFET2.
In addition, the variable delay circuitry 640A further includes an output buffer stage 666 that includes a third PFET 668, PFET3 operably coupled to a third NFET 670, NFET3 to form an input node 666A. The output buffer stage 666 includes an input node 666A formed by coupling the gate of the third PFET 668, PFET3, to the gate of the third NFET 670, NFET3. The source of the third PFET 668, PFET3, is coupled to the circuit supply voltage, VDD. The source of the third NFET 670, NFET3, is coupled to ground. The output buffer stage 666 further includes an output buffer stage output 672 that corresponds to the output of the programmable delay circuitry 432A. The output buffer stage output 672 may be formed by coupling the drain of the third PFET 668, PFET3, to the drain of the third NFET 670, NFET3. The output buffer stage 666 is configured to generate an output voltage, VOUT, at the output buffer stage output 672. Generally, the output voltage, VOUT, generated by the output buffer stage 666 at the output buffer stage output 672 will represent either a digital logic high state or a digital logic low state. For example, when the output voltage, VOUT, is substantially equal to the circuit supply voltage, VDD, the output voltage, VOUT, represents a digital logic high state. When the output voltage, VOUT, is substantially equal to the ground voltage, the output voltage, VOUT, represents a digital logic low state.
During operation of the variable delay circuitry 640A, a second delay voltage, VD2, increases as the second fixed delay capacitor 664 is charged and decreases as the second fixed delay capacitor 664 is discharged. When the second delay voltage, VD2, is sufficiently low such that the second delay voltage, VD2, is substantially equal to or below a logic low threshold voltage, the third PFET 668, PFET3, is configured to be in a conducting state and the third NFET 670, NFET3 is configured to be in a non-conducting state. In this case, when the third PFET 668, PFET3, is turned on, the output buffer stage output 672 is coupled to the circuit supply voltage, VDD, via the third PFET 668, PFET3. As a result, the output voltage, VOUT, at the output buffer stage output 672 is substantially equal to the circuit supply voltage, VDD, and the output voltage, VOUT, represents a digital logic high state.
However, when the second delay voltage, VD2, is sufficiently high such that the second delay voltage, VD2, is substantially equal to or above a logic high threshold voltage, the third PFET 668, PFET3, is configured to be in a non-conducting state and the third NFET 670, NFET3 is configured to be in a conducting state. In this case, the third NFET 670, NFET3, is turned on and the output buffer stage output 672 is coupled to ground via the third NFET 670, NFET3. As a result, the output voltage, VOUT, at the output buffer stage output 672 is substantially equal to the ground voltage, and the output voltage, VOUT, represents a digital logic low state.
During normal operation, when the first delay voltage, VD1, at the input node 654A is sufficiently low to be equal to or lower than a logic low threshold voltage, the second PFET 656, PFET2, is configured to be in a conducting state and the second NFET 658, NFET2, is configured to be in a non-conducting state. Accordingly, when the second PFET 656, PFET2, is turned on, the first variable current source 660 sources the variable bias current, IBIAS_VAR, through the second PFET 656, PFET2, to charge the second fixed delay capacitor 664 with a second fixed capacitor current, IC2. Assuming that most of the variable bias current, IBIAs_VAR, from the first variable current source 660 is used to charge the second fixed delay capacitor 664, the second fixed capacitor current, IC2 is substantially equal to the variable bias current, IBIAS_VAR, provided by the first variable current source 660. As the second fixed delay capacitor 664 is charged by the variable bias current, IBIAS_VAR, the magnitude of the second delay voltage, VD2, continues to increase and eventually rises above a voltage level that is greater than the logic high threshold voltage that may trigger an action by the output buffer stage 666. For example, once the second delay voltage, VD2, reaches or exceeds the logic high threshold voltage, the output buffer stage 666 will trigger so as to generate an output voltage, VOUT that represents a digital logic low state.
Otherwise, during normal operation, when the first delay voltage, VD1, at the input node 654A is sufficiently high to be equal to exceed a logic high threshold voltage, the second PFET 656, PFET2, is configured to be in a non-conducting state and the second NFET 658, NFET2, is configured to be in a conducting state. Accordingly, when the second NFET 658, NFET2, is turned on, the second variable current source 662 sinks the variable bias current, IBIAS_VAR, through the second NFET 658, NFET2, to discharge the second fixed delay capacitor 664 with the second fixed capacitor current, IC2, by removing charge from the second fixed delay capacitor 664. Assuming that most of the variable bias current, IBIAS_VAR, sunk by the second variable current source 662 is used to discharge the second fixed delay capacitor 664, the magnitude of the second fixed capacitor current, IC2, that removes charge from the second fixed delay capacitor 664 is substantially equal to the variable bias current, IBIAS_VAR, sunk by second variable current source 662. As the second fixed delay capacitor 664 is discharged by the variable bias current, IBIAS_VAR, the magnitude of the second delay voltage, VD2, continues to decrease or eventually fall below a voltage level that is less than the logic low threshold voltage that may trigger an action by the output buffer stage 666. For example, once the second delay voltage, VD2, reaches or falls below the logic low threshold voltage, the output buffer stage 666 will trigger, and the output buffer stage 666 will generate an output voltage, VOUT, that represents a digital logic high state.
The variable delay time provided by the variable delay circuitry 640A is created by the time period required to charge and discharge the second fixed delay capacitor 664 with the variable bias current, IBIAS_VAR, where the variable bias current, IBIAS_VAR, varies in magnitude. As depicted in
The controller 50 (
As depicted in
As discussed relative to the programmable delay circuitry 432A, the operational parameters of the programmable delay circuitry 432B may be configured by the controller 50 (
Continuing with the description of the programmable delay circuitry 432B, depicted in
As discussed above, the variable delay circuitry 640B is similar to the variable delay circuitry 640A except that the variable delay circuitry 640B replaces the first variable current source 660, the second variable current source 662, and the second fixed delay capacitor 664 of the variable delay circuitry 640A, with the third fixed current source 674, the fourth fixed current source 678, and the variable delay capacitor 680, respectively. Thus, the variable delay circuitry 640B includes the input stage 654 having the input node 654A, the second PFET 656, PFET2, the second NFET 658, NFET2, the third fixed current source 674, the fourth fixed current source 678, and the variable delay capacitor 680 having a variable delay capacitance, CDELAY_VAR, where the controller 50 (not shown) may be configured to change the capacitance value of the variable delay capacitance, CDELAY_VAR.
Similar to the variable delay circuitry 640A, the variable delay circuitry 640B also includes the output buffer stage 666 that includes the third PFET 668, PFET3, and the third NFET 670, NFET3. The output buffer stage 666 includes the input node 666A formed by coupling the gate of the third PFET 668, PFET3, to the gate of the third NFET 670, NFET3. The source of the third PFET 668, PFET3, is coupled to the circuit supply voltage, VDD. The source of the third NFET 670, NFET3, is coupled to ground. The output buffer stage output 672 of the output buffer stage 666, which is also the output of the programmable delay circuitry 432B, is formed by coupling the drain of the third PFET 668, PFET3, to the drain of the third NFET 670, NFET3. The output buffer stage 666 is configured to generate an output voltage, VOUT, at the output buffer stage output 672. For example, as will be discussed, a third delay voltage, VD3, across the variable delay capacitor 680 increases and decreases at a rate that depends on the capacitance value of the variable delay capacitance, CDELAY_VAR, of the variable delay capacitor 680 and the magnitude of a variable delay capacitor current, IC_VAR, that charges and discharges the variable delay capacitor 680. When the third delay voltage, VD3, across the variable delay capacitor 680 is sufficiently low such that the third delay voltage, VD3 is substantially equal to a logic low threshold voltage, the third PFET 668, PFET3, is configured to be in a conducting state and the third NFET 670, NFET3, is configured to be in a non-conducting state. In this case, when the third PFET 668, PFET3, is turned on, the output buffer stage output 672 is coupled to the circuit supply voltage, VDD. As a result, the output voltage, VOUT, at the output buffer stage output 672 is substantially equal to the circuit supply voltage, VDD, when the third PFET 668, PFET3, is in the conducting state. However, when the third delay voltage, VD3, across the variable delay capacitor 680 is sufficiently high such that the third delay voltage, VD3 is substantially equal to a logic high threshold voltage, the third NFET 670, NFET3, is configured to be in a conducting state and the third PFET 668, PFET3, is configured to be in a non-conducting state. In this case, when the third NFET 670, NFET3, is turned on, the output buffer stage output 672 is coupled to ground. As a result, the output voltage, VOUT, at the output buffer stage output 672 is substantially equal to the ground voltage when the third NFET 670, NFET3, is turned on. In this way, the output voltage, VOUT, at the output buffer stage output 672 toggles between a digital logic high state and a logic log state.
Continuing with the description of the variable delay circuitry 640B, depicted in
During normal operation, when the first delay voltage, VD1, at the input node 654A is sufficiently low, the second PFET 656, PFET2, is configured to be in a conducting state. At the same time, when the first delay voltage, VD1, at the input node 654A is sufficiently low to turn on the second PFET 656, PFET2, the second NFET 658, NFET2, is configured to be in a non-conducting state. When the second PFET 656, PFET2, is turned on, the third fixed current source 674 sources a second fixed bias current, IBIAS2, to charge the variable delay capacitor 680. The second fixed bias current, IBIAS2, charges the variable delay capacitor 680 with a variable delay capacitor current, IC_VAR. The rate of change in the third delay voltage, VD3, across the variable delay capacitor 680 depends upon the capacitance value of the variable delay capacitance, CDELAY_VAR, of the variable delay capacitor 680 and the magnitude of the variable delay capacitor current, I-C_VAR. Assuming that most of the second fixed bias current, IBIAS2, from the third fixed current source 674 is used to charge the variable delay capacitor 680, the variable delay capacitor current, IC_VAR, is substantially equal to the second fixed bias current, IBIAS2. As the variable delay capacitor 680 is charged by the second fixed bias current, IBIAS2, the magnitude of the third delay voltage, VD3, increases. As described above, after the third delay voltage, VD3, increases to a logic high threshold voltage, the third PFET 668, PFET3, is turned off and the third NFET 670, NFET3, is turned on, which changes the output voltage, VOUT, at the output buffer stage output 672 to be substantially equal to ground.
Otherwise, when the first delay voltage, VD1, at the input node 654A is sufficiently high, the second NFET 658, NFET2, is configured to be in a conducting state and the fourth fixed current source 678 is permitted to sink a second fixed bias current, IBIAS2, in order to discharges the variable delay capacitor 680. At the same time, when the first delay voltage, VD1, at the input node 654A is sufficiently low to turn on the second NFET 658, NFET2, the second PFET 656, PFET2, is configured to be in a non-conducting state. When the second NFET 658, NFET2, is turned on, the fourth fixed current source 678 sinks the second fixed bias current, IBIAS2, to discharge the variable delay capacitor 680 with a current substantially equal to IC_VAR. The rate of change in the third delay voltage, VD3, across the variable delay capacitor 680 depends upon the capacitance value of the variable delay capacitance, CDELAY_VAR, of the variable delay capacitor 680 and the magnitude of the variable delay capacitor current, IC_VAR. Assuming that most of the second fixed bias current, IBIAS2, from the fourth fixed current source 678 is used to discharge the variable delay capacitor 680, the variable delay capacitor current, IC_VAR, is substantially equal to the second fixed bias current, IBIAS2. As the variable delay capacitor 680 is discharged by the second fixed bias current, IBIAS2, the magnitude of the third delay voltage, VD3, decreases. As described above, after the third delay voltage, VD3, decreases to a logic low threshold voltage, the third NFET 670, NFET3, is turned off and the third PFET 668, PFET3, is turned on, which changes the output voltage, VOUT, at the output buffer stage output 672 to be substantially equal to the circuit supply voltage, VDD.
The variable delay time provided by the variable delay circuitry 640B is created by the time period required to charge and discharge the variable delay capacitor 680, which depends upon the capacitance value of the variable capacitance, CDELAY_VAR, and the magnitude of the second fixed bias current, IBIAS2. Because the variable delay capacitor 680 is either charged or discharged using a current substantially equal to the second fixed bias current, IBiAS2, either sourced by the third fixed current source 674 or sunk by the fourth fixed current source 678, the variable time period required for the third delay voltage, VD3, to increase to the logic high threshold voltage or decrease to the logic high threshold voltage used to trigger the operation of the operation of the output buffer stage 666 is dependent upon the variable capacitance, CDELAY_VAR of the variable delay capacitor 680.
As previously discussed, the controller 50 (
Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.
In one embodiment of the programmable delay circuitry, the correction start voltage circuit helps stabilize the variable time delay by reducing disturbances in a voltage across the variable delay capacitor when certain transistor elements in the programmable delay circuitry transition to be in a conducting state. Further, the correction start voltage circuit may improve accuracy of the variable time delay by reducing transition times of certain transistor elements in the programmable delay circuitry.
In one embodiment of the programmable delay circuitry, the programmable delay circuitry further includes a voltage divider circuit and a bias current and mirror circuit. The voltage divider circuit is coupled to the bias current and mirror circuit. The bias current and mirror circuit is coupled to the variable delay circuitry. The voltage divider circuit and the bias current and mirror circuit are configured to reduce changes in the variable time delay due to changes in a voltage level of a circuit supply voltage, which is provided to the programmable delay circuitry.
The programmable delay circuitry 432C depicted in
In addition, total delay time provided by the programmable delay circuitry 432C may include a fixed delay time and a variable delay time, where the variable delay time may be configured based on the programmable delay parameter(s), as discussed above. In addition, the fixed delay time may be sub-divided and distributed between an input buffer circuit 682 and variable delay circuitry 684.
As depicted in
The input buffer circuit 682 may further include a second input buffer circuit 698 operably coupled to the first input buffer output at the first voltage node 696. The second input buffer circuit 698 may include a second PFET 700, PFET2, and a second NFET 702, NFET2. The gate of the second PFET 700, PFET2, and the gate of the second NFET 702, NFET2, may be coupled to the drain of the first PFET 692, PFET1, and the drain of the first NFET 694, NFET2, at the first voltage node 696. The source of the second PFET 700, PFET2, may be coupled to the circuit supply voltage, VDD. The source of the second NFET 702, NFET2, may be coupled to ground. The drain of the second PFET 700, PFET2, and the drain of the second NFET 702, NFET2, may be coupled to form a second input buffer output at a second voltage node 704.
During operation of the first input buffer circuit 690, when the input voltage, VIN, at the first input buffer input 690A is sufficiently low such that the input voltage, VIN is substantially equal to or less than a logic low threshold voltage, the first PFET 692, PFET1, is configured to be in a conducting state and couples the circuit supply voltage, VDD, to the first voltage node 696. As a result, the voltage level at the first voltage node 696 is substantially equal to the circuit supply voltage, VDD, and the first input buffer circuit 690 provides an output voltage level representative of a digital logic high state at the first voltage node 696. In addition, the first NFET 694, NFET1, is configured to be in a non-conducting state when the input voltage, VIN, at the first input buffer input 690A is sufficiently low such that the input voltage, VIN is substantially equal to or less than the logic low threshold voltage.
However, when the input voltage, VIN, at the first input buffer input 690A is sufficiently high such that the input voltage, VIN is substantially equal to or greater than a logic high threshold voltage, the first NFET 694, NFET1, is configured to be in a conducting state and couples the first voltage node 696 to ground. As a result, the voltage level at the first voltage node 696 is substantially equal to ground, and the first input buffer circuit 690 provides an output voltage level representative of a digital logic low state at the first voltage node 696. In addition, the first PFET 692, PFET1, is configured to be in a non-conducting state when the input voltage, VIN, at the first input buffer input 690A is sufficiently high such that the input voltage, VIN is substantially equal to or greater than the logic high threshold voltage.
In a similar fashion, the operation of the second input buffer circuit 698 is dependent on the voltage level at the first voltage node 696, which is coupled to the first input buffer output of the first input buffer circuit 690. Accordingly, when the first input buffer circuit 690 provides a digital logic low state at the first voltage node 696 such that the voltage level at the first voltage node 696 is substantially equal to or less than the logic low threshold voltage, the second PFET 700, PFET2, is configured to be in a conducting state and couples the circuit supply voltage, VDD, to the second voltage node 704. As a result, the voltage level at the second input buffer circuit 698 is substantially equal to the circuit supply voltage, VDD, and the second input buffer circuit 698 provides a digital logic high state at the second voltage node 704. In addition, the second NFET 702, NFET2, is configured to be in a non-conducting state when the first input buffer circuit 690 provides an output voltage level representative of a digital logic low state at the first voltage node 696.
However, in a similar fashion as the operation of the first input buffer circuit 690, when the first input buffer circuit 690 provides a digital logic high state at the first voltage node 696 such that the voltage level at the first voltage node 696 is substantially equal to or higher than the logic low threshold voltage, the second NFET 702, NFET2, is configured to be in a conducting state and couples the second voltage node 704 to ground. As a result, the voltage level at the second input buffer circuit 698 is substantially equal to the ground voltage, and the second input buffer circuit 698 provides a digital logic low state at the second voltage node 704. In addition, the second PFET 700, PFET2, is configured to be in a non-conducting state when the first input buffer circuit 690 provides an output voltage level representative of a digital logic high state at the first voltage node 696
It will be appreciated that the propagation time of the digital logic level signal, represented by the input voltage, VIN, through the input buffer circuit may be considered as a first portion of a fixed delay provided by the programmable delay circuitry 432C and is a function of the switching time of the transistors. The first portion of the fixed delay time provided by the input buffer circuit 682 depends upon the switching time of the respective first input buffer circuit 690 and the second input buffer circuit 698. In some alternative embodiments of the programmable delay circuitry 432C, additional input buffer circuits, (not depicted in
The variable delay circuitry 684 includes an input stage 706 including a third PFET 708, PFET3, a third NFET 710, NFET3, a fourth PFET 714, PFET4, a fourth NFET 716, NFET4, a fifth PFET 718, PFET5, and a fifth NFET 720, NFET5. As will be explained, a portion of the input stage 706 of the variable delay circuitry 684 may include a correction start voltage circuit 712 that is formed by the interconnections of the third PFET 708, PFET3 and the third NFET 710, NFET3, to the fourth PFET 714, PFET4, and the fourth NFET 716, NFET4. The variable delay circuitry 684 further includes a variable delay capacitor 722. In some embodiments, the variable delay capacitor 722 may be configured as a programmable capacitor array.
As depicted in
For example, in some embodiments of the variable delay circuitry 684, the variable delay capacitor 722 may be configured as a programmable capacitor array. The programmable capacitor array may include multiple capacitors, where each of the capacitors is arranged in series with a switch element. Each switch element may have a switch state (open or closed) that may be controlled by the controller 50 such that the effective capacitance of the programmable capacitor array has a desired effective capacitance. In some embodiments, the programmable capacitor array may be a linear capacitor array, where each of the capacitors has the same value. In other embodiments, the programmable capacitor array may be a binary weighted capacitor array. The controller 50 may adjust the effective capacitance of the programmable capacitor array by controlling the switch state (open or closed) of each switch to combine different combinations of the multiple capacitors in parallel. Alternatively, the variable delay capacitor 722 may be a programmable varactor configured to be controlled by the controller 50. Depending on the topology and type of programmable capacitor, for example, the controller 50 may govern the effective capacitance of the programmable varactor by changing the distance between the two parallel plates that form the varactor or a voltage applied across the terminals of the varactor.
The variable delay circuitry 684 may further include an output buffer stage 726. By way of example, and not by way of limitation, the output buffer stage 726 depicted in
However, similar to the input buffer circuit, some alternative embodiments of the variable delay circuitry 684 may include an embodiment of the output buffer stage 726 that includes multiple levels of output buffering in order to provide additional isolation between the interior circuitry of the variable delay circuitry 684 and the digital logic level signal to be generated by the programmable delay circuitry 432C. For example, some alternative embodiments of the variable delay circuitry 684 may include additional output buffering to improve the drive level at the output of the programmable delay circuitry 432C.
The operation of the output buffer stage 726 depends upon the voltage level at the third voltage node 724. When the voltage level at the third voltage node 724 is equal to or less than the logic low threshold voltage such that the sixth PFET 728, PFET6, is turned on and in the saturation state, the output buffer output 732 is effectively coupled to the circuit supply voltage, VDD, through the sixth PFET 728, PFET6. Simultaneously, the sixth NFET 730, NFET6, is configured to be turned off when the sixth PFET 728, PFET6 is turned on. As a result, the output buffer stage 726 provides an output voltage, VOUT, substantially equal to the circuit supply voltage, VDD, which represents a digital logic high state. Thus, when the voltage level at the third voltage node 724 is equal to or less than the logic low threshold voltage such that the sixth PFET 728, PFET6 is turned, the output buffer stage 726 is triggered to transition from a digital logic low state to a digital logic low state at the output buffer output 732.
However, when the voltage level at the third voltage node 724 is equal to or greater than the logic high threshold voltage, such that the sixth NFET 730, NFET6, is turned on and in the saturation state, the output buffer output 732 is effectively coupled to the ground through the sixth NFET 730, NFET6. Simultaneously, the sixth PFET 728, PFET6, is configured to be turned off when the sixth NFET 730, NFET6 is turned on. As a result, the output buffer stage 726 provides an output voltage, VOUT, substantially equal to ground, which represents a digital logic low state. Thus, when the voltage level at the third voltage node 724 is equal to or greater than the logic high threshold voltage such that the sixth PFET 728, PFET6, is turned, the output buffer stage 726 is triggered to transition from a digital logic high state to a digital logic low state at the output buffer output 732.
The time period during which the digital logic level signal, represented by the voltage level at the third voltage node 724, propagates through the output buffer stage 726 may be a second portion of the fixed delay time provided by the programmable delay circuitry 432C. The second portion of the fixed delay time provided by the output buffer stage 726 depends on the switching time of the output buffer stage 726. Some alternative embodiments of the variable delay circuitry 684 may include additional output buffering. Accordingly, the propagation time through the output buffer stage of the variable delay circuitry 684 may be increased by addition of additional output buffering. Thus, the fixed delay time of the programmable delay circuitry 432C includes the first portion of the fixed delay time of the input buffer circuit 682 and the second portion of the fixed delay time of the output buffer stage 726.
Returning to the description of the variable delay circuitry 684 depicted in
Accordingly, the fixed delay time of the programmable delay circuitry 432C may further include a third portion of the fixed delay time, where the third portion of the fixed delay time is associated with the switching time of the fourth PFET 714, PFET4, and the switching time of the fourth NFET 716, NFET4.
As a result, when the voltage level on the second voltage node 704 is substantially equal to or less than the logic low threshold voltage such that the fourth PFET 714, PFET4, is in the conducting mode of operation (ON), the first bias current, IBIAS_1, passes through the fourth PFET 714, PFET4, pushes charge into the variable delay capacitor 722 to charge the variable delay capacitor 722. As the variable delay capacitor 722 is charged, the voltage across the variable delay capacitor 722, which is substantially equal to the voltage level on the third voltage node 724, increases. However, when the voltage level on the second voltage node 704 is substantially equal to or greater than the logic high threshold voltage such that the fourth NFET 716, NFET4, is in the conducting mode of operation (ON), the second bias current, IBIAS_2, sunk by the fifth NFET 720, NFET5, passes through the fourth NFET 716, NFET4, and pulls charge from the variable delay capacitor 722 to discharge the variable delay capacitor 722. As a result, the voltage across the variable delay capacitor 722, which is substantially equal to the voltage level on the third voltage node 724, falls.
The correction start voltage circuit 712 is formed by coupling the gate of the third PFET 708, PFET3 and the gate of the third NFET 710, NFET3, to the second voltage node 704, such that the gates of the third PFET 708, PFET3, the third NFET 710, NFET3, the fourth PFET 714, PFET4, and the fourth NFET 716, NFET4, are coupled. The source of the third PFET 708, PFET3, is coupled to the circuit supply voltage, VDD. The drain of the third PFET 708, PFET3, is coupled to the source of the fourth NFET 716, NFET4, and the drain of the fifth NFET 720, NFET5. The source of the third NFET 710, NFET3, is coupled to ground. The drain of the third NFET 710, NFET3, is coupled to the source of the fourth PFET 714, PFET4, and the drain of the fifth PFET 718, PFET5.
The correction start voltage circuit 712 is configured to provide a first known voltage level at the source of the fourth PFET 714, PFET4, while the fourth PFET 714, PFET4, is in the non-conducting state such that the voltage level present at the source of the fourth PFET 714, PFET4, is at the first known voltage level at the moment the fourth PFET 714, PFET4 transitions from the non-conducting state to the conducting state. In order to provide the first known voltage level at the source of the fourth PFET 714, PFET4, while the fourth PFET 714, PFET4, is in the non-conducting state, the third NFET 710, NFET3, is configured to be turned on when the while the fourth PFET 714, PFET4, is in the non-conducting state. As a result, the source of the fourth PFET 714, PFET4, is coupled to ground through the third NFET 710, NFET3. In the embodiment of the correction start voltage circuit 712 depicted in
In some embodiments of the correction start voltage circuit 712, the parasitic capacitance of the source of the fourth PFET 714, PFET4, the parasitic capacitance of the drain of the fifth PFET 718, PFET5, and/or a combination thereof is configured such that the voltage level present on the source of the fourth PFET 714, PFET4, remains at the first known voltage level momentarily at the moment the fourth PFET 714, PFET4 transitions from the non-conducting state to the conducting state. In other embodiments of the correction start voltage circuit 712, the parasitic capacitance of the drain of the third NFET 710, NFET3, may also be configured to improve the ability of the correction start voltage circuit 712 to provide the first known voltage on the source of the fourth PFET 714, PFET4, momentarily at the moment the fourth PFET 714, PFET4, transitions from the non-conducting state to the conducting state. In addition, the third NFET 710, NFET3 may be further configured to turn off just prior to or coincidentally with the fourth PFET 714, PFET4, transitioning from the non-conducting state to the conducting state. Otherwise, after the charge present in the parasitic capacitance(s) is discharged, the voltage level on the source of the fourth PFET 714, PFET4, is determined by the operational state of the fourth PFET 714, PFET4, and the first bias current, IBIAS_1, provided by the fifth PFET 718, PFET5.
In a similar fashion, the correction start voltage circuit 712 is configured to provide a second known voltage level at the source of the fourth NFET 716, NFET4, while the fourth NFET 716, NFET4, is in the non-conducting state such that the voltage level present at the source of the fourth NFET 716, NFET4, is at the second known voltage level at the moment the fourth NFET 716, NFET4 transitions from the non-conducting state to the conducting state. In order to provide the second known voltage level at the source of the fourth NFET 716, NFET4, while the fourth NFET 716, NFET4, is in the non-conducting state, the third PFET 708, PFET3, is configured to be turned on when the fourth NFET 716, NFET4, is in the non-conducting state. As a result, the source of the fourth NFET 716, NFET4, is coupled through the third PFET 708, PFET3, to the circuit supply voltage VDD. As a result, in the embodiment of the correction start voltage circuit 712 depicted in
In some embodiments of the correction start voltage circuit 712, the parasitic capacitance of the source of the fourth NFET 716, NFET4, the parasitic capacitance of the drain of the fifth NFET 720, NFET5, and/or a combination thereof is configured such that the voltage level present on the source of the fourth NFET 716, NFET4, remains at the second known voltage level momentarily at the moment the fourth NFET 716, NFET4 transitions from the non-conducting state to the conducting state. In other embodiments of the correction start voltage circuit 712, the parasitic capacitance of the drain of the third PFET 708, PFET3, may also be configured to improve the ability of the correction start voltage circuit 712 to provide the second known voltage on the source of the fourth NFET 716, NFET4, momentarily at the moment the fourth NFET 716, NFET4, transitions from the non-conducting state to the conducting state. In addition, the third PFET 708, PFET3 may be further configured to turn off just prior to or coincidentally with the fourth NFET 716, NFET4, transitioning from the non-conducting state to the conducting state. Otherwise, after the charge present in the parasitic capacitance(s) is discharged, the voltage level on the source of the fourth NFET 716, NFET4, is determined by the operational state of the fourth NFET 716, NFET4, and the second bias current, IBIAs_2, sunk by the fifth NFET 720, NFET5.
Advantageously, because the correction start voltage circuit 712 is configured to ensure the voltage level on the source of the fourth PFET 714, PFET4, is substantially equal to the first known voltage when the fourth PFET 714, PFET4, is in the non-conducting state and the voltage level on the source of the fourth NFET 716, NFET4, is substantially equal to the second known voltage when the fourth NFET 716, NFET4, is in the non-conducting state, the initial change in the voltage level at the third voltage node 724 that occurs as a result of charge stored in the capacitances associated with the source of the fourth PFET 714, PFET4, or the charge stored in the capacitances associated with the source of the fourth NFET 716, NFET4, (referred to as a state transition voltage charge) is predictable and substantially consistent. As a result, the state transition voltage charge may be controlled such that the voltage across the variable delay capacitor 722 is not substantially disturbed when either the fourth PFET 714, PFET4, or the fourth NFET 716, NFET4, transitions to be in the conducting state.
For example, as previously described, when the second input buffer circuit 698 provides a digital logic high state, the second input buffer provides an output voltage at the second voltage node 704 substantially equal to the circuit supply voltage, VDD. In this case, the gate of the fourth NFET 716, NFET4, is greater than the logic high threshold level. As a result, the fourth NFET 716, NFET4, turns on and discharges the variable delay capacitor 722 until the voltage level at the third voltage node 724 is substantially equal to ground. In addition, the third NFET 710, NFET3, of the correction start voltage circuit 712 is configured to turn on and couple the source of the fourth PFET 714, PFET4, to ground such that the charge stored on the source of the fourth PFET 714, PFET-4, is at a voltage level substantially equal to ground. As a result, the charge stored on the source of the fourth PFET 714, PFET4, minimally affects the charging period, ΔTCHARGING_PERIOD, of the variable delay circuitry 684, where the charging period, ΔTCHARGING_PERIOD, is a period of time during which the variable delay capacitor 722 is being charged until the third voltage node 724 is equal to or exceeds the logic high threshold voltage of the output buffer stage 726.
Similarly, when the second input buffer circuit 698 provides a digital logic low state, the second input buffer provides an output voltage at the second voltage node 704 substantially equal to ground. In this case, the gate of the fourth PFET 714, PFET4, is less than the logic low threshold level. As a result, fourth PFET 714, PFET4, turns on and charges the variable delay capacitor 722 until the voltage level at the third voltage node 724 is substantially equal to the circuit supply voltage, VDD. In addition, the third PFET 708, PFET3, of the correction start voltage circuit 712 is configured to turn on and couple the source of the fourth NFET 716, NFET4, to the circuit supply voltage, VDD, such that the charge stored on the source of the fourth NFET 716, NFET4, is at a voltage level substantially equal to ground. As a result, the charge stored on the source of the fourth NFET 716, NFET4, minimally affect the charging period, ΔTDISCHARGING_PERIOD, of the variable delay circuitry 684, where the charging period, ΔTDISCHARGING_PERIOD, is a period of time during which the variable delay capacitor 722 is being discharged until the third voltage node 724 is equal to or less than the logic low threshold voltage of the output buffer stage 726.
Otherwise, if the correction start voltage circuit 712 is not present, the source of the fourth PFET 714, PFET4, and the source of the fourth NFET 716, NFET4, will each tend to float to an undetermined voltage level when either the fourth PFET 714, PFET4, or the fourth NFET 716, NFET4, are in the non-conducting state. As a result, state transition voltage change is unpredictable.
The operation of the output buffer stage 726 depends upon the voltage level at the third voltage node 724. When the voltage level at the third voltage node 724 is equal to or less than the logic low threshold voltage such that the sixth PFET 728, PFET6 is turned on and in the saturation state, the output buffer output 732 is effectively coupled to the circuit supply voltage, VDD, through the sixth PFET 728, PFET6. Simultaneously, sixth NFET 730, NFET6, is configured to be turned off when the sixth PFET 728, PFET6 is turned on. As a result, the output buffer stage 726 provides an output voltage, VOUT, substantially equal to the circuit supply voltage, VDD, which represents a digital logic high state.
However, when the voltage level at the third voltage node 724 is equal to or greater than the logic high threshold voltage such that the sixth NFET 730, NFET6 is turned on and in the saturation state, the output buffer output 732 is effectively coupled to the ground through the sixth NFET 730, NFET6. Simultaneously, the sixth PFET 728, PFET6, is configured to be turned off when the sixth NFET 730, NFET6 is turned on. As a result, the output buffer stage 726 provides an output voltage, VOUT, substantially equal to ground, which represents a digital logic low state.
The variable delay time, TVARIABLE_DELAY_TIME, provided by the variable delay circuitry 684 is a function of a charging period, ΔTCHARGING_PERIOD and a discharging period, ΔTDISCHARGING_PERIOD, of the variable delay capacitor. The charging period, ΔTCHARGING_PERIOD, is a period of time during which the variable delay capacitor 722 is being charged until the third voltage node is equal to or exceeds the logic high threshold voltage. During the charging period, ΔTCHARGING_PERIOD, the change in the voltage across the variable delay capacitor 722, necessary to change the digital logic state at the input of the output buffer stage 726, is the charging voltage change, ΔDELAY_VAR_CAP_CHARGING. The discharging period, ΔTDISCHARGING_PERIOD, is a period of time during which the variable delay capacitor 722 is being charged until the third voltage node 724 is equal to or exceed the logic high threshold voltage. During the discharging period, ΔTDISCHARGING_PERIOD, the change in the voltage across the variable delay capacitor 722, necessary to change the digital logic state at the input of the output buffer stage 726, is the discharging voltage change, ΔDELAY_VAR_CAP_DISCHARGING.
The average variable delay time, TAVERAGE_VARIABLE DELAY, provided by the variable delay circuitry 684 is provided by equation (1):
The charging period, ΔTCHARGING_PERIOD, of the variable delay capacitor 722 is dependent upon the capacitance value of the variable delay capacitance, CDELAY_VAR, and the magnitude of the variable delay capacitor current, IC_VAR, where the magnitude of the variable delay capacitor current, IC_VAR, is substantially equal to the first bias current, IBIAS_1 during the charging period, ΔTCHARGING_PERIOD. Similarly, the discharging period, ΔTDISCHARGING_PERIOD, of the variable delay capacitor 722 is dependent upon the capacitance value of the variable delay capacitance, CDELAY_VAR, and the magnitude of the variable delay capacitor current, IC_VAR, where the magnitude of the variable delay capacitor current, IC_VAR, is substantially equal to the second bias current, I-BIAS_2 during the discharging period, ΔTDISCHARGING_PERIOD.
During the charging period, ΔTCHARGING_PERIOD, the variable delay capacitor current, IC_VAR, is given by equation (2):
Similarly, during the discharging period, ΔTDISCHARGING_PERIOD, the variable delay capacitor current, IC_VAR, is given by equation (3) as follows:
Assuming the variable delay capacitor current, IC_VAR, is substantially equal to the first bias current, IBIAS_1, provided by the fifth PFET 718, PFET5, during the charging period, ΔTCHARGING_PERIOD, the charging period, ΔTCHARGING_PERIOD, is given by equation (4) as follows:
Likewise, assuming the magnitude of the variable delay capacitor current, IC_VAR, is substantially equal to the second bias current, IBIAS_2, sunk by the fifth NFET 720, NFET5, during the discharging period, ΔTDISCHARGING_PERIOD, the discharging period, ΔTDISCHARGING_PERIOD, is given by equation (5):
In some embodiments of the programmable delay circuitry 432C the channel width of the fifth PFET 718, PFET5, and the channel width of the fifth NFET 720, NFET5, are configured such that the first bias current, IBIAS_1, is substantially equal to the second bias current, IBIAS_2, where the magnitude of the first bias current, IBIAS_1, and the magnitude of the second bias current, IBIAS_2, are substantially equal to a bias current, IBIAS.
Some embodiments of the output buffer stage 726 may be configured such that the charging voltage change, ΔDELAY_VAR_CAP_CHARGING, is substantially equal to the discharging voltage change, ΔDELAY_VAR_CAP_DISCHARGING. For example, in some embodiments, the output buffer stage 726 logic low threshold voltage and a logic high threshold are configured such that the voltage change, ΔDELAY_VAR_CAP_CHARGING, is substantially equal to the discharging voltage change, ΔDELAY_VAR_CAP_DISCHARGING. In the case where the magnitude of the charging voltage change, ΔDELAY_VAR_CAP_CHARGING, is substantially equal to the magnitude of the discharging voltage change, ΔDELAY_VAR_CAP_DISCHARGING, such that the magnitude of the charging voltage change, ΔDELAY_VAR_CAP_CHARGING, and the magnitude of the discharging voltage change, ΔDELAY_VAR_CAP_DISCHARGING, are substantially equal to a transition voltage change, ΔDELAY_VAR_CAP_TRANSITION, the variable delay time, TVARIABLE_DELAY_TIME, of the variable delay circuitry 684 is given by equation (6):
In other embodiments of the programmable delay circuitry 432C, the channel width of the fifth PFET 718, PFET5, and the channel width of the fifth NFET 720, NFET5, may be configured such that the first bias current, IBIAS_1, is not substantially equal to the second bias current, IBIAS_2. In this case, the charging period, ΔTCHARGING_PERIOD, and the discharging period, ΔTDISHARGING_PERIOD, may not be substantially equal. As an example, in some embodiments, the charging period, ΔTCHARGING_PERIOD, is longer than the discharging period, ΔTDISHARGING_PERIOD. In other embodiments, the charging period, ΔTCHARGING_PERIOD, is less than the discharging period, ΔTDISHARGING_PERIOD.
As an alternative embodiment, the logic low threshold voltage and the logic high threshold of the output buffer stage 726 may be configured such the charging voltage change, ΔDELAY_VAR_CAP_CHARGING, is substantially equal to the discharging voltage change, ΔDELAY_VAR_CAP_DISCHARGING.
In addition, as discussed above, in some embodiments of the programmable delay circuitry 432C, the controller 50 (
Furthermore, as discussed above, in some embodiments of the programmable delay circuitry 432C, the controller 50 (
Because the first input buffer circuit 690, the second input buffer circuit 698, the input stage 706 of the variable delay circuitry 684, the correction start voltage circuit 712, and the output buffer stage 726 are substantially symmetric in construction, the first input buffer circuit 690, the second input buffer circuit 698, the input stage 706 of the variable delay circuitry 684, the correction start voltage circuit 712, and the output buffer stage 726 may be configured such that the logic low threshold voltage and the logic high threshold voltage tend to proportionally track the circuit supply voltage, VDD. As a result, the magnitude of the charging voltage change, ΔDELAY_VAR_CAP_CHARGING, and the magnitude of the discharging voltage change, ΔDELAY_VAR_CAP_DISCHARGING, will also tend to proportionally track the circuit supply voltage. However, the variations in the variable delay time, TVARIABLE_DELAY_TIME, provided by the variable delay circuitry 684 due to changes in the voltage level of the circuit supply voltage, VDD, may be minimized by configuring the programmable delay circuitry 432C such that the magnitude of the first bias current, IBIAS_1, and the magnitude of the second bias current, IBIAS_2, change proportionally with respect to a change in the voltage level of the circuit supply voltage, VDD.
As an example, the voltage divider circuit 686 and bias current and mirror circuit 688 may be configured such that the first bias current, IBIAS_1, provided by the fifth PFET 718, PFET5, and the second bias current, IBIAS_2, sunk by the fifth NFET 720, NFET5, are related to the voltage level of the circuit supply voltage, VDD, such that the variations in the variable delay time, TVARIABLE_DELAY_TIME, provided by the variable delay circuitry 684 due to changes in the voltage level of the circuit supply voltage, VDD, may be minimized.
The bias current and mirror circuit 688 includes a seventh PFET 734, PFET7, a seventh NFET 736, NFET7, an eighth PFET 738, PFET8, an eighth NFET 740, PFET9, a bias reference current setting resistor 744, and a bias resistor 746. The bias reference current setting resistor 744 has a bias reference current setting resistance, R3. The bias resistor 746 has a bias resistance, R4.
The source of the seventh PFET 734, PFET7, is coupled to the circuit supply voltage, VDD. The gate of the seventh PFET 734, PFET7, is coupled to the source of the seventh PFET 734, NFET7, and the drain of the eighth NFET 740, NFET8. In addition, the gate and drain of the seventh PFET 734, PFET7, is coupled to the gate of the fifth PFET 718, PFET5.
The gate and drain of the seventh PFET 734, PFET7, is coupled to the drain of the eighth NFET 740, NFET8, The source of the eighth NFET 740, NFET8, is coupled to the drain of the seventh NFET 736, NFET7. The sources of the eighth NFET 740, NFET8, and the seventh NFET 736, NFET7, are coupled to ground. The gate of the seventh NFET 736, NFET7, is coupled to the drain and gate of the ninth NFET 742, NFET9. In addition, the gate of the seventh NFET 736, NFET7, and the gate and drain of the ninth NFET 742, NFET9, are coupled to the gate of the fifth NFET 720, NFET5, of the variable delay circuitry 684.
The bias reference current setting resistor 744 is coupled between the circuit supply voltage, VDD, and the source of the eighth PFET 738, PFET8. The bias resistor 746 is coupled between the drain of the eighth PFET 738, PFET8, and the drain and gate of the ninth NFET 742, NFET9, and the gate of the seventh NFET 736, NFET7.
The voltage divider circuit 686 includes a first voltage divider resistor 748, a tenth PFET 750, PFET10, an eleventh PFET 752, PFET11, and a second voltage divider resistor 754. The first voltage divider resistor 748 has a first voltage divider resistance, R1. The second voltage divider resistor 754 has a second voltage divider resistance, R2. The first voltage divider resistance, R1, of the first voltage divider resistor 748 is substantially equal to the second voltage divider resistance, R2, of the second voltage divider resistor 754.
The first voltage divider resistor 748 is coupled between the circuit supply voltage, VDD, and the source of the tenth PFET 750, PFET10. The gate of the tenth PFET 750, PFET10, is coupled to the drain of the tenth PFET 750, PFET10 and the source of the eleventh PFET 752, PFET11. The gate of the eleventh PFET 752, PFET11, is coupled to the drain of the eleventh PFET 752, PFET11. The second voltage divider resistor 754 is coupled between the drain of the eleventh PFET 752, PFET11, and ground. Because the gate of the tenth PFET 750, PFET10, is coupled to the drain of the tenth PFET 750, and the gate of the eleventh PFET 752, PFET11, is coupled to the drain of the eleventh PFET 752, PFET11, both the tenth PFET 750, PFET10, and the eleventh PFET 752, PFET11, are biased to be on in a saturation mode of operation. The source-to-drain voltage across the tenth PFET 750, PFET10, and the source-to-drain voltage across the eleventh PFET 752, PFET11, are substantially equal. Because the first voltage divider resistance, R1, of the first voltage divider resistor 748 is substantially equal to the second voltage divider resistance, R2, of the second voltage divider resistor 754, the voltage divider circuit 686 may be configured to set a bias voltage substantially equal to one-half of the circuit supply voltage, VDD, on the drain of the tenth PFET 750, PFET10, and the source of the eleventh PFET 752, PFET11.
The operation of the bias current and mirror circuit 688 is now explained with reference to the voltage divider circuit 686. The bias current and mirror circuit 688 is coupled to the voltage divider circuit 686 by coupling the gate of the eighth PFET 738, PFET8, to the gate and drain of the eleventh PFET 752, PFET11. The eighth PFET 738, PFET8, of the bias current and mirror circuit 688 and the eleventh PFET 752, PFET11, of the voltage divider circuit 686 are configured such that the gate-to-source voltage of the eighth PFET 738, PFET8, is substantially equal to the gate-to-source voltage of the eleventh PFET 752, PFET11. As a result, the voltage on the source of the eighth PFET 738, PFET8, is substantially equal to the voltage on the source of the eleventh PFET 752, PFET11. As discussed above with respect to the operation of the voltage divider circuit 686, the voltage on the source of the eleventh PFET 752, PFET11, is substantially equal to VDD/2. Accordingly, the voltage on the source of the eighth PFET 738, PFET8, is also substantially equal to VDD/2. The current through the bias reference current setting resistor 744, which is the reference bias current, IBIAS_REF, is provided by equation (7) as follows:
Accordingly, the drain-to-source current of the ninth NFET 742, NFET9, is substantially equal to IBIAS_REF. Because the gate and drain of the ninth NFET 742, NFET9, are coupled to the gate of the seventh NFET 736, NFET7, and the gate of the fifth NFET 720, NFET5, the source-to-drain current flowing through the ninth NFET 742, NFET9, is mirrored such that the drain-to-source current flowing through the seventh NFET 736, NFET7, and the drain-to-source current flowing through the fifth NFET 720, NFET5, are proportional to the drain-to-source current flowing through the ninth NFET 742, NFET9. Furthermore, the source-to-drain current flowing through the seventh PFET 734, PFET7, is substantially equal to the drain-to-source current flowing through the seventh NFET 736, NFET7. Because the gate-to-source voltage of the fifth PFET 718, PFET5, is substantially equal to the gate voltage of the seventh PFET 734, PFET7, the source-to-drain current of the seventh PFET 734, PFET7, is proportional to the bias reference current, IBIAS_REF, where the bias reference current setting resistance, R3, of the bias reference current setting resistor 744 sets the bias reference current, IBIAS_REF. As a result, the first bias current, IBIAS_1, proportionally tracks the circuit supply voltage, VDD. Similarly, the second bias current, IBIAS_2, proportionally tracks the circuit supply voltage, VDD.
Accordingly, the bias reference current setting resistance, R3, resistance value may be configured to minimize the sensitivity of the variable delay time, TVARIABLE_DELAY_TIME, provided by the variable delay circuitry 684 to a change in the voltage level of the circuit supply voltage, VDD. In addition, in some embodiments, the channel width ratios of the channel width of the ninth NFET 742, NFET9, to each of the channel widths of the seventh PFET 734, PFET7, the seventh NFET 736, NFET7, the fifth PFET 718, PFET5 and the fifth NFET 720, NFET5, may be configured to minimize the sensitivity of the variable delay time, TVARIABLE_DELAY_TIME, provided by the variable delay circuitry 684 due to changes in the voltage level of the circuit supply voltage, VDD.
The variable capacitance control bus 760, CNTR_CD (5:1), may include a first capacitor control signal 762, CNTR_CD1, a second capacitor control signal 764, CNTR_CD2, a third capacitor control signal 766, CNTR_CD3, a fourth capacitor control signal 768, CNTR_CD4, and a fifth capacitor control signal 770, CNTR_CD5.
The programmable capacitor array 758 may include a first array capacitor 772, a second array capacitor 774, a third array capacitor 776, a fourth array capacitor 778, and a fifth array capacitor 780. The first array capacitor 772 may have a capacitance substantially equal to a first array capacitor capacitance, CD1. The second array capacitor 774 may have a capacitance substantially equal to a second array capacitor capacitance, CD2. The third array capacitor 776 may have a capacitance substantially equal to a third array capacitor capacitance, CD3. The fourth array capacitor 778 may have a capacitance substantially equal to a fourth array capacitor capacitance, CD4. The fifth array capacitor 780 may have a capacitance substantially equal to a fifth array capacitor capacitance, CD5.
In addition, the programmable capacitor array 758 may further include a first switch element 782, NFET11, a second switch element 784, NFET12, a third switch element 786, NFET13, a fourth switch element 788, NFET14, and a fifth switch element 790, NFET15. In
The programmable capacitor array 758 includes a first programmable capacitance 792, a second programmable capacitance 794, a third programmable capacitance 796, a fourth programmable capacitance 798, and a fifth programmable capacitance 800. The first programmable capacitance 792 may be formed by coupling the first array capacitor 772 between the third voltage node 724 and the drain of the first switch element 782, NFET11, where the source of the first switch element 782, NFET11, is coupled to ground and the gate of first switch element 782, NFET11, is coupled to the first capacitor control signal 762, CNTR_CD1, of the variable capacitance control bus 760, CNTR_CD (5:1). The second programmable capacitance 794 may be formed by coupling the second array capacitor 774 between the third voltage node 724 and the drain of the second switch element 784, NFET12, where the source of the second switch element 784, NFET12, is coupled to ground and the gate of second switch element 784, NFET12, is coupled to the second capacitor control signal 764, CNTR_CD2, of the variable capacitance control bus 760, CNTR_CD (5:1). The third programmable capacitance 796 may be formed by coupling the third array capacitor 776 between the third voltage node 724 and the drain of the third switch element 786, NFET13, where the source of the third switch element 786, NFET13, is coupled to ground and the gate of third switch element 786, NFET13, is coupled to the third capacitor control signal 766, CNTR_CD3, of the variable capacitance control bus 760, CNTR_CD (5:1). The fourth programmable capacitance 798 may be formed by coupling the fourth array capacitor 778 between the third voltage node 724 and the drain of the fourth switch element 788, NFET14, where the source of the fourth switch element 788, NFET14, is coupled to ground and the gate of fourth switch element 788, NFET14, is coupled to the fourth capacitor control signal 768, CNTR_CD4, of the variable capacitance control bus 760, CNTR_CD (5:1). The fifth programmable capacitance 800 may be formed by coupling the fifth array capacitor 780 between the third voltage node 724 and the drain of the fifth switch element 790, NFET15, where the source of the fifth switch element 790, NFET15, is coupled to ground and the gate of the fifth switch element 790, NFET15, is coupled to the fifth capacitor control signal 770, CNTR_CD5, of the variable capacitance control bus 760, CNTR_CD (5:1).
As an example, in some embodiments, the variable delay capacitor 722A is configured such that the programmable capacitor array 758 is a linearly programmable capacitor array. The variable delay capacitor 722A may be configured to be a linearly programmable capacitor array by configuring the first array capacitor capacitance, CD1, the second array capacitor capacitance, CD2, the third array capacitor capacitance, CD3, the fourth array capacitor capacitance, CD4, and the fifth array capacitor capacitance, CD5, to have the same capacitance value.
As an alternative example, in some embodiments of the variable delay capacitor 722A, the programmable capacitor array 758 may be configured as a binary weighted programmable capacitor array. The binary weighted programmable capacitor array may be configured such that the second array capacitor capacitance, CD2, has substantially twice the capacitance as the first array capacitor capacitance, CD1, the third array capacitor capacitance, CD3, has substantially twice the capacitance as the second array capacitor capacitance, CD2, the fourth array capacitor capacitance, CD4, has substantially twice the capacitance as the third array capacitor capacitance, CD3, and the fifth array capacitor capacitance, CD5, has substantially twice the capacitance as the fourth array capacitor capacitance, CD4.
The controller 50 may be configured to selectively control the variable capacitance bus, CNTR_CD (5:1), to set the capacitance value of the variable delay capacitance, CDELAY_VAR, of the variable delay capacitor 722A. The first capacitor control signal 762, CNTR_CD1, the second capacitor control signal 764, CNTR_CD2, the third capacitor control signal 766, CNTR_CD3, the fourth capacitor control signal 768, CNTR_CD4, and the fifth capacitor control signal 770, CNTR_CD5, may form a binary capacitor control word, CNTR_CD, where 0≧CNTR_CD≧31.
Accordingly, the programmable capacitor array 758 may be configured such that as the value of the binary capacitor control word, CNTR_CD increases from 0 to 31, the effective capacitance of the programmable capacitor array 758 changes linearly.
Accordingly, returning to
Illustratively, by way of example, and not by limitation, in some embodiments of the programmable capacitor array 758 used to provide the variable delay capacitance, CDELAY_VAR, of the variable delay circuitry 684, the first array capacitor capacitance, CD1, of the first array capacitor 772 may have a capacitance of around 18.25 pF. The second array capacitor capacitance, CD2, of the second array capacitor 774 may have a capacitance of around 30.93 pF. The third array capacitor capacitance, CD3, of the third array capacitor 776 may have a capacitance of around 61.86 pF. The fourth array capacitor capacitance, CD4, of the fourth array capacitor 778 may have a capacitance of around 123.72 pF. The fifth array capacitor capacitance, CD5, of the fifth array capacitor 780 may have a capacitance of around 247.45 pF.
The variable delay capacitance, CDELAY_VAR, of the variable delay capacitor 722, depicted in
A switch mode power supply converter, a parallel amplifier, and a parallel amplifier output impedance compensation circuit are disclosed. The switch mode power supply converter provides a switching voltage and generates an estimated switching voltage output, which is indicative of the switching voltage. The parallel amplifier generates a power amplifier supply voltage at a power amplifier supply output based on a compensated VRAMP signal. The parallel amplifier output impedance compensation circuit provides the compensated VRAMP signal based on a combination of a VRAMP signal and a high frequency ripple compensation signal. The high frequency ripple compensation signal is based on a difference between the VRAMP signal and the estimated switching voltage output.
In one embodiment of the parallel amplifier output impedance compensation circuit, the parallel amplifier output impedance compensation circuit compensates for a non-ideal output impedance of the parallel amplifier by providing the compensated VRAMP signal based on the combination of the VRAMP signal and a high frequency ripple compensation signal. In one embodiment of the parallel amplifier output impedance compensation circuit, the combination of the VRAMP signal and the high frequency ripple compensation signal is based on pre-filtering the VRAMP signal to equalize the overall frequency response of the switch mode power supply converter and the parallel amplifier to provide a proper transfer function of the switch mode power supply converter and the parallel amplifier.
The switch mode power supply converter 802 depicted in
In addition, some embodiments of the switch mode power supply converter 802 may include an FLL circuit (not depicted) similar to the FLL circuit 54 (
Similar to the generation of the estimated switching voltage output 38B, VSW_EST, by the switcher control circuit 52 of the multi-level charge pump buck converter 12B, depicted in
The programmable delay circuitry 806 of the switch mode power supply converter 802 may be configured by the controller 50 to provide the alignment period, TALIGNMENT, in order to generate the delayed estimated switching voltage output 38D, VSW_EST_DELAY. As a non-limiting example, the programmable delay circuitry 806 may be similar in form and function to the programmable delay circuitry 432A, depicted in
The controller 50 may configure the switch mode power supply converter 802 to scale the magnitude of the delayed estimated switching voltage output 38D, VSW_EST_DELAY, such that the magnitude of the delayed estimated switching voltage output 38D, VSW_EST_DELAY, tracks variations in the supply input 24, (VBAT).
The pseudo-envelope follower power management system 10PA further includes a VRAMP digital-to-analog (D/A) circuit 808 and a parallel amplifier circuit 14PA that is similar in form and function to the parallel amplifier circuit 14B, depicted in
The pseudo-envelope follower power management system 10PA includes a parallel amplifier output impedance compensation circuit 37B configured to generate a compensated VRAMP signal, VRAMP_C, for use by the parallel amplifier 35 in lieu of the VRAMP signal in order to reduce the high frequency ripple voltages generated in the parallel amplifier output voltage, V-PARA_AMP, by the parallel amplifier 35 at the parallel amplifier output 32A due to the non-ideal output impedance characteristics of the parallel amplifier 35. For example, one of the non-ideal output impedance characteristics of the parallel amplifier 35 is that the parallel amplifier 35 has an output impedance response that is inductive and increases approximately +6 dB/octave near and around the switching frequency of the switch mode power supply converter 802. Thus, for example, the output impedance of the parallel amplifier 35 may be characterized as having a parallel amplifier inductance, LCORR.
Returning to
For example, the power amplifier associated inductance, LPA, (not shown) includes any parasitic inductance or filter inductance added between the power amplifier supply voltage, VCC, controlled by the parallel amplifier circuit 14PA, and the power amplifier collector 22A of a linear RF power amplifier 22. The power amplifier associated capacitance, CPA, (not shown) includes any parasitic capacitance of a load line between the power amplifier supply voltage, VCC, controlled by the parallel amplifier circuit 14PA and any added decoupling capacitance related to a power amplifier decoupling capacitor (not shown) coupled to the power amplifier collector 22A. The power amplifier associated inductance, LPA, and the power amplifier associated capacitance, CPA, (not shown) may be determined at the time of calibration of an electronic device that includes the pseudo-envelope follower power management system 10PA. The power amplifier associated inductance, LPA, (not shown) in combination with the power amplifier associated capacitance, CPA, (not shown) may form a power amplifier low pass filter (not shown) such that the frequency response of the combination of the power amplifier low pass filter and the pseudo-envelope follower power management system 10PA is not substantially flat through the operating frequency range of the linear RF power amplifier 22. Accordingly, the frequency response of the digital VRAMP pre-distortion filter circuit 812 may be configured to compensate the frequency response of the pseudo-envelope follower power management system 10PA such that the overall frequency response, as measured between the digital VRAMP signal 810, VRAMP_DIGITAL, and the power amplifier collector 22A, is substantially flat through the operating frequency range of the linear RF power amplifier 22.
As depicted in
Accordingly, unlike the parallel amplifier circuit 14B, depicted in
The digital VRAMP pre-distortion filter circuit 812 may include a pre-filter circuit 812A, a second digital-to-analog converter (D/A) circuit 812B, and an anti-aliasing filter 812C. The pre-filter circuit 812A may be configured to be either an infinite impulse response (IIR) filter or a finite impulse response (FIR) filter configured to receive the digital VRAMP signal 810, VRAMP_DIGITAL. The pre-filter circuit 812A may be configured by the controller 50 to control the frequency response of the pre-filter circuit 812A. The pre-filter circuit 812A may include one or more coefficients that may be configured by the controller 50 to shape the frequency response of the pre-filter circuit 812A.
As an example, in the case where the pre-filter circuit 812A is configured to be an infinite impulse response (IIR) filter, the pre-filter circuit 812A may include feed forward filter coefficients and feedback filter coefficients. Likewise, the pre-filter circuit 812A may be configured to be a multiple order filter. For example, in some embodiments of the digital VRAMP pre-distortion filter circuit 812, the pre-filter circuit 812A may be configured to be a first order filter. In alternative embodiments of the digital VRAMP pre-distortion filter circuit 812, the pre-filter circuit 812A may be a filter having two or more orders. As a result, the digital VRAMP pre-distortion filter circuit 812 may permit the controller to have additional degrees of control of the pre-distortion of the digital VRAMP signal 810, VRAMP_DIGITAL, which is used to provide a pre-distorted VRAMP signal. As an example, the controller 50 may configure the feed forward coefficients and the feedback coefficients of the digital VRAMP pre-distortion filter circuit 812 to provide frequency peaking to compensate for the low pass filter effect of the combination of the power amplifier associated inductance, LPA, (not shown), and the power amplifier filter associated capacitance, CPA, (not shown), as described above.
As an alternative case, in some embodiments the pre-filter circuit 812A may be a finite impulse response (FIR) filter having multiple weighting coefficients. The controller 50 may configure each of the weighting coefficients to configure the frequency response of the digital VRAMP pre-distortion filter circuit 812 to pre-distort the digital VRAMP signal, VRAMP_DIGITAL, to also equalize the overall frequency response of the pseudo-envelope follower power management system 10PA. In addition, the digital VRAMP pre-distortion filter circuit 812 may be further configured to compensate for the power amplifier associated inductance, LPA, (not shown), and the power amplifier filter associated capacitance, CPA, (not shown), such that the overall frequency response, as measured between the digital VRAMP signal 810, VRAMP_DIGITAL, and the power amplifier collector 22A, is substantially flat through the operating frequency range of the linear RF power amplifier 22.
The output of the pre-filter circuit 812A is digital to analog converted by the second digital-to-analog converter (D/A) circuit 812B, where the output of the second digital-to-analog converter (D/A) circuit 812B is anti-alias filtered by the anti-aliasing filter 812C to provide the pre-filtered VRAMP signal 814, VRAMP_PRE-FILTERED. The frequency response of the pre-filter circuit 812A may be configured to equalize the overall transfer function response between the digital VRAMP signal 810, VRAMP_DIGITAL, and the power amplifier collector 22A. As an example, the amount or shape of the equalization provided by the frequency response of the pre-filter circuit 812A, and thus the digital VRAMP pre-distortion filter circuit 812, may depend upon the bypass capacitance, CBYPASS, of the bypass capacitor 19, the power amplifier associated inductance, LPA, (not shown), the power amplifier associated capacitance, CPA, (not shown), the frequency response of the parallel amplifier 35, and/or a combination thereof.
In addition, the controller 50 may adjust the frequency response of the pre-filter circuit 812A by modifying the one or more coefficients of the pre-filter circuit 812A to equalize the relative transfer function response between the power amplifier supply voltage VCC, and the digital VRAMP signal 810, VRAMP_DIGITAL. The controller 50 adjusts the frequency response of the pre-filter circuit 812A such that the frequency response of the overall transfer function response between the digital VRAMP signal 810, VRAMP_DIGITAL, and the power amplifier collector 22A is substantially flattened through a desired frequency range. Illustratively, in some embodiments, the controller 50 may configure the equalization or frequency response of the pre-filter circuit 812A such that the frequency response of the overall transfer function response the digital VRAMP signal 810, VRAMP_DIGITAL, and the power amplifier collector 22A is substantially flattened out to around 20 MHz.
As an example, where the pre-filter circuit 812A is configured as an IIR filter, the pre-filter circuit 812A is configured to operate at a clock rate of about 312 MHz. Illustratively, for the case where the bypass capacitance, CBYPASS, of the bypass capacitor 19 is approximately 2 nF, the controller 50 may configure the frequency response of the pre-filter circuit 812A to have a pole at approximately 14.5 MHz and a zero at approximately 20 MHz.
In addition, in some embodiments of the digital VRAMP pre-distortion filter circuit 812, the controller 50 may configure the equalization or frequency response provided by the pre-filter circuit 812A as a function of the operational bandwidth of the linear RF power amplifier 22 need to provide the wide-band modulation corresponding to a specific LTE band number. As an example, in a case where the LTE band has a 15 MHz bandwidth, the controller 50 may configure the digital VRAMP pre-distortion filter circuit 812 to provide additional VRAMP pre-distortion such that the radio frequency signal generated by the linear RF power amplifier falls within the spectrum mask requirements for an LTE 15 MHz test case.
Returning to
The parallel amplifier output impedance compensation circuit 37B further includes a first subtracting circuit 822, a ZOUT compensation high pass filter 824, a GCORR scalar circuit 826, a second subtracting circuit 828, a tune circuit 830, and a summing circuit 832. The first subtracting circuit 822 includes a positive terminal configured to receive the VRAMP signal provided to the first control input 34 of the parallel amplifier circuit 14PA and a negative terminal configured to receive the estimated switching voltage input signal 820, VSW_I. The first subtracting circuit 822 subtracts the estimated switching voltage input signal 820, VSW_I, from the VRAMP signal to generate an expected difference signal 834, which is provided to the ZOUT compensation high pass filter 824. The expected difference signal 834 represents the difference between the target voltage level of the power amplifier supply voltage VCC, to be generated at the power amplifier supply output 28 in response to the VRAMP signal and the switching voltage, VSW, to be provided at the switching voltage output 26 of the switch mode power supply converter 802 at the time when the parallel amplifier 35 generates the parallel amplifier output voltage, VPARA_AMP, at the parallel amplifier output 32A.
A frequency response of the ZOUT compensation high pass filter 824 may be configurable. As an example, the ZOUT compensation high pass filter 824 may include programmable time constants. The ZOUT compensation high pass filter 824 may include resistor arrays or capacitance arrays that may be configurable by the controller 50 to set the value of programmable time constants. For example, the resistor arrays may be binary weighted resistor arrays similar to the binary weighted resistor arrays previously described. The capacitor arrays may be binary weighted capacitor arrays similar to the binary weighted capacitor arrays previously described. The controller 50 may configure the programmable time constants of the ZOUT compensation high pass filter 824 to obtain a desired high pass filter response. In addition, the controller 50 may configure the programmable time constants of the ZOUT compensation high pass filter 824 to obtain a desired high pass filter response as a function of the operational bandwidth or the wide-bandwidth modulation associated with the LTE band number for which the linear RF power amplifier 22 is configured to operate.
Illustratively, in some embodiments, the ZOUT compensation high pass filter 824 may have a programmable time constant set to 40 nanoseconds. For example, the programmable time constant may be obtained by the controller 50 configuring the resistance of a programmable resistor to be substantially equal to 4K ohms and the capacitance of a programmable capacitor to be substantially equal to 10 pF. In this scenario, the high pass cutoff frequency, fHPC, of the example ZOUT compensation high pass filter 824 may be approximately equal to 4 MHz. In some embodiments, the ZOUT compensation high pass filter 824 may be a multiple-order high pass filter having multiple programmable time constants. In the case where the ZOUT compensation high pass filter 824 is a multiple-order high pass filter, the controller 50 may be configured to set multiple programmable time constants to obtain a desired high pass frequency response from the ZOUT compensation high pass filter 824. As an example, the ZOUT compensation high pass filter 824 may be a second order high pass filter having a first time constant and a second time constant corresponding to a first high pass cutoff frequency, fHPC1, and a second high pass cutoff frequency, fHPC2. In this case, the controller 50 may configure the first time constant and the second time constant of the ZOUT compensation high pass filter 824 to obtain a desired high pass frequency response. In other embodiments, the ZOUT compensation high pass filter 824 may be configured as an active filter.
When the controller 50 configures the estimated switching voltage output selection switch 816, S1, to provide the delayed estimated switching voltage output 38D, VSW_EST_DELAY, as the estimated switching voltage input signal 820, VSW_I, the controller 50 may configure the programmable delay circuitry 806 to provide a delay substantially equal to an alignment period, TALIGNMENT, in order to time align the indication of the switching voltage, VSW, represented by the estimated switching voltage input signal 820, VSW_I, with the VRAMP signal. The expected difference signal 834 is provided to the ZOUT compensation high pass filter 824. The ZOUT compensation high pass filter 824 high pass filters the expected difference signal 834 to generate an estimated high frequency ripple signal 836. The high pass filtering of the ZOUT compensation high pass filter 824 substantially extracts only the high frequency content of the expected difference signal 834, where the high frequency content of the expected difference signal 834 represents a scaled derivative of the ripple current in the inductor current, ISW_OUT, of the power inductor 16 generated by the switch mode power supply converter 802 due to the changes in the switching voltage, VSW, associated with the estimated switching voltage input signal 820, VSW_I. Thus, the estimated high frequency ripple signal 836 represents an estimated high frequency ripple current at the power amplifier supply output 28 that may cause the parallel amplifier 35 to generate high frequency ripple voltages in the parallel amplifier output voltage, VPARA_AMP, at the parallel amplifier output 32A. The delay period provided by the programmable delay circuitry 806 may be configured by the controller 50 to temporally align the delayed estimated switching voltage output 38D, VSW_EST_DELAY, with the VRAMP signal to improve the accuracy of the estimated high frequency ripple signal 836.
In contrast, the controller 50 may configure the estimated switching voltage output selection switch 816, S1, to provide the estimated switching voltage output 38B, VSW_EST, as the estimated switching voltage input signal 820, VSW_I, to the ZOUT compensation high pass filter 824. In this case, the ZOUT compensation high pass filter 824 high pass filters the expected difference signal 834 to generate the estimated high frequency ripple signal 836. The estimated high frequency ripple signal 836 substantially corresponds to a scaled derivative of a switcher ripple current in the inductor current, ISW_OUT, of the power inductor 16 based on the estimated switching voltage output 38B, VSW_EST. However, because the generation of the estimated switching voltage output 38B, VSW_EST, cannot be temporally aligned by adjusting a delay period provided by the programmable delay circuitry 806, the controller 50 may not configure the programmable delay circuitry 806 to minimize the peak-to-peak ripple voltages on the power amplifier supply voltage, VCC, by improving the temporal alignment of the estimated switching voltage output 38B, VSW_EST, with respect to the VRAMP signal.
As previously discussed, the ZOUT compensation high pass filter 824 high pass filters the expected difference signal 834 generated based on the estimated switching voltage output 38B, VSW_EST, to generate the estimated high frequency ripple signal 836. The pass band of the ZOUT compensation high pass filter 824 extract only the high frequency content of the estimated switching voltage input signal 820, VSW_I, where the expected difference signal 834 represents the expected difference between the switching voltage, VSW, and the target voltage level of the power amplifier supply voltage, VCC, based on the VRAMP signal.
Because the ZOUT compensation high pass filter 824 high pass filters the expected difference signal 834, the direct current content of the expected difference signal 834 is not present in the estimated high frequency ripple signal 836. The GCORR scalar circuit 826 scales the estimated high frequency ripple signal 836 based on a scaling factor, GCORR, to generate a high frequency ripple compensation signal 838.
The high frequency ripple compensation signal 838 is added to the pre-filtered VRAMP signal 814, VRAMP_PRE-FILTERED, by the summing circuit 832 to generate the compensated VRAMP signal, VRAMP_C. The high frequency ripple compensation signal 838 is added to the pre-filtered VRAMP signal 814, VRAMP_PRE-FILTERED, to compensate for the non-ideal output impedance of the parallel amplifier 35. The compensated VRAMP signal, VRAMP_C, is provided as an input to the parallel amplifier 35. The parallel amplifier generates the parallel amplifier output voltage, VPARA_AMP, based on the difference between the compensated VRAMP signal, VRAMP_C, and the power amplifier supply voltage, VCC.
Generation of the scaling factor, GCORR, will now be discussed. The second subtracting circuit 828 is configured to subtract the power amplifier supply voltage, VCC, from the VRAMP signal to provide a GCORR feedback signal 840 that is received by the tune circuit 830. In some embodiments of the parallel amplifier output impedance compensation circuit 37B, the tune circuit 830 may be configured to dynamically provide the scaling factor, GCORR, to the GCORR scalar circuit 826 based on the GCORR feedback signal 840. As an example, the controller 50 may configure the tune circuit 830 to provide a different value of the scaling factor, GCORR, on a block-by-block transmission basis dependent upon the operational mode of the linear RF power amplifier 22. For example, the tune circuit 830 may be configured by the controller 50 during a calibration procedure to develop at least one GCORR curve. In other embodiments, the tune circuit 830 may have multiple GCORR curves that may be used to provide a scaling factor, GCORR, based on the GCORR feedback signal 840 and the operational mode of the linear RF power amplifier 22. As an example, the controller 50 may configure the tune circuit 830 to use a particular one of the GCORR curves depending on the configuration and/or operational mode of the pseudo-envelope follower power management system 10PA, the parallel amplifier 35, or a combination thereof. Each GCORR curve may include several coefficients or values for the scaling factor, GCORR, that correspond to the magnitude of the GCORR feedback signal 840. In some embodiments, the controller 50 may select a GCORR curve to be used on a block-by-block transmission basis depending on the operational mode of the linear RF power amplifier 22.
For example, the controller 50 may select a first GCORR curve to be used by the tune circuit 830 when the linear RF power amplifier 22 is in a first operational mode. The controller 50 may select a second GCORR curve to be used by the tune circuit 830 when the linear RF power amplifier 22 is in a second operational mode. In still other embodiments of the parallel amplifier output impedance compensation circuit 37B, the tune circuit 830 may only have one GCORR curve to be used by the tune circuit 830 to provide the scaling factor, GCORR, to the GCORR scalar circuit 826 based on the GCORR feedback signal 840.
As an example, in some embodiments of the parallel amplifier output impedance compensation circuit 37B, the scaling factor, GCORR, is tuned by the tune circuit 830 based on a built-in calibration sequence that occurs at power start-up. As an example, the controller 50 may configure the switch mode power supply converter 802 to operate with a switching frequency that is a fixed frequency to create a switcher ripple current in the inductor current, ISW_OUT, of the power inductor 16 at a frequency of concern for the pseudo-envelope follower power management system 10PA. In those cases where the switch mode power supply converter 802 is configured as a multi-level charge pump buck converter, the controller 50 may configure the switch mode power supply converter 802 to operate in a “bang-bang mode” of operation. When operating in the “bang-bang mode” of operation, the controller 50 configures the switcher control circuit 804 such that the switch mode power supply converter 802 operates in a fashion similar to a buck converter. Thus, when operating in the “bang-bang mode” of operation, the switch mode power supply converter 802 switcher control circuit 804 does not permit the switch mode power supply converter 802 to provide a boosted output voltage at the switching voltage output 26.
As a non-limiting example, to tune the scaling factor, GCORR, the controller 50 may configure the switch mode power supply converter 802 to operate at a calibration frequency with a fixed duty cycle in order to create a switcher ripple current at the calibration frequency. For example, the controller 50 may set the calibration frequency to 10 MHz. The VRAMP signal is set to a constant value in order to create a constant output value for the power amplifier supply voltage, VCC, at the power amplifier supply output 28. As discussed previously, the controller 50 may configure the switch mode power supply converter 802 to operate in a “bang-bang mode” of operation. The direct current voltage present at the power amplifier supply voltage, VCC, will be primarily set by the duty cycle of the switch mode power supply converter 802. The DC voltage may be mainly set by the duty cycle on the switching voltage output 26 of the switch mode power supply converter 802. The tune circuit 830 determines the peak-to-peak ripple voltage on the power amplifier supply voltage, VCC, based on the GCORR feedback signal 840. Based on the magnitude of the peak-to-peak ripple voltage on the power amplifier supply voltage, VCC, the tune circuit 830 adjusts the value of the scaling factor, GCORR, until the peak-to-peak ripple voltage on the GCORR feedback signal 840 is minimized. In some embodiments, to adjust the value of the scaling factor, GCORR, based on the GCORR feedback signal 840, the controller 50 may determine the degree of adjustment to provide based on the estimated power inductor inductance parameter, LEST, the estimated bypass capacitor capacitance parameter, CBYPASS_EST, and the estimated power amplifier transconductance parameter, KI_OUT_EST, as previously described. Based on the scaling factor, GCORR, that provides the minimum the peak-peak ripple voltage on the power amplifier supply voltage, VCC, the tune circuit 830 selects the scaling factor, GCORR, to be provided to the GCORR scalar circuit 826. In some embodiments, the controller 50 may configure the switch mode power supply converter 802 to operate at various calibration frequencies to develop one or more GCORR curves, where each GCORR curve corresponds to an operational mode of the linear RF power amplifier 22.
The determination of the scaling factor, GCORR, and/or the development of the GCORR curves is substantially orthogonal to the temporal alignment of the delayed estimated switching voltage output 38D, VSW_EST_DELAY. Thus, following calibration of the tune circuit 830 to provide the scaling factor, GCORR, appropriate for the operational mode of the linear RF power amplifier 22, the controller 50 may be further configure to adjust the alignment period, TALIGNMENT, associated with the programmable delay circuitry 806 to temporally align the delayed estimated switching voltage output 38D, VSW_EST_DELAY, in order to further minimize the peak-to-peak ripple voltage on the power amplifier supply voltage, VCC. Thus, after the controller 50 completes the calibration of the tune circuit 830 to minimize the peak-to-peak ripple voltage on the power amplifier supply voltage, VCC, the controller 50 may configure the programmable delay circuitry 806 to iteratively adjust the alignment period, TALIGNMENT, provided by the programmable delay circuitry 806 to further minimize the peak-to-peak ripple voltage on the power amplifier supply voltage, VCC. In some embodiments, the controller 50 may determine the alignment period, to be provided by the programmable delay circuitry 806, for different operational modes of the linear RF power amplifier 22.
The GCORR function circuit 842 is configured to receive the scaled parallel amplifier output current estimate, IPARA_AMP_SENSE, generated by the parallel amplifier sense circuit 36 of the parallel amplifier circuitry 32. The value of the scaling factor, GCORR, may be based on a GCORR scaling function, GCORR(IPARA_AMP_SENSE), where the GCORR scaling function, GCORR(IPARA_AMP_SENSE), characterizes values of the scaling factor, GCORR, as a function of the scaled parallel amplifier output current estimate, IPARA_AMP_SENSE. In some embodiments, the GCORR scaling function, GCORR(IPARA_AMP_SENSE), may be a polynomial function. In other embodiments, the GCORR scaling function, GCORR(IPARA_AMP_SENSE), may be a linear function. For example, the GCORR scaling function, GCORR(IPARA_AMP_SENSE), may have GCORR scaling function coefficients that may be configurable by the controller 50 via the control bus 44. As a non-limiting example, equation (8) provides an example of the GCORR scaling function, GCORR(IPARA_AMP_SENSE), having two GCORR scaling function coefficients. For example, the GCORR scaling function coefficients may include a first GCORR scaling function coefficient, GCORR(0), and a second GCORR scaling function coefficient, GCORR(1), where the GCORR scaling function, GCORR(IPARA_AMP_SENSE), is a linear function characterized by equation (8) as follows:
GCORR(IPARA_AMP_SENSE)=GCORR(0)+GCORR(1)×IPARA_AMP_SENSE (8)
The first GCORR scaling function coefficient, GCORR(0), may represent a scaling factor that is independent of the scaled parallel amplifier output current estimate, IPARA_AMP_SENSE, and the second GCORR scaling function coefficient, GCORR(1), represents a first order coefficient of the GCORR scaling function, GCORR(IPARA_AMP_SENSE), that captures the dependency of the scaling factor, GCORR, on the change of value of the parallel amplifier inductance, LCORR, as a function of the parallel amplifier output current, IPARA_AMP. For example, in some embodiments, the second GCORR scaling function coefficient, GCORR(1) may be based on the parallel amplifier inductance estimate parameter, LCORR_EST, where the parallel amplifier inductance estimate parameter, LCORR_EST, is an estimated inductance of the parallel amplifier 35 between the frequencies 10 MHz and 30 MHz.
In addition, because the parallel amplifier output current, IPARA_AMP, may change depending upon the operational mode of the linear RF power amplifier 22, the values of the first GCORR scaling function coefficient, GCORR(0), and the value of the second GCORR scaling function coefficient, GCORR(1), may be calibrated for each mode of operation of the linear RF power amplifier 22. As an example, the GCORR function circuit 842 may include a first set of GCORR scaling function coefficients that correspond to a first LTE band number and a second set of GCORR scaling function coefficients that correspond to a second LTE band number. In other words, the controller 50 may configure the GCORR function circuit 842 to adaptively determine the GCORR scaling function coefficients to be used to characterize the GCORR scaling function, GCORR(IPARA_AMP_SENSE), based upon the operational mode of the pseudo-envelope follower power management system 10PB and/or the band of operation at which the linear RF power amplifier 22 is transmitting.
In some alternative embodiments, the GCORR function circuit 842 may be configured by the controller 50 to provide a fixed value of the scaling factor, GCORR, as depicted in equation (9) as follows:
where the estimated power inductor inductance parameter, LEST, represents the measured or estimated inductance of the power inductor 16 between a specific range of frequencies and the parallel amplifier inductance estimate parameter, LCORR_EST, estimates the inductance of the parallel amplifier 35 between a specific range of frequencies, as discussed above.
As a non-limiting example, the analog VRAMP pre-distortion filter circuit 844 may include programmable time constants that may be configured by the controller 50. The controller 50 may configure the frequency response of the analog VRAMP pre-distortion filter circuit 844 to equalize the response of the pseudo-envelope follower power management system 10PA by adjusting the value of the programmable time constants.
In some embodiments of the parallel amplifier circuit 14PC, the analog VRAMP pre-distortion filter circuit 844 may be configured to compensate for the transfer function of the parallel amplifier 35 in conjunction with the power amplifier filter associated capacitance, CPA, the power amplifier associated inductance, LPA, (not shown), and the bypass capacitance, CBYPASS, of the bypass capacitor 19. For example, the controller 50 may configure the analog VRAMP pre-distortion filter circuit 844 to provide frequency peaking to compensate for the low pass filter response due to the combination of the power amplifier associated inductance, LPA, (not shown) and the power amplifier associated capacitance, CPA, (not shown) associated with the linear RF power amplifier 22. In some embodiments, the Laplace transfer function of the analog VRAMP pre-distortion filter circuit 844 may be represented by equation (10), as follows:
where, τZERO_PRE is a first time constant associated with a real-zero in the Laplace transfer function of the analog VRAMP pre-distortion filter circuit 844, and τPOLE_PRE is a second time constant associated with real-pole in the Laplace transfer function of the analog VRAMP pre-distortion filter circuit 844. The first time constant, τZERO_PRE, and the second time constant, τPOLE_PRE, may be configured by the controller 50 to pre-distort the VRAMP signal prior to adding the high frequency ripple compensation signal 838 to compensate for the non-ideal parallel amplifier output impedance of the parallel amplifier 35. The controller 50 τPOLE_PRE, of the analog VRAMP pre-distortion filter circuit 844 based on the RF modulation bandwidth of the linear RF power amplifier 22 associated with a wide-bandwidth modulation of a mode of operation of a communication device that includes the pseudo-envelope follower power management system 10PC. As an example, the controller 50 may configure the first time constant, τZERO_PRE, and second time constant, τPOLE_PRE, to provide peaking of the VRAMP signal in order to flatten the overall modulation frequency response of the pseudo-envelope follower power management system 10PC based on the wide-bandwidth modulation of a mode of operation of a communication device.
As another example, the controller 50 may configure the analog VRAMP pre-distortion filter circuit 844 to pre-distort the frequency response of the VRAMP signal such that the overall transfer function between the first control input 34, which receives the VRAMP signal, and the power amplifier collector 22A of the linear RF power amplifier 22 is substantially flat through the operating frequency range of the linear RF power amplifier 22. As a non-limiting example, the controller 50 may configure the first time constant, τZERO_PRE, to place a real-zero at around 11 MHz and the second time constant, τPOLE_PRE, to locate a real-pole at around 20 MHz. Accordingly, the analog VRAMP pre-distortion filter circuit 844 may be configured to provide a peaking response in order to compensate for the frequency response of the pseudo-envelope follower power management system 10PC and the low pass filter effects of the combination of the power amplifier associated inductance, LPA, (not shown), and the power amplifier filter associated capacitance, CPA, (not shown).
Otherwise, similar to the parallel amplifier output impedance compensation circuit 37B, depicted in
The parallel amplifier output impedance compensation circuit 37D also includes the first subtracting circuit 822, the ZOUT compensation high pass filter 824, the GCORR scalar circuit 826, the second subtracting circuit 828, the tune circuit 830, and the summing circuit 832. The first subtracting circuit 822 is configured to subtract the estimated switching voltage input signal 820, VSW_I, from the VRAMP signal to generate an expected difference signal 834, which is provided to the ZOUT compensation high pass filter 824. As discussed previously, the controller 50 may configure the programmable time constants associated with the ZOUT compensation high pass filter 824 to high pass filter the expected difference signal 834 in order to generate an estimated high frequency ripple signal 836.
Alternatively, the controller 50 may configure the estimated switching voltage output selection switch 816, S1, to provide the estimated switching voltage output 38B, VSW_EST, as the estimated switching voltage input signal 820, VSW_I, to the ZOUT compensation high pass filter 824. In this case, the ZOUT compensation high pass filter 824 high pass filters the expected difference signal 834 to generate the estimated high frequency ripple signal 836. As such, the estimated high frequency ripple signal 836 substantially corresponds to a scaled derivative of a switcher ripple current in the inductor current, ISW_OUT, of the power inductor 16 based on the estimated switching voltage output 38B, VSW_EST. Similar to the parallel amplifier output impedance compensation circuit 37B, when the controller configures the estimated switching voltage output selection switch 816, S1, to provide the estimated switching voltage output 38B, VSW_EST, as the estimated switching voltage input signal 820, VSW_I, the controller does not have the ability to adjust temporal alignment of the estimated switching voltage output 38B, VSW_EST, with the VRAMP signal in order to minimize the peak-to-peak ripple voltage on the power amplifier supply voltage, VCC, due to the non-ideal output impedance of the parallel amplifier 35.
In contrast, when the controller 50 configures the estimated switching voltage output selection switch 816, S1, to provide the delayed estimated switching voltage output 38D, VSW_EST_DELAY, as the estimated switching voltage input signal 820, VSW_I, the controller 50 may adjust the delay provided by the programmable delay circuitry 806 to temporally align the delayed estimated switching voltage output 38D, VSW_EST_DELAY, with the VRAMP signal.
The ZOUT compensation high pass filter 824 high pass filters the expected difference signal 834 to generate an estimated high frequency ripple signal 836 that may be scaled by the GCORR scalar circuit 826 to create the high frequency ripple compensation signal 838. The high frequency ripple compensation signal 838 is added to the analog pre-filtered VRAMP signal 814A, VRAMP_ANALOG_PRE-FILTERED, to form the compensated VRAMP signal, VRAMP_C. The compensated VRAMP signal, VRAMP_C, is provided as an input to the parallel amplifier 35. The parallel amplifier generates the parallel amplifier output voltage, VPARA_AMP, based on the difference between the compensated VRAMP signal, VRAMP_C, and the power amplifier supply voltage, VCC, at the power amplifier supply output 28.
The operation, configuration, and calibration of the tune circuit 830 of the parallel amplifier output impedance compensation circuit 37D, depicted in
Illustratively, as described before, the first time constant, τZERO_PRE, and second time constant, τPOLE_PRE, may be adjusted by the controller 50 to provide peaking of the VRAMP signal in order to equalize the overall frequency response between the first control input 34, which received the VRAMP signal, and the power amplifier collector 22A of a linear RF power amplifier 22. The controller 50 may configure the frequency response of the analog VRAMP pre-distortion filter circuit 844 to equalize the response of the pseudo-envelope follower power management system 10PA by adjusting the value of the programmable time constants of the analog VRAMP pre-distortion filter circuit 844, as previously described. In addition, similar to the parallel amplifier output impedance compensation circuit 37D, the controller 50 may configure the analog VRAMP pre-distortion filter circuit 844 of the parallel amplifier output impedance compensation circuit 37E to pre-distort the frequency response of the VRAMP signal such that the overall transfer function between the first control input 34, which received the VRAMP signal, and the power amplifier collector 22A of a linear RF power amplifier 22 is substantially flat through the operating frequency range of the linear RF power amplifier 22. For example, as described above, the controller 50 may configure the analog VRAMP pre-distortion filter circuit 844 to provide frequency peaking to compensate for the low pass filter response due to the combination of the power amplifier associated inductance, LPA, (not shown) and the power amplifier associated capacitance, CPA, (not shown) associated with the linear RF power amplifier 22.
However, unlike the parallel amplifier output impedance compensation circuit 37D, depicted in
Accordingly, the parallel amplifier output impedance compensation circuit 37E, may include an estimated switching voltage output selection switch 816, S1, having a first input 816A configured to receive the estimated switching voltage output 38B, VSW_EST, a second input 816B configured to receive the delayed estimated switching voltage output 38D, VSW_EST_DELAY, and an estimated switching voltage output selection switch output 816C. The controller 50 may configure the estimated switching voltage output selection switch 816. S1, to provide either the estimated switching voltage output 38B, VSW_EST, or the second input configured to receive the delayed estimated switching voltage output 38D, VSW_EST_DELAY, as a estimated switching voltage input signal 820, VSW_I, at the estimated switching voltage output selection switch output 816C. As discussed above, if the controller 50 configures the estimated switching voltage output selection switch 816, S1, to provide the delayed estimated switching voltage output 38D, VSW_EST_DELAY, the controller 50 may configure the delay provided by the programmable delay circuitry 806 to temporally optimize the relationship between estimated switching voltage input signal 820, VSW_I, and the VRAMP signal to minimize the high frequency voltage ripple generated as a result of the non-ideal output impedance characteristics of the parallel amplifier 35.
Similar to the parallel amplifier output impedance compensation circuit 37C, the parallel amplifier output impedance compensation circuit 37E also includes the first subtracting circuit 822, ZOUT compensation high pass filter 824, the GCORR scalar circuit 826, and the summing circuit 832. The first subtracting circuit 822 is configured to subtract the estimated switching voltage input signal 820, VSW_I, from the VRAMP signal to generate an expected difference signal 834, which is provided to the ZOUT compensation high pass filter 824. Similar to the operation of the parallel amplifier output impedance compensation circuit 37D, depicted in
Unlike the parallel amplifier output impedance compensation circuit 37D, depicted in
Alternatively, in some embodiments of the parallel amplifier output impedance compensation circuit 37E, controller 50 characterizes the GCORR function circuit 842 during either calibration of the pseudo-envelope follower power management system 10PD as described relative to the parallel amplifier output impedance compensation circuit 37C depicted in
Similar to the parallel amplifier output impedance compensation circuit 37E, depicted in
Unlike the previously described embodiments of the parallel amplifier output impedance compensation circuits 37B-E, depicted in
The VRAMP post-distortion filter circuit 850 may have a Laplace transfer function similar to the transfer function described by equation (11), as follows:
where, τZERO_POST, is a first post distortion time constant associated with zero in the VRAMP post-distortion filter circuit 850 and, τPOLE_POST, is a second post distortion time constant associated with pole of the VRAMP post-distortion filter circuit 850. The first post distortion time constant, τZERO_POST, and the second post distortion time constant, τPOLE_
Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
The present application claims priority to and is a continuation of U.S. patent application Ser. No. 14/022,858, filed Sep. 10, 2013, entitled “OUTPUT IMPEDANCE COMPENSATION OF A PSEUDO-ENVELOPE FOLLOWER POWER MANAGEMENT SYSTEM,” now U.S. Pat. No. 9,099,961. U.S. patent application Ser. No. 14/022,858 claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 13/316,229, filed Dec. 9, 2011, entitled “PSEUDO-ENVELOPE FOLLOWER POWER MANAGEMENT SYSTEM WITH HIGH FREQUENCY RIPPLE CURRENT COMPENSATION,” now U.S. Pat. No. 8,633,766, which claims priority to U.S. Provisional Patent Applications No. 61/421,348, filed Dec. 9, 2010; No. 61/421,475, filed Dec. 9, 2010; and No. 61/469,276, filed Mar. 30, 2011. U.S. patent application Ser. No. 14/022,858 claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 13/089,917, filed Apr. 19, 2011, entitled “PSEUDO-ENVELOPE FOLLOWING POWER MANAGEMENT SYSTEM,” now U.S. Pat. No. 8,493,141, which claims priority to U.S. Provisional Patent Application No. 61/325,659, filed Apr. 19, 2010. U.S. patent application Ser. No. 14/022,858 claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 13/218,400, filed Aug. 25, 2011, entitled “BOOST CHARGE-PUMP WITH FRACTIONAL RATIO AND OFFSET LOOP FOR SUPPLY MODULATION,” now U.S. Pat. No. 8,519,788, which claims priority to U.S. Provisional Patent Application No. 61/376,877, filed Aug. 25, 2010. U.S. patent application Ser. No. 13/218,400 is a continuation-in-part of U.S. patent application Ser. No. 13/089,917, filed Apr. 19, 2011, which claims priority to U.S. Provisional Patent Application No. 61/325,659, filed Apr. 19, 2010. All of the applications listed above are hereby incorporated herein by reference in their entireties.
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