OUTPUT INTERFACING DEVICE COMPENSATED IN LOAD AND CORRESPONDING ELECTRONIC CIRCUIT

Abstract

An output interfacing device is provided, which receives at its input an input signal and provides at its output, an output signal to an external load. The output interfacing device invertes the effect of the capacitance of the external load on the slew rate of the output signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 already commented on in relation to the prior art, shows an electrical diagram of a first classic interfacing device;

FIG. 2, also commented on in relation to the prior art, shows the performances of the interfacing device of FIG. 1;

FIG. 3, already commented on in relation to the prior art, shows an electrical diagram of a second classic interfacing device;

FIG. 4, also commented on in relation to the prior art, shows the performances of the interfacing device of FIG. 3;

FIG. 5 shows the electrical diagram of an interfacing device in one example of the present disclosure; and

FIG. 6 shows the performances of the interfacing device shown in FIG. 5, for three values of output capacitance.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The general principle of the disclosure is based, for example, on the reduction and the increase of the slew rate of the output signal of an interfacing device.

Simplification of the description, the rest of the document will simply describe the specific case of a NMOS type output buffer. Those skilled in the art will extend without difficulty this lesson to any types of output buffers, especially de PMOS and “push-pull” type output buffers.

In relation to FIG. 5 an output interfacing device 500 will be described in one example of the disclosure.

In this example, the output interfacing device 500 comprises:

• • a first inverter INV1 corresponding to the command stage E1 described in relation to FIG. 1;
  • an output stage E2 classic in itself, comprising an output transistor TN2: and
  • inverting means 51 specific to the present disclosure.

For reasons of clarity, the detailed architecture and the operation of the first inverter INV1 are not described again below.

By way of reminder, this first inverter INV1 is formed by a first transistor TP1 and a second transistor TN1. mounted with common gate and drain.

The output interfacing device 500 comprises an input 1 to which is applied an input SIN and an output 2 signal delivering an output signal SOUT to an external load C1 (which is for example a capacitance of 50 pF).

As shown in FIG. 5, the means for inverting 51 the effect of the external load capacitance on the slew rate of the output signal comprise:

• • means of decreasing 52 the slew rate of the output signal comprising a control resistor RSL mounted between the drain of the first transistor TP1 and the drain of the second transistor TN1; and
  • means of increasing 53 the slew rate of the output signal comprising a feed back 54 of the drain of the output transistor TN2 to its gate.

As may be seen below, the feed back 54 creates a feed back loop, which accelerates the switching dynamic of the device.

In one example, the feed back is carried out via a control capacitance CSL. Advantageously, initialisation means 56 are provided to discharge the control capacity CSL. The initialisation means 56 comprise a fourth PMOS type transistor mounted with common source and drain with a fifth NMOS type transistor. The fourth PMOS transistor is commanded by the input signal SIN (which is applied to the gate of the transistor), and the fifth transistor NMOS is commanded by the command signal SCOM delivered by the first inverter INV1. Consequently, at each switching of the input signal from VCC to VSS, the fourth PMOS and fifth NMOS transistors are made conductive, which has the effect of short circuiting the control capacitance CSL and thus of discharging it.

In this example, the output interfacing device 500 further comprises command means 55 permitting the feed back to be authorised or not.

As shown by FIG. 5, the command means 55 comprise:

• • a second inverter INV2 receiving at its input the command signal SCOM and providing at its output an inverted command signal SCOM*; and
  • a third transistor TN3, whose source is connected to the gate of the output transistor TN2 and whose drain is connected to one end of the control capacitance CSL, forming a switch commanded by the inverted command signal SCOM* (applied to the gate of the transistor TN3).

Hereunder in reference to FIG. 5 is described the operation of the output interfacing device 500, for the switching of the input signal SIN from VCC to VSS. By way of example, it is considered that the second inverter INV2 switches, which is to say it delivers an inverted command signal SCOM substantially equal to VCC, when the input signal SIN is greater than 1.5V.

When the input signal SIN is greater than or equal to VSS and less than or equal to 1.5V, the capacitance of the gate (not shown) of the output transistor TN2 is loaded via the command signal SCOM. The increase in voltage of the command signal SCOM is controlled (which is to say delayed) by the control resistor RSL. The consequence of this is to delay the command of the output transistor TN2, and therefore to slow down the switching speed of the device. It is important to note that, in this case, the second inverter INV2 delivers an inverted command signal SCOM* substantially equal to VSS. The third transistor TN3 is therefore made non conductive (switch open), which has the effect of deactivating the feed back loop. It may also be noted that the control resistor RSL improves the immunity of the device to interference and/or electromagnetic interference.

In return, when the input signal SIN is greater than 1.5V and less than or equal to VCC, the second inverter INV2 delivers an inverted command signal SCOM* substantially equal to VCC, the third transistor TN3 is therefore made conductive (switch closed) and the feed back loop activated. The gate capacitance (not shown) of the output transistor TN2 is then loaded via the output signal SOUT (which is supplied by the control capacitance CSL). The consequence of this is to accelerate the command of the output transistor TN2, and therefore to increase the switching speed of the device.

The addition of the control resistor RSL with the feed back loop (control capacitance CSL) permits the effect of the external load capacitance C1 on the slew rate) of the output signal SOUT to be inverted.

Now in relation to FIG. 6 are presented the dynamic performances (falling time for the output signal SOUT measured at the terminals of the capacitance C1) of the output interfacing device 500 (FIG. 5) in response to an input signal SIN in the form of a conductive voltage scale of a voltage substantially equal to the power supply VCC (4V) to VSS (0V).

More precisely, FIG. 6 shows three curves references 601 to 603 showing the voltage (in Volts) of the output signal SOUT as a function of temps t expressed in microseconds (μs) for three values of capacitance C1. Consequently, the curve with the reference 601 corresponds to a capacitance of 50 pF, the curve with the reference 602 corresponds to a capacitance of 200 pF and the curve with the reference 603 corresponds to a capacitance of 500 pF.

As shown in FIG. 6, the rapidity of the output interfacing device 500 increases when the output capacitive load increases. In fact, if the curve 601 is compared with the curve 603, it may be seen that; with a capacitance of 500 pF at the output of the device, it takes approximately twice less time to pass from VCC to VSS.

An example of the disclosure provides a technique, which permits simple and efficient control of the slew rate of the output signal of an output interfacing device.

An example of the disclosure provides a system, which permits the slew rate of the output signal to be accelerated, when the capacitance of the load at the output of the device increases.

It should be noted that the formulation of this advantage is, in itself, novel and inventive as those skilled in the field of output interfacing devices have not yet envisaged obtaining a slew rate of the output signal that is increasingly higher for a capacitive load that is increasingly higher.

An example of the disclosure provides a system, which generates reduced interference with respect to the classic output interfacing devices.

An example of the disclosure provides a system, which is simple and inexpensive to make.

Although the present disclosure has been described with reference to one or more examples, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the disclosure and/or the appended claims.

Claims

1. Output interfacing device receiving at its input an input signal and providing at its output, to an external load, an output signal, wherein the device comprises: means of inverting the effect of the capacitance of the external load on the slew rate of the output signal, said inverting means comprising means of increasing the slew rate of the output signal, andmeans of initialising said increasing means, allowing said increasing means to be initialised every time that said input signal switches between a first level and a second level.

2. Output interfacing device according to claim 1, said device further comprising means of switching said output signal, wherein said inverting means of the effect of the capacitance of the external load on the slew rate of the output signal comprise means of decreasing the slew rate of the output signal, allowing a command of said switching means to be delayed, as long as a predetermined command criterion has not been verified.

3. Output interfacing device according to claim 2, said device comprising first and second transistors mounted with common gate and drain, so as to form a first inverter, wherein said means of decreasing the slew rate of the output signal comprise at least one resistive element mounted between the first transistor and the second transistor.

4. Output interfacing device according to any of claim 1, wherein said means of increasing the slew rate of the output signal comprise feed back means of the output of said switching means on the input of said switching means.

5. Output interfacing device according to claim 4, wherein said feed back means comprise at least one capacitive element.

6. Output interfacing device according to any of claim 1, wherein the device comprises command means of said feed back means, for allowing said feed back means to be blocked as long as said predetermined command criterion has not been verified.

7. Output interfacing device according to claim 6, wherein said command means comprise: a third transistor forming a switch and mounted between said feed back means and said switching means; anda second inverter acting on said third transistor so that:as long as said predetermined command criterion has not been verified, then said third transistor is placed in a non conductive state.

8. Output interfacing device according to claim 1, wherein said initialisation means comprise a fourth PMOS type transistor mounted with common source and drain with a fifth NMOS type transistor.

9. Electronic circuit wherein the circuit comprises an output interfacing device according to claim 1.

10. Output interfacing device comprising: an input receiving an input signal;an output providing an output signal to an external load;first and second transistors mounted with common gate and drain, so as to form a first inverter, and at least one resistive element mounted between the first transistor and the second transistor;a first switch, which switches the output signal on the output;feed back from the output of the switch to an input of the first switch; anda circuit, which blocks the feed back as long as a predetermined command criterion for the first switch has not been verified.

11. Output interfacing device according to claim 10, wherein said feed back comprises at least one capacitive element.

12. Output interfacing device according to claim 10, wherein said circuit, which blocks the feed back, comprises: a third transistor forming a second switch and mounted between said feed back and said first switch; anda second inverter acting on said third transistor so that:as long as said predetermined command criterion has not been verified, then said third transistor is placed in a non conductive state.

13. Output interfacing device according to claim 10, and further comprising a fourth PMOS type transistor mounted with common source and drain with a fifth NMOS type transistor, the common source and drain being coupled to the output.

14. An electronic circuit comprising an output interfacing device according to claim 10.

15. A method comprising: receiving an input signal at an input of an output interfacing device providing at its output an output signal to an external load;inverting an effect of a capacitance of the external load on the slew rate of the output signal, comprising increasing the slew rate of the output signal, andinitialising the slew rate of the output signal every time that said input signal switches between a first level and a second level.