Patent Application
20110235222
The present invention relates to a current limit and output short to ground protection circuit, making use of voltage clamping circuitry.
Normally, for electronic devices such as power amplifier ICs and voltage regulator ICs, an abnormal situation, when it occurred, may affect such ICs. One of such situations may occur when its output pin is short circuited to ground. When this happens, there will be a large current flow through its power transistor. This situation can damage the device and the power supply circuit to the device. In order to prevent this problem, many devices would incorporate a protection circuit for protecting an output terminal from being short circuited to ground, which is herein also referred to as an output short to ground protection circuit, or simply a protection circuit. Such a protection circuit typically functions to turn off output stage upon the occurrence of the abnormal situation. However, in other types of protection circuits, it just limits current instead of turning off the output stage.
The output short to ground protection circuit has two types of methods to detect output short to ground. One is by monitoring the output voltage, and the other is detecting current through output stage. The present invention relates to the method of monitoring the output voltage.
A typical circuit to detect output short to ground by monitoring the output voltage is as shown in
Though this circuit is effective, it has the drawback of taking a large implementation area. That is, more circuit elements, hence more mask area, are required for this circuit. This has the disadvantage of extra costs incurred on the IC manufacturer.
The present invention is intended to solve such problems, and it is an object of the present invention to provide a current limiting type output short to ground protection circuit that utilizes less circuit elements.
The purpose of this invention is to limit output current during IC start-up or when the output pin is short circuited to ground.
The present invention makes use of voltage clamping circuitry to limit output current.
According to one embodiment of the present invention, an output short to ground protection circuit for an electronic device having an output power transistor, an output terminal and a capacitor connected between the output terminal and the ground, said protection circuit comprises: an NMOS transistor having a drain terminal connected to a gate terminal of the output power transistor; a fixed voltage generator connected to a gate terminal of the NMOS transistor; a first voltage clamping circuit having a first terminal connected to the gate terminal of the output power transistor and a second terminal connected to a source terminal of the NMOS transistor; and a second voltage clamping circuit having a first terminal connected to said source terminal of said NMOS transistor and second terminal connected to the output terminal.
The following description explains the best mode embodiment of the present invention.
Referring to
Based on a first embodiment of the present invention, the output short to ground protection circuit 110 comprises voltage clamping circuits 111 and 112, fixed voltage generator 113, and NMOS transistor M2.
Fixed voltage generator 113 may typically be in the form of a voltage regulator or a voltage reference circuit. The fixed voltage generator 113 serves to provide a fixed voltage for biasing NMOS transistor M2 via its gate terminal.
One of the two terminals of voltage clamping circuit 111 is connected to the gate terminal of NMOS transistor M1, whereas the other terminal is connected to the source terminal of NMOS transistor M2.
One of the two terminals of voltage clamping circuit 112 is connected to the source terminal of NMOS transistor M2, whereas the other terminal is connected to the output terminal, Vout 117.
Further provided is an electronic device having a current source 116 connected to the gate terminal of NMOS transistor M1, a feedback block 114 connected between output terminal Vout 117 and the gate terminal of NMOS transistor M1, and a capacitor 115 connected between output terminal Vout 117 and the ground.
The operation of the first embodiment of the present invention is as follows.
In
V
A
=V
clamp2
+V
out.
Upon startup, voltage at the output terminal Vout 117 is low (Vout 117≈0), due to capacitor 115 still in the process of being charged up. Hence, VA is fixed by voltage clamping circuit 112 to Vclamp2. Fixed voltage from fixed voltage generator 113 serves to bias the gate of NMOS transistor M2 so as to cause it to conduct when the potential at the output terminal, Vout 117 is low. That is, VA≈Vclamp2. The fixed voltage from the fixed voltage generator 113 is less than Vclamp2+Vout+Vth,M2, where Vth,M2 is the threshold voltage of NMOS transistor M2.
Effectively, this means that the voltage between gate and source of NMOS transistor M1, VGS,M1 is equal to VA≈Vclamp2. This has the effect of limiting the output current, Iout 118.
Upon gradual charging of capacitor 115, the potential at the output terminal Vout 117 will increase as well.
VA will correspondingly rise to become equal to Vclamp2+Vout, which is high enough to cause NMOS transistor M2 to turn off. As a result
V
GS,M1
=V
clamp1
+V
clamp2,
where Vclamp1 is the potential difference between node A and the gate terminal of NMOS transistor M1, as a result of voltage clamping circuit 111. The resultant current of Iout 118 as a result VGS,M1=Vclamp1+Vclamp2 is the current under normal working conditions.
For a condition where the output terminal Vout 117 is short circuited to ground, the same condition as that produced at the startup is produced. Thus, VA≈Vclamp2, causing NMOS transistor M2 to turn on. This results in VGS,M1=Vclamp2, thus limiting the current Iout 118.
A second embodiment of the present invention is shown in
As can be seen in
The gate terminal of NMOS M4 is connected to its drain terminal, which is further connected to the source terminal of NMOS transistor M2. The source terminal of NMOS transistor M4 is connected to the drain terminal of NMOS transistor M5.
The gate terminal of NMOS transistor M5 is connected to its drain terminal, whereas its source terminal is connected to the output terminal, Vout 117.
Hence,
V
clamp1
=V
GS,M3
V
clamp2
=V
GS,M4
+V
GS,M5.
NMOS transistor M3 is a diode connected transistor (or a diode connection transistor). Similarly, each of NMOS transistors M4 and M5 is a diode connected transistor. The number of the diode connected transistor for the voltage clamping circuit 111 is at least one, and the number of the diode connected transistor for the voltage clamping circuit 112 is at least one.
The operation of the second embodiment is similar to that of the first embodiment.
Although the present invention has been described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims, unless they depart therefrom.
