Patent Application
20200333817
The present invention relates to an output stage circuit of a voltage regulator and the related voltage regulator, and more particularly, to an output stage circuit implemented with middle voltage devices and its related voltage regulator.
The push-pull voltage regulator is a low dropout (LDO) regulator with both source and sink capabilities. More specifically, the push-pull voltage may have a PMOS output transistor operated as a current source and an NMOS output transistor providing a current sink path, so as to provide push-pull regulation.
When the push-pull voltage regulator operates in a high voltage domain, i.e., receiving a high power supply voltage, the output transistors should be high voltage devices having a withstand voltage conforming to the power supply voltage. If the voltage regulator needs to be implemented with middle voltage devices, the output voltage range of the voltage regulator is limited; otherwise, the cross voltage of an output transistor may exceed the output transistor's withstand voltage. Thus, there is a need for improvement over the prior art.
It is therefore an objective of the present invention to provide a novel voltage regulator, which is capable of realizing a large output voltage range only with the usage of middle voltage devices and/or low voltage devices, so as to reduce the chip area and circuit costs.
An embodiment of the present invention discloses an output stage circuit of a voltage regulator, which comprises a first output transistor, a first voltage generator and a first stack transistor. The first stack transistor is coupled between the first output transistor and an output terminal of the voltage regulator, and comprises a first terminal, a second terminal and a third terminal. The first terminal is coupled to the output terminal of the voltage regulator. The second terminal is coupled to the first output transistor. The third terminal is coupled to the first voltage generator.
Another embodiment of the present invention discloses a voltage regulator, which comprises an amplifier, a control circuit, a level shifter and an output stage circuit. The control circuit is coupled to the amplifier. The level shifter is coupled to the control circuit. The output stage circuit is coupled to the level shifter, and comprises a first output transistor, a first voltage generator and a first stack transistor. The first stack transistor is coupled between the first output transistor and an output terminal of the voltage regulator, and comprises a first terminal, a second terminal and a third terminal. The first terminal is coupled to the output terminal of the voltage regulator. The second terminal is coupled to the first output transistor. The third terminal is coupled to the first voltage generator.
Another embodiment of the present invention discloses an output stage circuit of a push-pull voltage regulator, which comprises a high-side output transistor, a low-side output transistor, a first voltage generator and a first stack transistor. The first stack transistor is coupled between the high-side output transistor and an output terminal of the push-pull voltage regulator, and comprises a first terminal, a second terminal and a third terminal. The first terminal is coupled to the output terminal of the push-pull voltage regulator. The second terminal is coupled to the high-side output transistor. The third terminal is coupled to the first voltage generator.
Another embodiment of the present invention discloses an output stage circuit of a push-pull voltage regulator, which comprises a high-side output transistor, a low-side output transistor, a first voltage generator and a first stack transistor. The first stack transistor is coupled between the low-side output transistor and an output terminal of the push-pull voltage regulator, and comprises a first terminal, a second terminal and a third terminal. The first terminal is coupled to the output terminal of the push-pull voltage regulator. The second terminal is coupled to the low-side output transistor. The third terminal is coupled to the first voltage generator.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Please refer to
In addition, the voltage divider 108, which may be composed of a resistor ladder having resistors R1 and R2, is coupled between the output terminal of the voltage regulator 10 and the amplifier 102, to generate the feedback voltage VFB based on the output voltage VOUT of the voltage regulator 10. A capacitor C1, which may be included in the voltage regulator 10 or disposed alone, is coupled to the output terminal of the voltage regulator 10, in order to improve the stability of the voltage regulator 10.
As shown in
Please refer to
More specifically, the high-side output transistor MP may be a PMOS transistor and the low-side output transistor MN may be an NMOS transistor. The stack transistor MS1, which is coupled between the high-side output transistor MP and the output terminal of the voltage regulator 20, is also a PMOS transistor. As for the stack transistor MS1, the drain terminal is coupled to the output terminal of the voltage regulator 20, the source terminal is coupled to the high-side output transistor MP, and the gate terminal is coupled to the voltage generator 220.
In the output stage circuit 208 of the voltage regulator 20, the output transistors MP and MN and the stack transistor MS1 are middle voltage devices, while the output stage circuit 208 still operates in the high power supply voltage VPP that may be greater than the withstand voltage of the middle voltage devices. With the implementation of the stack transistor MS1, the voltage VH may be pushed to a higher value even if the output voltage VOUT is lower. This clamps the drain-to-source voltage of the output transistor MP to be within its withstand voltage, i.e., the withstand voltage of the middle voltage device, so as to prevent overstress appearing on the output transistor MP. In addition, the voltage generator 220 may output a proper gate control voltage to the stack transistor MS1, to turn on the stack transistor MS1 and allow the drain-to-source voltage of the stack transistor MS1 to be within its withstand voltage, so as to prevent overstress appearing on the stack transistor MS1.
In an embodiment, the voltage generator 220 may output the gate control voltage to the stack transistor MS1 according to the output voltage VOUT of the voltage regulator 20. For example, the voltage generator 220 may be configured with several candidate voltages that may be used as its output voltage, and the gate control voltage may be selected from the candidate voltages via the control of registers or by other methods. As a voltage source for a circuit system, the voltage regulator 20 may output a constant voltage value; that is, the output voltage VOUT is predetermined and fixed when the voltage regulator 20 is in use. Therefore, the proper value of the gate control voltage for the stack transistor MS1 may also be predetermined based on the output voltage VOUT. For example, when the output voltage VOUT is higher, a candidate voltage with a higher value may be selected as the gate control voltage to be received by the stack transistor MS1; when the output voltage VOUT is lower, another candidate voltage with a lower value may be selected as the gate control voltage to be received by the stack transistor MS1, so as to achieve proper cross voltages of the output transistor MP and the stack transistor MS1.
Please note that the voltage regulator 20 shown in
It should also be noted that the circuit structure of the voltage regulator 20 is one of various embodiments of the present invention. Please refer to
With the implementation of the stack transistor MS2, the voltage VL may be pushed to a lower value even if the output voltage VOUT is higher. This clamps the drain-to-source voltage of the output transistor MN to be within its withstand voltage, i.e., the withstand voltage of the middle voltage device, so as to prevent overstress appearing on the output transistor MN. In addition, the voltage generator 320 may output a proper gate control voltage to the stack transistor MS2, to turn on the stack transistor MS2 and allow the drain-to-source voltage of the stack transistor MS2 to be within its withstand voltage, so as to prevent overstress appearing on the stack transistor MS2. The detailed implementations and operations of the stack transistor MS2 and the voltage generator 320 are similar to those of the stack transistor MS1 and the voltage generator 220 shown in
As mentioned above, the stack transistor MS1 may prevent the overstress problem when the output voltage VOUT tends to a lower value. This extends the output voltage range of the voltage regulator 20 by realizing lower output voltages without the usage of high voltage devices. Similarly, the stack transistor MS2 may prevent the overstress problem when the output voltage VOUT tends to a higher value. This extends the output voltage range of the voltage regulator 30 by realize higher output voltages without the usage of high voltage devices. In a further embodiment, both the stack transistors MS1 and MS2 are implemented, as the voltage regulator 40 shown in
In an embodiment, the power supply voltage VPP may be 13.5V, a high supply voltage in the system. The circuit elements in the voltage regulator of the present invention may be implemented with middle voltage devices having a withstand voltage approximately equal to 7V, instead of high voltage devices capable of withstanding the 13.5V high voltage. In such a situation, the output voltage range of the voltage regulator may be from 3V to 10V. As a result, the voltage regulator may achieve a wider output voltage range without the usage of high voltage process. In addition, since no high voltage process and devices are used in the voltage regulator, the chip area and circuit costs may be saved. For example, in the voltage regulator 40 as shown in
Please note that the present invention aims at providing an output stage circuit and a related voltage regulator having a wide output voltage range without the usage of high voltage devices. Those skilled in the art may make modifications and alternations accordingly. For example, the abovementioned voltage values of the power supply voltage VPP and the withstand voltages of the high voltage devices and the middle voltage devices are merely an example intended to better illustrate the embodiments, and may not become a limitation on the scope of the present invention. In addition, in the above embodiments, the proposed output stage circuits are realized in a push-pull voltage regulator. In another embodiment, the output stage circuits of the present invention may also be applicable to other types of voltage regulators.
To sum up, the present invention provides a voltage regulator capable of realizing a large output voltage range with the usage of middle voltage devices and/or low voltage devices. In the voltage regulator of the present invention, the output stage circuit includes a stack transistor coupled between the output transistor and the output terminal of the voltage regulator. The stack transistor clamps the drain-to-source voltage of the output transistor, and is well controlled by receiving a proper gate control voltage from a voltage generator. Therefore, the output stage circuit with a high power supply voltage may be implemented with middle voltage devices only, and the overstress problem may be prevented by disposing the stack transistor. As a result, the output voltage range of the voltage regulator may be extended without the usage of any high voltage devices, so as to save the chip area and circuit costs.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
