Output Voltage Regulation Apparatus and Method

Abstract

An output voltage regulation apparatus includes a voltage regulation circuit, a control circuit, a power stage circuit, a filtering network, and a feedback network. The feedback network is configured to output a feedback voltage to a feedback voltage node of the control circuit. The voltage regulation circuit is configured to regulate the feedback voltage. The control circuit is configured to switch on or off power transistors in the power stage circuit. The filtering network is configured to perform filtering on an output voltage of the power stage circuit to obtain the regulated output voltage.

Description

TECHNICAL FIELD

Embodiments of this application relate to the field of power management, and in particular, to an output voltage regulation apparatus and method.

BACKGROUND

In recent years, consumer electronics such as smartphones and tablet computers show a trend of rapid development. A power management integrated circuit (PMIC) is a power device for managing host systems of the consumer electronics, and the PMIC has advantages such as high integration, high conversion efficiency, and low costs. An integrated voltage regulator (IVR) is an important component of the PMIC. With rapid generational shift of the consumer electronics, the consumer electronics have higher requirements on performance of the IVR. To reduce system power consumption, an output voltage of the IVR needs to be dynamically and rapidly regulated in real time based on post-stage load.

The output voltage is usually rapidly regulated by rapidly regulating a reference voltage or a value of a feedback resistor. However, these solutions usually cause an overshoot, an undershoot, or a glitch of the output voltage. For example, as shown in FIG. 1, FIG. 1 shows a waveform when the output voltage is rapidly regulated by rapidly regulating the reference voltage. When a reference voltage V_REF jumps from V_REF1 to V_REF2 after duration t_ramp, an output voltage V_O also rapidly increases from V_O1. However, a waveform of V_O usually experiences an overshoot, that is, ΔV marked in FIG. 1. After a recovery time t_setting, V_O is stabilized at a target value V_O2. In addition, shorter duration t_ramp indicates a larger overshoot ΔV and a longer recovery time t_setting. On the contrary, when V_REF jumps downwards, V_O also experiences a corresponding undershoot, and can reach a stable value only after a recovery time after the undershoot.

In conclusion, the solution of rapidly regulating the output voltage of the IVR is likely to cause the overshoot, the undershoot, or the glitch of the output voltage, and the recovery time of the overshoot or the undershoot is very long, affecting system performance to some degree.

SUMMARY

Embodiments of this application provide an output voltage regulation apparatus and method, to implement rapid voltage regulation, and to resolve a problem that an overshoot or an undershoot occurs in an output voltage regulation process.

Specific technical solutions provided in the embodiments of this application are as follows.

According to a first aspect, an output voltage regulation apparatus is provided. A voltage regulation circuit is added into the output voltage regulation apparatus. On a basis of maintaining a reference voltage V_REF in a control circuit unchanged, a current of a feedback voltage V_FB node in the control circuit is changed using the voltage regulation circuit, to rapidly regulate an output voltage V_O. In this way, not only rapid regulation of the output voltage can be implemented, but also an overshoot, an undershoot, or a glitch that occurs in an output voltage regulation process can be inhibited, and a time of regulating the output voltage to a regulated voltage is effectively shortened.

In a possible design, the apparatus includes the voltage regulation circuit, the control circuit, a power stage circuit, a filtering network, and a feedback network, where the voltage regulation circuit, the control circuit, the power stage circuit, the filtering network, and the feedback network form a loop, an input end of the feedback network is connected to an output end of the filtering network and is configured to acquire an output voltage V_O of the filtering network, and an output end of the feedback network is connected to a feedback voltage node of the control circuit and is configured to output a feedback voltage to the feedback voltage node of the control circuit, an output end of the voltage regulation circuit is connected between the output end of the feedback network and the feedback voltage node of the control circuit and is configured to regulate a current I of the feedback voltage node, an output end of the control circuit is connected to an input end of the power stage circuit and is configured to regulate an output duty cycle of the power stage circuit based on the current I of the feedback voltage node, and an input end of the filtering network is connected to an output end of the power stage circuit and is configured to perform filtering on the output duty cycle of the power stage circuit, to obtain a regulated output voltage V_O. The output voltage V_O is rapidly regulated by regulating the current of the feedback node, providing an excellent inhibition effect on an overshoot or an undershoot of the output voltage such that a voltage regulation effect is more rapidly and stably achieved.

In a possible design, the voltage regulation circuit includes a digital-to-analog conversion circuit and a voltage-to-current conversion circuit, the digital-to-analog conversion circuit is configured to receive a digital signal used to represent voltage regulation, generate a first reference voltage signal based on the digital signal, and transmit the first reference voltage signal to the voltage-to-current conversion circuit, and the voltage-to-current conversion circuit is configured to receive the first reference voltage signal, convert the first reference voltage signal to a current regulation signal, and transmit the current regulation signal to the feedback voltage node.

In a possible design, the voltage regulation circuit is further configured to inject a current to the feedback voltage node or receive a current flowing out of the feedback voltage node, based on the current regulation signal.

In a possible design, the feedback network includes a first feedback resistor R_f1 and a second feedback resistor R_f2, and an output point of the feedback network is located between the first feedback resistor and the second feedback resistor, and the output voltage V_O and the current I of the feedback voltage node satisfy the following relationship, V_O=V_REF*(1+R_f1/R_f2)+I*R_f1, where V_REF is a second reference voltage signal obtained by the control circuit.

According to a second aspect, an output voltage regulation method is provided. On a basis of maintaining a reference voltage V_REF in a control circuit unchanged, a current of a feedback voltage V_FB node in the control circuit is changed, to rapidly regulate an output voltage V_O. In this way, not only rapid regulation of the output voltage can be implemented, but also an overshoot, an undershoot, or a glitch that occurs in an output voltage regulation process can be inhibited, and a time of regulating the output voltage to a regulated voltage is effectively shortened.

In a possible design, an output voltage V_O of a filtering network is acquired and a feedback voltage is output to a feedback voltage node of the control circuit using a feedback network, a current I of the feedback voltage node is regulated using a voltage regulation circuit, an output duty cycle of the power stage circuit is regulated based on the current I of the feedback voltage node using the control circuit, and filtering is performed on the output duty cycle of the power stage circuit using the filtering network, to obtain a regulated output voltage V_O. The output voltage V_O is rapidly regulated by regulating the current of the feedback node, providing an excellent inhibition effect on an overshoot, an undershoot, or a glitch of the output voltage such that a voltage regulation effect is more rapidly and stably achieved.

In a possible design, the regulating a current I of the feedback voltage node using a voltage regulation circuit is receiving a digital signal used to represent voltage regulation, generating a first reference voltage signal based on the digital signal, converting the first reference voltage signal to a current regulation signal, and transmitting the current regulation signal to the feedback voltage node.

In a possible design, the regulating a current I of the feedback voltage node using a voltage regulation circuit is injecting a current to the feedback voltage node or receiving a current flowing out of the feedback voltage node, based on the current regulation signal.

In a possible design, the output voltage V_O and the current I of the feedback voltage node satisfy the following relationship, V_O=V_REF*(1+R_f1/R_f2)+I*R_f1, where V_REF is a second reference voltage signal obtained by the control circuit, R_f1 is a first feedback resistor in the feedback network, R_f2 is a second feedback resistor in the feedback network, and an output point of the feedback network is located between the first feedback resistor and the second feedback resistor.

According to a third aspect, a power supply is provided. The power supply includes the output voltage regulation apparatus according to the first aspect or any possible design of the first aspect.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic diagram of a waveform when an output voltage is rapidly regulated.

FIG. 2 is a first schematic structural diagram of an output voltage regulation apparatus according to an embodiment of this application.

FIG. 3 is a second schematic structural diagram of an output voltage regulation apparatus according to an embodiment of this application.

FIG. 4 is a third schematic structural diagram of an output voltage regulation apparatus according to an embodiment of this application.

FIG. 5 is a fourth schematic structural diagram of an output voltage regulation apparatus according to an embodiment of this application.

DESCRIPTION OF EMBODIMENTS

The following describes in detail the embodiments of this application with reference to accompanying drawings.

A basic concept of a voltage regulation solution in the embodiments of this application is the following. A voltage regulation circuit is added into an output voltage regulation apparatus. On a basis of maintaining a reference voltage V_REF in a control circuit unchanged, a current of a feedback voltage V_FB node in the control circuit is changed using the voltage regulation circuit, to rapidly regulate an output voltage V_O. In this way, not only rapid regulation of the output voltage can be implemented, but also an overshoot, an undershoot, or a glitch that occurs in an output voltage regulation process can be inhibited, and a time of regulating the output voltage to a regulated voltage is effectively shortened.

The embodiments of this application may be applied to a rapid voltage regulation device related to a direct current (DC) to DC converter (DC to DC Converter or DC-DC) or a rapid voltage regulation device related to an alternating current (AC) to DC converter (AC to DC Converter or AC-DC). The output voltage regulation apparatus in the embodiments of this application may be an IVR, or any apparatus that can rapidly regulate an output voltage by applying a method of the embodiments of this application.

An output voltage regulation apparatus and method provided in the embodiments of this application are described in detail below.

As shown in FIG. 2, an output voltage regulation apparatus 200 includes a voltage regulation circuit 201, a control circuit 202, a power stage circuit 203, a feedback network 204, and a filtering network 205. The voltage regulation circuit 201, the control circuit 202, the power stage circuit 203, the feedback network 204, and the filtering network 205 form a loop. A specific connection relationship between the circuits is an input end of the feedback network 204 is connected to an output end of the filtering network 205, an output end of the feedback network 204 is connected to the control circuit 202, and is connected to a feedback voltage node of the control circuit 202, an output end of the voltage regulation circuit 201 is connected between the output end of the feedback network 204 and the feedback voltage node of the control circuit 202, an output end of the control circuit 202 is connected to an input end of the power stage circuit 203, and an output end of the power stage circuit 203 is connected to the filtering network 205. Optionally, the filtering network includes an inductor L and a capacitor C. An output signal of the output end of the filtering network 205 is an output voltage V_O.

The feedback network 204 is configured to acquire the output voltage V_O of the filtering network 205, and output a feedback voltage to the feedback voltage node of the control circuit 202.

The voltage regulation circuit 201 is configured to regulate a current I of the feedback voltage node of the control circuit 202.

The control circuit 202 is configured to regulate an output duty cycle of the power stage circuit 203 based on the current I of the feedback voltage node of the control circuit 202.

The filtering network 205 is configured to perform filtering on the output duty cycle of the power stage circuit 203, to obtain a regulated output voltage V_O.

Optionally, the voltage regulation circuit 201 injects a current to or draws a current from the feedback voltage node of the control circuit 202, to regulate the current I of the feedback voltage node of the control circuit 202. When the current I of the feedback voltage node changes, a value of the output voltage V_O may be affected. In this embodiment of this application, the output voltage V_O is rapidly regulated by rapidly regulating the current I of the feedback voltage node. The drawing a current indicates receiving a current flowing out, in other words, the voltage regulation circuit 201 receives a current flowing out of the feedback voltage node.

Optionally, as shown in FIG. 3, the voltage regulation circuit 201 includes a digital-to-analog conversion circuit 2011 and a voltage-to-current conversion circuit 2012.

When the output voltage V_O needs to be regulated, the voltage regulation circuit 201 generates a digital signal for voltage regulation, and the digital signal represents information of the voltage regulation, such as an amplitude. The digital-to-analog conversion circuit 2011 is configured to receive the digital signal used to represent the voltage regulation, generate a first reference voltage signal based on the digital signal, and transmit the first reference voltage signal to the voltage-to-current conversion circuit 2012.

The voltage-to-current conversion circuit 2012 is configured to receive the first reference voltage signal, convert the first reference voltage signal to a current regulation signal, and transmit the current regulation signal to the feedback voltage node. The current regulation signal includes injecting a current to or drawing a current from the feedback voltage node. Optionally, the voltage regulation circuit 201 is further configured to inject a current to the feedback voltage node or receive a current flowing out of the feedback voltage node, based on the current regulation signal.

Optionally, the digital signal for the voltage regulation is a code value S<7:0> for the voltage regulation. When the output voltage V_O needs to be regulated from V_O1 to V_O2, the voltage regulation circuit 201 generates the code value S<7:0> for the voltage regulation based on a requirement. After passing through the digital-to-analog conversion circuit (DAC) 2011, the code value S<7:0> for the voltage regulation is converted to the first reference voltage signal which may be denoted as V_REF_DAC. V_REF_DAC is transmitted to the voltage-to-current conversion circuit 2012 and is converted to the current regulation signal. The current regulation signal may be used to inject a current to or draw a current from the feedback voltage node, and it needs to be determined based on the code value S<7:0> for the voltage regulation whether to inject a current or draw a current.

Optionally, as shown in FIG. 4, the feedback network 204 includes a first feedback resistor R_f1 and a second feedback resistor R_f2, and an output point of the feedback network 204 is located between the first feedback resistor R_f1 and the second feedback resistor R_f2.

The output voltage V_O and the current I of the feedback voltage node satisfy the following relationship.

V _O =V _REF*(1+R_f1/R_f2)+I*R_f1  formula (1), where

V_REF is a second reference voltage signal obtained by the control circuit 202.

As shown in FIG. 5, in a possible implementation, specific structures of the control circuit 202 and the power stage circuit 203 are described as follows.

The control circuit 202 includes an error amplifier 2021 and a comparator 2022. The power stage circuit 203 includes a driver stage BUF 2031, an upper power transistor 2032, and a lower power transistor 2033.

The error amplifier 2021 outputs a V_EAOUT signal after performing error amplification on the feedback voltage V_FB that is output by the feedback network 204 and the second reference voltage signal V_REF. After the V_EAOUT signal and a triangular wave signal V_SAW1 pass through the comparator 2022, a duty cycle square wave signal is output, and the duty cycle square wave signal is used to switch on or off the power stage circuit 203. The voltage regulation circuit 201 injects a current to or draws a current from the feedback voltage node using the current regulation signal, to regulate a value of the feedback voltage V_FB.

The power stage circuit 203 switches on or off the power transistors based on the duty cycle square wave signal that is output by the comparator 2022, and further outputs energy of a PVDD as the output voltage V_O.

A Kirchhoff equation of the feedback voltage V_FB node is as follows.

$\begin{array}{cc}\frac{V_{\mathrm{FB}}}{R_{f2}}+I-\frac{V_O-V_{\mathrm{FB}}}{R_{f1}}=0& \mathrm{formula}\left(2\right)\end{array}$

V_FB and V_REF of two input ends of the error amplifier 2021 have the following relationship.

V _FB =V _REF  formula (3)

The formula (1) may be deduced using the formula (2) and the formula (3).

When a direction of the current I is flowing into the feedback voltage V_FB node, a value of I is positive. When a direction of the current I is flowing out of the feedback voltage V_FB node, a value of I is negative, that is, a current whose magnitude is an absolute value of I is drawn from the feedback voltage V_FB node. In the formula (1), the value of V_O equals V_REF*(1+R_f1/R_f2) minus a product of the absolute value of I and R_f1.

The voltage regulation circuit 201 includes a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

Based on a same inventive concept as that of the output voltage regulation apparatus shown in FIG. 2, an embodiment of this application further provides an output voltage regulation method. On a basis of maintaining a reference voltage V_REF in a control circuit unchanged, a current of a feedback voltage V_FB node in the control circuit is changed, to rapidly regulate an output voltage V_O. In this way, not only rapid regulation of the output voltage can be implemented, but also an overshoot, an undershoot, or a glitch that occurs in an output voltage regulation process can be inhibited, and a time of regulating the output voltage to a regulated voltage is effectively shortened.

The specific method is as follows. An output voltage V_O of a power stage circuit is acquired and a feedback voltage is output to a feedback voltage node of the control circuit using a feedback network, a current I of the feedback voltage node is regulated using a voltage regulation circuit, to change the output feedback voltage, and the output voltage V_O of the power stage circuit is regulated based on the current I of the feedback voltage node using the control circuit. The output voltage V_O is rapidly regulated by regulating the current of the feedback node, providing an excellent inhibition effect on an overshoot, an undershoot, or a glitch of the output voltage such that a voltage regulation effect is more rapidly and stably achieved.

Optionally, the regulating a current I of the feedback voltage node using a voltage regulation circuit is receiving a digital signal used to represent voltage regulation, generating a first reference voltage signal based on the digital signal, converting the first reference voltage signal to a current regulation signal, and transmitting the current regulation signal to the feedback voltage node.

Optionally, the regulating a current I of the feedback voltage node using a voltage regulation circuit is injecting a current to the feedback voltage node or receiving a current flowing out of the feedback voltage node, based on the current regulation signal.

Optionally, the output voltage V_O and the current I of the feedback voltage node satisfy the following relationship, V_O=V_REF*(1+R_f1/R_f2)+I*R_f1, where V_REF is a second reference voltage signal obtained by the control circuit, R_f1 is a first feedback resistor in the feedback network, R_f2 is a second feedback resistor in the feedback network, and an output point of the feedback network is located between the first feedback resistor and the second feedback resistor.

Persons skilled in the art should understand that the embodiments of this application may be provided as a method, a system, or a computer program product. Therefore, this application may use a form of hardware only embodiments, software only embodiments, or embodiments with a combination of software and hardware. Moreover, this application may use a form of a computer program product that is implemented on one or more computer-usable storage media (including but not limited to a disk memory, a compact disc read only memory (CD-ROM), an optical memory, and the like) that include computer usable program code.

This application is described with reference to the flowcharts and/or block diagrams of the method, the device or system, and the computer program product according to the embodiments of this application. It should be understood that computer program instructions may be used to implement each process and/or each block in the flowcharts and/or the block diagrams and a combination of a process and/or a block in the flowcharts and/or the block diagrams. These computer program instructions may be provided for a general-purpose computer, a special-purpose computer, an embedded processor, or a processor of another programmable data processing device to generate a machine such that the instructions executed by a computer or a processor of another programmable data processing device generate an apparatus for implementing a specific function in one or more processes in the flowcharts and/or in one or more blocks in the block diagrams.

These computer program instructions may alternatively be stored in a computer-readable memory that can instruct the computer or another programmable data processing device to work in a specific manner such that the instructions stored in the computer-readable memory generate an artifact that includes an instruction apparatus. The instruction apparatus implements a specific function in one or more processes in the flowcharts and/or in one or more blocks in the block diagrams.

These computer program instructions may alternatively be loaded onto a computer or another programmable data processing device such that a series of operations and steps are performed on the computer or the another programmable device, thereby generating computer-implemented processing. Therefore, the instructions executed on the computer or the another programmable device provide steps for implementing a specific function in one or more processes in the flowcharts and/or in one or more blocks in the block diagrams.

Although some preferred embodiments of this application have been described, persons skilled in the art can make changes and modifications to these embodiments once they learn the basic inventive concept. Therefore, the following claims are intended to be construed as to cover the preferred embodiments and all changes and modifications falling within the scope of this application.

Obviously, persons skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. This application is intended to cover these modifications and variations provided that they fall within the scope of protection defined by the following claims and their equivalent technologies.

Claims

1. An output voltage regulation apparatus, comprising: a control circuit;a power stage circuit;a filtering network;a feedback network, wherein an input end of the feedback network is coupled to an output end of the filtering network, wherein the input end of the feedback network is configured to acquire a regulated output voltage of the filtering network, wherein an output end of the feedback network is coupled to a feedback voltage node of the control circuit, and wherein the output end of the feedback network is configured to output a feedback voltage to the feedback voltage node of the control circuit; anda voltage regulation circuit, wherein an output end of the voltage regulation circuit is coupled between the output end of the feedback network and the feedback voltage node of the control circuit, wherein the voltage regulation circuit is configured to regulate the feedback voltage,wherein the control circuit is configured to: receive the feedback voltage; andswitch on or off power transistors in the power stage circuit, andwherein the filtering network is configured to perform filtering on an output voltage of the power stage circuit to obtain the regulated output voltage.

2. The output voltage regulation apparatus according to claim 1, wherein the output end of the voltage regulation circuit is configured to output a current regulation signal to regulate the feedback voltage.

3. The output voltage regulation apparatus according to claim 2, wherein the current regulation signal is used to inject a current to the feedback voltage node or receive a current flowing out of the feedback voltage node to regulate the feedback voltage.

4. The output voltage regulation apparatus according to claim 2, wherein the voltage regulation circuit comprises a digital-to-analog conversion circuit and a voltage-to-current conversion circuit; wherein the digital-to-analog conversion circuit is configured to: receive a digital signal used to represent voltage regulation;generate a first reference voltage signal based on the digital signal; andtransmit the first reference voltage signal to the voltage-to-current conversion circuit, andwherein the voltage-to-current conversion circuit is configured to: receive the first reference voltage signal;convert the first reference voltage signal to the current regulation signal; andtransmit the current regulation signal to the feedback voltage node.

5. The output voltage regulation apparatus according to claim 1, wherein the feedback network comprises a first feedback resistor and a second feedback resistor, and wherein an output point of the feedback network is located between the first feedback resistor and the second feedback resistor.

6. The output voltage regulation apparatus according to claim 1, wherein the control circuit is configured to output a duty cycle square wave signal to switch on or off the power transistors in the power stage circuit.

7. The output voltage regulation apparatus according to claim 6, wherein the control circuit comprises: an error amplifier configured to perform error amplification on the feedback voltage and a second reference voltage signal to output an output signal; anda comparator configured to compare the output signal and a triangular wave signal to output the duty cycle square wave signal.

8. The output voltage regulation apparatus according to claim 6, wherein the power stage circuit comprises an upper power transistor and a lower power transistor, and wherein the duty cycle square wave signal is used to switch on or off the upper power transistor and the lower power transistor.

9. The output voltage regulation apparatus according to claim 8, wherein the power stage circuit further comprises a driver stage, and wherein the driver stage is coupled to the upper power transistor and the lower power transistor and configured to receive the duty cycle square wave signal.

10. The output voltage regulation apparatus according to claim 1, wherein the filtering network comprises an inductor and a capacitor.

11. An output voltage regulation method, comprising: acquiring a regulated output voltage of a filtering network;outputting a feedback voltage to a feedback voltage node of a control circuit using a feedback network;regulating the feedback voltage using a voltage regulation circuit;switching on or off power transistors in a power stage circuit using the control circuit; andperforming filtering on an output voltage of the power stage circuit using the filtering network to obtain the regulated output voltage.

12. The method according to claim 11, wherein regulating the feedback voltage comprises: outputting a current regulation signal to regulate the feedback voltage.

13. The method according to claim 12, wherein the current regulation signal is used to inject a current to the feedback voltage node or receive a current flowing out of the feedback voltage node to regulate the feedback voltage.

14. The method according to claim 12, wherein outputting the current regulation signal to regulate the feedback voltage comprises: receiving a digital signal representing voltage regulation;generating a first reference voltage signal based on the digital signal using a digital-to-analog conversion circuit;converting the first reference voltage signal to the current regulation signal; andtransmitting the current regulation signal to the feedback voltage node using a voltage-to-current conversion circuit.

15. The method according to claim 11, wherein the feedback network comprises a first feedback resistor and a second feedback resistor, and wherein an output point of the feedback network is located between the first feedback resistor and the second feedback resistor.

16. The method according to claim 11, wherein switching on or off the power transistors in the power stage circuit comprises outputting a duty cycle square wave signal to switch on or off the power transistors in the power stage circuit.

17. The method according to claim 16, wherein outputting the duty cycle square wave signal comprises: performing error amplification on the feedback voltage and a second reference voltage signal to output an output signal; andcomparing the output signal and a triangular wave signal to output the duty cycle square wave signal.

18. The method according to claim 16, wherein the power stage circuit comprises an upper power transistor and a lower power transistor, and wherein the duty cycle square wave signal is used to switch on or off the upper power transistor and the lower power transistor.

19. The method according to claim 18, wherein the power stage circuit further comprises a driver stage which is coupled to the upper power transistor and the lower power transistor, and wherein switching on or off the power transistors in the power stage circuit further comprises receiving the duty cycle square wave signal using the driver stage.

20. The method according to claim 11, wherein the filtering network comprises an inductor and a capacitor.