Patent Application
20240213930
This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2022-0177478 filed on Dec. 16, 2022, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.
This disclosure relates to an overcurrent protection circuit and a power amplifier including an overcurrent protection circuit.
A wireless communication system applies various digital modulation/demodulation methods in accordance with evolution of communication standards. The existing code division multiple access (CDMA) communication system employs a quadrature phase shift keying (QPSK) scheme and a wireless LAN according to the communication standard of IEEE employs an orthogonal frequency division multiplexing (OFDM) scheme. Furthermore, long term evolution (LTE) and LTE Advanced (LTE+), which are recent 3GPP standard specifications, employ QPSK, QAM (Quadrature Amplitude Modulation), and OFDM schemes.
In order to increase a transmission distance, a transmitting device used for a wireless communication system includes a power amplifier that amplifies a radio-frequency (RF) signal. The power amplifier may be designed to most efficiently operate at a rated voltage. When a load impedance of the power amplifier is changed, an overcurrent may flow, and thus there may be a situation in which the power amplifier transmits a power beyond its physical limitations. Accordingly, it is necessary to design a power amplifier that stably operates even in a situation in which an output current is applied over the design limitation.
A technique of limiting an output current of the power amplifier is referred to as overcurrent protection (OCP). As a method of implementing the OCP, there is a feedback method. According to the feedback method, the output current is sensed and a bias current is reduced in response to the sensed output current to limit the output current. However, according to the feedback method, the power amplifier may be broken by a delay time of a feedback loop.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the disclosure of this application, and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.
This Summary is provided to introduce a selection of concepts in simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In one general aspect, an overcurrent protection circuit includes a variable voltage source configured to generate a first voltage that varies in response to a variable current; an amplifier including a first input terminal to which the first voltage is applied; and a limit current source connected to a second input terminal of the amplifier and configured to generate a limit current corresponding to the first voltage.
The variable voltage source may include a first transistor and a second transistor connected to each other in a current mirror structure; a variable current source connected between a first terminal of the first transistor and a ground and configured to generate the variable current; and a first resistor connected between a first terminal of the second transistor and the ground.
A voltage of the first terminal of the second transistor may be the first voltage.
The limit current source may be further connected to an output terminal of the amplifier, and a voltage of the output terminal of the amplifier may be a second voltage that varies in response to the variable current.
The limit current source may include a first transistor including a control terminal to which the second voltage is applied, and a first terminal connected to the second input terminal of the amplifier; a first resistor connected between the first terminal of the first transistor and a ground; and a second transistor including a control terminal to which the second voltage is applied, and a first terminal that outputs the limit current.
The limit current source may include a first transistor including a control terminal to which the second voltage is applied; a second transistor including a first terminal connected to a first terminal of the first transistor, and a second terminal connected to the second input terminal of the amplifier; a first resistor connected between the second terminal of the second transistor and a ground; a third transistor including a control terminal to which the second voltage is applied; and a fourth transistor including a first terminal connected to a first terminal of the third transistor, a control terminal connected to a control terminal of the second transistor, and a second terminal that outputs the limit current.
The limit current may vary in response to the first voltage and the second voltage.
The limit current may be generated to be supplied to a bias circuit configured to bias a power transistor.
The amplifier may be an operational amplifier, the first input terminal of the amplifier may be an inverting terminal of the operational amplifier, and the second input terminal of the amplifier may be a non-inverting terminal of the operational amplifier.
In another general aspect, a power amplifier includes a power transistor configured to amplify an input radio-frequency (RF) signal; a bias circuit configured to supply a bias current to the power transistor; and an overcurrent protection circuit configured to supply a limit current to the bias circuit to prevent an overcurrent from flowing in the power transistor, wherein the overcurrent protection circuit includes a variable voltage source configured to generate a first voltage that varies in response to a variable current; an amplifier including a first input terminal to which the first voltage is applied; and a limit current source connected to a second input terminal of the amplifier and configured to generate the limit current so that the limit current corresponds to the first voltage.
The variable voltage source may include a variable current source configured to generate the variable current; and a current mirror configured to generate a first current based on the variable current, generate the first voltage based on the first current so that the first voltage varies in response to the variable current.
The limit current source may be further connected to an output terminal of the amplifier, and a voltage of the output terminal of the amplifier may be a second voltage that varies in response to the variable current.
The limit current source may include a first transistor including a control terminal to which the second voltage is applied, and a first terminal connected to the second input terminal of the amplifier; a first resistor connected between the first terminal of the first transistor and a ground; and a second transistor including a control terminal to which the second voltage is applied, and a first terminal that outputs the limit current.
The limit current source may include a first transistor including a control terminal to which the second voltage is applied; a second transistor including a first terminal connected to a first terminal of the first transistor, and a second terminal connected to the second input terminal of the amplifier; a first resistor connected between the second terminal of the second transistor and a ground; a third transistor including a control terminal to which the second voltage is applied; and a fourth transistor including a first terminal connected to a first terminal of the third transistor, a control terminal connected to a control terminal of the second transistor, and a second terminal that outputs the limit current.
The limit current may vary in response to the first voltage and the second voltage.
In another general aspect, an overcurrent protection circuit includes a variable voltage source configured to generate a first voltage that varies in response to a variable current; an amplifier including a first input terminal to which the first voltage is applied; and a limit current source configured to generate a limit current corresponding to the first voltage, and apply a voltage corresponding to the limit current to a second input terminal of the amplifier.
The variable voltage source may include a first transistor and a second transistor connected to each other in a current mirror structure; a variable current source connected between a first terminal of the first transistor and a ground and configured to generate the variable current; and a first resistor connected between a first terminal of the second transistor and the ground.
A voltage of the first terminal of the second transistor may be the first voltage.
The limit current source may include a first transistor including a control terminal connected to an output terminal of the amplifier, and a first terminal providing the voltage corresponding to the limit current to the second input terminal of the amplifier; a first resistor connected between the first terminal of the first transistor and a ground; and a second transistor including a control terminal connected to the output terminal of the amplifier, and a first terminal that outputs the limit current.
The limit current source may include a first transistor including a control terminal connected to an output terminal of the amplifier; a second transistor including a first terminal connected to a first terminal of the first transistor, and a second terminal providing the voltage corresponding to the limit current to the second input terminal of the amplifier; a first resistor connected between the second terminal of the second transistor and a ground; a third transistor including a control terminal connected to the output terminal of the amplifier; and a fourth transistor including a first terminal connected to a first terminal of the third transistor, a control terminal connected to a control terminal of the second transistor, and a second terminal that outputs the limit current.
Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.
Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness.
The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.
Throughout the specification, when an element, such as a layer, region, or substrate, is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there can be no other elements intervening therebetween.
As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items.
Although terms such as “first,” “second,” and “third” may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.
Spatially relative terms such as “above,” “upper,” “below,” and “lower” may be used herein for ease of description to describe one element's relationship to another element as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “above” or “upper” relative to another element will then be “below” or “lower” relative to the other element. Thus, the term “above” encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated by 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.
The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “includes,” and “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.
Through the specification, the RF signal may have a format according to any known wireless and wired protocols including Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, and 5G or higher, but is not limited thereto.
As illustrated in
The input matching network 100 is connected to an input terminal (a base B) of the power transistor 200 and performs impedance matching between an input RF (radio-frequency) signal RFIN and the power transistor 200. The output matching network 300 is connected to an output terminal (a collector C) of the power transistor 200 and performs impedance matching between an output RF signal RFOUT and a next stage (that is, a next stage of the power amplifier). The input matching network 100 and the output matching network 300 may be implemented by a combination of one or more components selected from resistors, inductors, and capacitors.
The power transistor 200 amplifies the power of the RF signal RFIN input to the input terminal (the base B) and then outputs the amplified power to the output terminal (the collector C). That is, an RF signal RFIN to be amplified is input to the base B of the power transistor 200, and the collector C of the power transistor 200 outputs an amplified RF signal RFOUT. An emitter E of the power transistor 200 may be connected to a ground, and even though it is not illustrated in
In an abnormal state, in some cases, the current ICC excessively increases. Examples of an abnormal state may be a case when a load impedance of the power transistor 200 significantly fluctuates, and a case when a battery providing the power source voltage VCC is unstable. When the current ICC excessively increases, the power transistor 200 may be damaged or destroyed. Hereinafter, when the current ICC excessively increases, it is referred to as an “abnormal state,” and when the current ICC does not excessively increase, it is referred to as a “normal state”. In order to prevent the abnormal state, the overcurrent protection circuit 600 according to one embodiment supplies a limit current ILIM to the bias circuit 400 to protect the power transistor 200 from an overcurrent.
The power transistor 200 may be implemented by various transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). Furthermore, in
A coupling capacitor CC is connected to the input terminal (the base B) of the power transistor 200. The coupling capacitor CC performs a function of removing (blocking) a direct current (DC) component from the RF signal RFIN.
The bias circuit 400 is supplied with a reference current IREF from the reference current generating circuit 500, and is supplied with a limit current ILIM from the overcurrent protection circuit 600. The bias circuit 400 generates a bias current IBIAS needed by the power transistor 200 using the reference current IREF and the limit current ILIM. The bias current IBIAS is supplied to the input terminal (the base B) of the power transistor 200 and a bias level (a bias point) of the power transistor 200 is set by the bias current IBIAS. According to one embodiment, a maximum value of the bias current IBIAS is limited by the limit current ILIM, as will be described in more detail below.
The reference current generating circuit 500 generates a reference current IREF and supplies the reference current to the bias circuit 400. As one example, the reference current generating circuit 500 generates different reference currents IREF according to a power mode of the power amplifier 1000. When the power mode is a high power mode, the reference current generating circuit 500 generates a reference current IREF HPM. When the power mode is a low power mode, the reference current generating circuit 500 generates a reference current IREF_LPM. A magnitude of the reference current IREF HPM may be larger than a magnitude of the reference current IREF_LPM. In any event, the method of generating the reference current IREF by the reference current generating circuit 500 is known to those skilled in the art, and accordingly a detailed description thereof will be omitted.
The overcurrent protection circuit 600 according to one embodiment generates the limit current ILIM and supplies the generated limit current ILIM to the bias circuit 400. As one example, the overcurrent protection circuit 600 may generate different limit currents ILIM depending on the normal state or the abnormal state of the power amplifier 1000. In the normal state, the overcurrent protection circuit 600 generates a normal limit current ILIM_NS in accordance with the bias circuit 400. That is, in the normal state, the overcurrent protection circuit 600 generates a normal limit current ILIM_NS that is proportional to a need of the bias circuit 400. Furthermore, in the abnormal state, the overcurrent protection circuit 600 generates a limit current ILIM that does not exceed an abnormal limit current ILIM_ABS. That is, in the abnormal state, the overcurrent protection circuit 600 may generate a limit current ILIM that does not exceed the abnormal limit current ILIM_ABS regardless of the need of the bias circuit 400. In other words, the limit current ILIM does not exceed the abnormal limit current ILIM_ABS. Accordingly, a maximum range of the bias current IBIAS of the bias circuit 400 is limited and the power amplifier 1000 is protected from an overcurrent.
As illustrated in
The transistors T1 to T3 may be implemented by various transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). Furthermore, in
A base and a collector of the transistor T1 are connected to each other in a diode-connected structure, and the collector of the transistor T1 is connected to a current source IREF via the resistor R1. The transistor T1 sinks a current 12 from the current source IREF. The reference current generating circuit 500 supplies the reference current IREF to the bias circuit 400 so that in
A base and a collector of the transistor T2 are connected to each other in a diode-connected structure, and the collector of the transistor T2 is connected to an emitter of the transistor T1. An emitter of the transistor T2 is connected to the ground.
A collector of the transistor T3 is connected to a current sourceILIM and a base of the transistor T3 is connected to the base of the transistor T1. Furthermore, an emitter of the transistor T3 is connected to the input terminal (the base B) of the power transistor 200 and supplies the bias current IBIAS to the power transistor 200. The overcurrent protection circuit 600 supplies the limit current ILIM to the bias circuit 400 so that in
The reference current IREF is divided into a current 11 and the current 12, and the current 11 is input to the base of the transistor T3. Accordingly, the bias current IBIAS is equal to a sum of the limit current ILIM and the current 11. The bias current IBIAS is the base current of the power transistor 200, so that the bias current IBIAS and the current ICC have a relationship defined by the following Equation 1.
In Equation 1, β is a common-emitter current gain of the power transistor 200.
As described above, in the abnormal state, the value of the current ICC increases. Referring to Equation 1, as the value of the current ICC increases, a value of the bias current IBIAS also increases. Therefore, the increase of the limit current ILIM is needed. In this case, the overcurrent protection circuit 600 according to one embodiment is designed so that the limit current ILIM does not exceed the abnormal limit current ILIM_ABS. The overcurrent protection circuit 600 that performs the above-described operation will be described in more detail below.
As illustrated in
The variable voltage source 610 generates and outputs a voltage VA that fluctuates in response to an internal variable current source IVAR (see
The amplifier 620 receives the voltage VA output from the variable voltage source 610 through an inverting terminal (−). That is, the voltage VA is applied to the inverting terminal (−) of the amplifier 620. A voltage VB is output from the limit current source 630 and is applied to a non-inverting terminal (+) of the amplifier 620. The amplifier 620 outputs a voltage VOUT from an output terminal of the amplifier 620, and the voltage VOUT is applied to the limit current source 630. The amplifier 620 may be an operational amplifier (OP AMP). The voltage VB may be set to be equal to the voltage VA by the operation of the amplifier 620. Furthermore, by the operation of the amplifier 620, the voltage VOUT may be set so that the voltage VA and the voltage VB become the same voltage. The voltage VA is variable so that the voltage VOUT is also variable, i.e., it fluctuates.
The limit current source 630 generates the limit current ILIM in response to the voltage VOUT applied from the amplifier 620 and the voltage VB applied to the amplifier 620. The limit current ILIM generated in the limit current source 630 is supplied (applied) to the bias circuit 400.
As illustrated in
In
The source of the transistor M1 is connected to a power source voltage VDD and a gate (control terminal) and a drain of the transistor M1 are connected to each other. One end of the variable current source IVAR is connected to the drain of the transistor M1 and the other end of the variable current source IVAR is connected to the ground. A gate (control terminal) of the transistor M2 is connected to the gate (control terminal) of the transistor M1, and a source of the transistor M2 is connected to the power source voltage VDD. The resistor R3 is connected between a drain of the transistor M2 and the ground. The transistor M1 and the transistor M2 are connected to each other in a current mirror structure. In
The variable current source IVAR according to one embodiment generates and outputs a variable current IVAR. As an example, the variable current source IVAR may generate a variable current IVAR having different current values depending on a power mode of the power amplifier 1000. When the power mode is a high power mode, the variable current source IVAR may generate a current IVAR_HPM. When the power mode is a low power mode, the variable current source IVAR may generate a current IVAR_LPM. A magnitude of the current IVAR_HPM may be larger than a magnitude of the current IVAR_LPM.
Since the variable current source IVAR has a variable current value, a voltage VA value is also variable (fluctuates). The transistor M1 and the transistor M2 have a current mirror structure so that a drain current ID2 of the transistor M2 is proportional to a size ratio of the transistor M1 and the transistor M2 (a ratio of a channel width and a channel length). That is, the drain current ID2 of the transistor M2 has a relationship defined by the following Equation 2.
I
D2
=K1×IVAR (2)
In Equation 2, K1 refers to a size ratio of the transistor M1 and the transistor M2. As an example, when a size of the transistor M1 is equal to a size of the transistor M2, K1 is 1. When K is 1, the drain current ID2 of the transistor M2 is equal to the current IVAR generated by the variable current source IVAR.
The voltage VA is defined by the following Equation 3.
V
A
=R3×ID2=R3·K1·IVAR (3)
Referring to Equation 3, the voltage VA may vary (fluctuate) according to a value of the variable current IVAR. The voltage VB is set to be equal to the voltage VA by the amplifier 620. Furthermore, by the operation of the amplifier 620, the voltage VOUT may be set so that the voltage VA and the voltage VB become the same voltage. Accordingly, the voltage VOUT may also vary (fluctuate) according to the value of the variable current IVAR.
Referring to
The voltage VB in Equation 4 is equal to the voltage VA, so that the voltage VB in Equation 4 may be replaced by Equation 3 for the voltage VA.
In
I
LIM
=K2×ID3 (5)
In Equation 5, K2 refers to a size ratio of the transistor M3 and the transistor M4. As one example, when the size of the transistor M4 is 20 times larger than the size of the transistor M3, K2 is 20.
In Equation 5, instead of the drain current ID3 of the transistor M3, when Equation 4 is applied, the limit current ILIM is defined by the following Equation 6.
In Equation 6, values of K1 and K2 and values of resistances R3 and R4 may be set in advance according to a design of the power amplifier 1000. The limit current ILIM may have different values depending on the value of the variable current IVAR. As described above, the variable current IVAR has different values depending on the power mode of the power amplifier 1000 so that value of the limit current ILIM also has different values depending on the power mode.
Referring to Equation 6, the value of the limit current ILIM is affected by the values of the resistances R3 and R4. In the overcurrent protection circuit 600 according to one embodiment, the resistors R3 and R3 are manufactured by the same process so that the limit current ILIM may be less affected by deviations in the values of the resistors.
In the limit current source 630, the transistor M3 may be designed to operate in the saturation region at all times. In contrast, the transistor M4 may operate in different modes depending on a drain voltage VC of the transistor M4. The drain voltage VC of the transistor M4 may be a collector voltage of the transistor T3 in
As one example, in the normal state, the transistor M4 operates in a triode region, and in the abnormal state, the transistor M4 operates in the saturation region. When the transistor M4 operates in the triode region, the value of the limit current ILIM may vary in response to the drain voltage VC of the transistor M4. When the transistor M4 operates in the saturation region, the value of the limit current ILIM has a value defined by Equation 6. In the abnormal state, the value of the current ICC increases. In this case, the transistor M4 of the overcurrent protection circuit 600 operates in the saturation region and the value of the limit current ILIM may have a value defined by Equation 6. That is, the above described abnormal limit current ILIM_ABS may be designed to have a value defined by Equation 6. By doing this, the overcurrent protection circuit 600 may prevent the damage due to the overcurrent of the power transistor 200.
According to Equation 3, the voltage VOUT, which is the output voltage of the output terminal of the amplifier 620, may vary (fluctuate) according to a value of the variable current source IVAR. The voltage VOUT is a gate (control terminal) voltage of the transistor M4 so that a headroom of the transistor M4 may expand. That is, in the overcurrent protection circuit 600 according to one embodiment, the gate (control terminal) voltage of the transistor M4 is not fixed, but may vary so that the headroom of the transistor M4 may expand. The headroom refers to a range of a drain-source voltage (Vds) of a transistor to allow the transistor to operate in the saturation region. This will be described below with reference to
In
When the gate (control terminal) voltage VG4 of the transistor M4 is 1 V, if the voltage VC is equal to or lower than 2 V, the transistor M4 operates in the saturation region. That is, when the voltage VC has a range of 0 V to 2 V, the transistor M4 operates in the saturation region.
When the gate (control terminal) voltage VG4 of the transistor M4 is 2 V, if the voltage VC is equal to or lower than 3 V, the transistor M4 operates in the saturation region. That is, when the voltage VC has a range of 0 V to 3 V, the transistor M4 operates in the saturation region. In other words, when the gate (control terminal) voltage VG4 increases from 1 V to 2 V, a range of the drain-source voltage at which the transistor M4 operates in the saturation region expands. Accordingly, in one embodiment, the headroom of the transistor M4 expands.
Referring to
As illustrated in
A source of the transistor M5 is connected to the drain of the transistor M3 so that a drain of the transistor M5 may be connected to the non-inverting terminal (+) of the amplifier 620. A source of the transistor M6 is connected to the drain of the transistor M4 and a limit current ILIM is output from the drain of the transistor M6. A gate (control terminal) of the transistor M5 and a gate (control terminal) of the transistor M6 are connected to each other, and a power source voltage VDD1 is applied to the gate (control terminal) of the transistor M5 and the gate (control terminal) of the transistor M6 as a bias voltage.
That is, the transistor M5 is connected to the transistor M3 in a cascode structure, and the transistor M6 is connected to the transistor M4 in a cascode structure. Due to this cascode structure, a channel resistance of the limit current source 630′ of
While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and are not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0177478 | Dec 2022 | KR | national |
