Patent Application
20240275160
The disclosure herein relates to an overcurrent protection circuit and a power supply device.
Conventionally, overcurrent protection circuits have widely been in practical use as one of abnormality protection means.
An example of conventional technologies related to the above is disclosed in Patent Document 1 identified below.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2006-115646
The output transistor M1 corresponds to a first output transistor that is connected between an input terminal for the input voltage Vin and an output terminal for the output voltage Vout so as to be driven by a gate drive signal G1.
A source of the output transistor M1 is connected to the input terminal for the input voltage Vin. A drain of the output transistor M1 is connected to the output terminal for the output voltage Vout. A gate of the output transistor M1 is connected to an application terminal for the gate drive signal G1 (=corresponding to a first drive signal). An on-resistance Ron1 of the output transistor M1 is variably controlled in accordance with the gate drive signal G1.
The higher the gate drive signal G1 is, the lower a gate-source voltage Vgs1 of the output transistor M1 becomes. Thus, the on-resistance Ron1 of the output transistor M1 increases, and thus an output current Io1 flowing through the output transistor M1 (and thus an output current Iout flowing through the load 2) decreases. On the other hand, the lower the gate drive signal G1 is, the higher the gate-source voltage Vgs1 of the output transistor M1 becomes. Thus, the on-resistance Ron1 of the output transistor M1 decreases, and thus the output current Io1 flowing through the output transistor M1 increases.
The resistors R1 and R2 are connected in series between the output terminal for the output voltage Vout and a ground terminal. The resistors R1 and R2 function as a voltage dividing circuit that outputs from a connection node therebetween a feedback voltage Vfb (={R2/(R1+R2)}×Vout) in accordance with the output voltage Vout. Note that, in a case where the output voltage Vout stays within an input dynamic range of the error amplifier A1, the resistors R1 and R2 may be omitted such that the output voltage Vout is directly fed to the error amplifier A1.
The capacitor C1 is connected in series between the output terminal for the output voltage Vout and the ground terminal. The capacitor C1 functions as smoothing means for the output voltage Vout.
The reference voltage generation circuit REF generates a predetermined reference voltage Vref from the input voltage Vin. Preferably usable as the reference voltage generation circuit REF is, for example, a bandgap reference voltage supply or the like having flat input voltage dependence and temperature dependence.
The error amplifier A1 generates an error signal between the feedback voltage Vfb fed to a non-inverting input terminal (+) thereof and the reference voltage Vref fed to an inverting input terminal (−) thereof, and outputs the error signal as the gate drive signal G1. Thus, the gate drive signal G1 lowers when the feedback voltage Vfb is lower than the reference voltage Vref, and rises when the feedback voltage Vfb is higher than the reference voltage Vref. Note that the error amplifier A1 can be understood as an example of an output feedback circuit configured to accept an input of the output voltage Vout or the feedback voltage Vfb in accordance with the output voltage Vout to generate the gate drive signal G1 of the output transistor M1.
The overcurrent protection circuit OCP restricts the output current Io1 flowing through the output transistor M1 (and thus the output current Iout flowing through the load 2) to values equal to or less than a predetermined upper limit value.
Note that, among the components described above, the output transistor M1, the reference voltage generation circuit REF, the error amplifier A1, the resistors R1 and R2, and the overcurrent protection circuit OCP may be integrated into a semiconductor integrated circuit device (what is called a power supply control IC). However, the output transistor M1 and the resistors R1 and R2 may be externally attached to the semiconductor integrated circuit device.
Next, with reference to
The mirror transistor M11 corresponds to a first mirror transistor that is driven by the gate drive signal G1 common to the output transistor M1 so as to pass a mirror current Im1 that behaves similarly to the output current Io1 in terms of increase and decrease.
A source of the mirror transistor M11 is connected via the sense resistor Rs to the input terminal for the input voltage Vin. A drain of the mirror transistor M11 is connected to the output terminal for the output voltage Vout. A gate of the mirror transistor M11 is connected to the application terminal for the gate drive signal G1. An on-resistance Ron11 of the mirror transistor M11 is variably controlled in accordance with the gate drive signal G1.
For example, the higher the gate drive signal G1 is, the lower a gate-source voltage Vgs11 of the mirror transistor M11 becomes. Thus, the on-resistance Ron11 of the mirror transistor M11 increases, and thus the mirror current Im1 (=corresponding to a first mirror current) flowing through the mirror transistor M11 decreases. On the other hand, the lower the gate drive signal G1 is, the higher the gate-source voltage Vgs11 of the mirror transistor M11 becomes. Thus, the on-resistance Ron11 of the mirror transistor M11 decreases, and thus the mirror current Im1 flowing through the mirror transistor M11 increases.
The mirror transistor M11 is smaller in size than the output transistor M1. Thus, the mirror current Im1 is smaller than the output current Io1.
The sense resistor Rs functions as a current/voltage conversion element that converts a sense current Is (=the mirror current Im1) flowing therethrough into a sense voltage Vs (=Is×Rs). A first end (=a high-potential end) of the sense resistor Rs is connected to a non-inverting input terminal (+) of the operational amplifier A10. A second end (=a low-potential end) of the sense resistor Rs is connected to an inverting input terminal (−) of the operational amplifier A10.
The operational amplifier A10 regulates the gate drive signal G1 in accordance with a difference between the sense voltage Vs, which appears across the sense resistor Rs, and an internal offset voltage Vofs (=corresponding to an overcurrent detection threshold) of the operational amplifier A10.
For example, when the sense voltage Vs is lower than the internal offset voltage Vofs, the operational amplifier A10 enters an output high-impedance state. In this state, no restriction is put on the gate drive signal G1. Thus, the on-resistance Ron1 of the output transistor M1 is not lowered, or the output current Io1 is not restricted.
On the other hand, when the sense voltage Vs is higher than the internal offset voltage Vofs, the operational amplifier A10 enters a state where the operational amplifier A10 raises the gate drive signal G1 in accordance with the difference between them (=Vs−Vofs). When the gate drive signal G1 is raised, the on-resistance Ron1 of the output transistor M1 decreases, and thus the output current Io1 decreases.
Further, when the gate drive signal G1 is raised, the on-resistance Ron11 of the mirror transistor M11 lowers, and thus the mirror current Im1 (and thus the sense current Is) decreases. Thus, the difference between the sense voltage Vs and the internal offset voltage Vofs decreases, and a raising amount by which the operational amplifier A10 raises the gate drive signal G1 decreases.
As a result of the series of gate drive control described above, the sense voltage Vs and the internal offset voltage Vofs eventually reach an equilibrium state where they are equal to each other. This state is the very state where the sense current Is (and thus the output current Io1) is restricted to values equal to or less than the predetermined upper limit value.
In this manner, the sense resistor Rs and the operational amplifier A10 function as a current restriction portion that controls the gate drive signal G1 such that the sense current Is is restricted to values equal to or less than the predetermined upper limit value.
However, in the power supply device 1 of the comparative example described above, operation timing of the overcurrent protection circuit OCP (=start-up timing of the overcurrent protection operation) is uniquely determined. This makes it difficult to suppress peak current while improving load variation characteristics.
In what follows, in view of the above discussion, a new embodiment will be proposed that is capable of suppressing peak current while improving load response characteristics.
Note also that, in the following description, a current flowing through the output transistor M1 will be denoted as output current Io1, a current flowing through the output transistor M2 will be denoted as output current Io2, and a current flowing through the load 2 will be denoted as output current Iout (≈Io1+Io2). Further, a current flowing through the mirror transistor M11 will be denoted as mirror current Im1, and a current flowing through the mirror transistor M12 will be denoted as mirror current Im2.
The output transistor M2 corresponds to a second output transistor that is connected between the input terminal for the input voltage Vin and the output terminal for the output voltage Vout so as to be driven by a gate drive signal G2.
A source of the output transistor M2 is connected to the input terminal for the input voltage Vin. A drain of the output transistor M2 is connected to the output terminal for the output voltage Vout. A gate of the output transistor M2 is connected to an application terminal for the gate drive signal G2 (=corresponding to a second drive signal). An on-resistance Ron2 of the output transistor M2 is variably controlled in accordance with the gate drive signal G2.
The higher the gate drive signal G2 is, the lower a gate-source voltage Vgs2 of the output transistor M2 becomes. Accordingly, the on-resistance Ron2 of the output transistor M2 increases, and thus the output current Io2 flowing through the output transistor M2 decreases. On the other hand, the lower the gate drive signal G2 is, the higher the gate-source voltage Vgs2 of the output transistor M2 becomes. Accordingly, the on-resistance Ron2 of the output transistor M2 decreases, and thus the output current Io2 flowing through the output transistor M2 increases.
In this manner, in the power supply device 1 of the present embodiment, the output transistor is divided into a plurality of output transistors (the two output transistors M1 and M2 in the present figure). Moreover, operation timings of the output transistors M1 and M2 are shifted from each other by the resistor R10.
Referring to the present figure, rising and falling of the gate drive signal G2 are delayed compared to those of the gate drive signal G1. Accordingly, the output transistor M2 operates with a delay compared to the output transistor M1. As a result, increase and decrease of the output current Io2 are delayed compared to those of the output current Io1.
In this manner, by creating a difference in transient response characteristics between the output transistors M1 and M2, it is possible to regulate phase characteristics of the power supply device 1 as necessary in accordance with a size ratio between the output transistors M1 and M2.
For example, the output transistor M2 may be designed to be larger in size than the output transistor M1. Specifically, the size ratio between the output transistors M1 and M2 may be 1:2.
The mirror transistor M12 corresponds to a first mirror transistor that is driven by the gate drive signal G2, common to the output transistor M2, so as to pass the mirror current Im2 that behaves similarly to the output current Io2 in terms of increase and decrease.
A source of the mirror transistor M12 is connected to the source of the mirror transistor M11. A drain of the mirror transistor M12 is connected to the output terminal for the output voltage Vout. A gate of the mirror transistor M12 is connected to an application terminal for the gate drive signal G2. An on-resistance Ron12 of the mirror transistor M12 is variably controlled in accordance with the gate drive signal G2.
For example, the higher the gate drive signal G2 is, the lower a gate-source voltage Vgs12 of the mirror transistor M12 becomes. Accordingly, the on-resistance Ron12 of the mirror transistor M12 increases, and thus the mirror current Im2 flowing through the mirror transistor M12 (=corresponding to the second mirror current) decreases. On the other hand, the lower the gate drive signal G2 is, the higher the gate-source voltage Vgs12 of the mirror transistor M12 becomes. Accordingly, the on-resistance Ron12 of the mirror transistor M12 decreases, and thus the mirror current Im2 flowing through the mirror transistor M12 increases.
The mirror transistor M12 is smaller in size than the output transistors M1 and M2. Accordingly, the mirror current Im2 is smaller than the output currents Io1 and Io2.
The resistor R10 is connected between the gates of the output transistor M1 and the mirror transistor M11 (=the application terminal for the gate drive signal G1) and the gates of the output transistor M2 and the mirror transistor M12 (=the application terminal for the gate drive signal G2). A resistance value of the resistor R10 may be set to several tens to several hundreds kΩ (e.g., 250 kΩ).
The overcurrent protection circuit OCP (in particular, an overcurrent restriction unit formed of the sense resistor Rs and the operational amplifier A10) controls the gate drive signal G1 such that the sense current Is (=Im1+Im2) which is a total of the mirror currents Im1 and Im2 is restricted to values equal to or less than the predetermined upper limit value.
In this manner, in the power supply device 1 of the present embodiment, the mirror transistor of the overcurrent protection circuit OCP is divided in a plurality of mirror transistors (the two mirror transistors M11 and M12 in the present figure). Moreover, operation timings of the mirror transistors M11 and M12 are shifted from each other by the resistor R10.
Referring to the present figure, rising and falling of the gate drive signal G2 are delayed compared to those of the gate drive signal G1. Accordingly, the mirror transistor M12 operates with a delay compared to the mirror transistor M11. As a result, increase and decrease of the mirror current Im2 are delayed compared to those of the mirror current Im1.
In this manner, by creating a difference in transient response characteristics between the mirror transistors M11 and M12, it is possible to regulate operation timing of the overcurrent protection circuit OCP (=start-up timing of the overcurrent protection operation) as necessary in accordance with a size ratio between the mirror transistors M11 and M12. This makes it possible to suppress peak current while improving load variation characteristics.
Note that a solid line of the output current Iout indicates a behavior of the output current Iout when a mirror current ratio Im1/Im2=2/1. On the other hand, a dotted line of the output current Iout indicates a behavior of the output current Iout when the mirror current ratio Im1/Im2=1/2.
The mirror current ratio Im1/Im2 described above is a ratio between the mirror currents Im1 and Im2 respectively flowing through the mirror transistors M11 and M12 in a steady state of the power supply device 1. That is, the mirror current ratio Im1/Im2 may be understood as a size ratio between the mirror transistors M11 and M12.
As is clear from comparison between the solid line and the dotted line of the output current Iout, in the power supply device 1 of the present embodiment, by regulating the mirror current ratio Im1/Im2, it is possible to suppress transient peak current at the startup of the power supply device 1.
Note that a solid line of the output current Iout indicates a behavior of the output current Iout when a mirror current ratio Im1/Im2=2/1. On the other hand, a dotted line of the output current Iout indicates a behavior of the output current Iout when the mirror current ratio Im1/Im2=1/2.
As is clear from comparison between the solid line and the dotted line of the output current Iout, in the power supply device 1 of the present embodiment, by regulating the mirror current ratio Im1/Im2, it is possible to suppress transient peak current during overcurrent protection operation associated with load variation of the power supply device 1. On the other hand, a DC upper limit value (=overcurrent detection threshold value) of the output current Iout is constant regardless of the mirror current ratio Im1/Im2.
For example, in a case where the size ratio between the output transistors M1 and M2 is 1:2, erroneous operation can occur when Im1/Im2>5/10.
For example, in a case where the size ratio between the output transistors M1 and M2 is 1:2, erroneous operation can occur when Im1/Im2<2/10.
In light of the behaviors illustrated in
Note that, in terms of design philosophy of the power supply device 1, it is desirable to first determine the size ratio between the output transistors M1 and M2 and the resistance value of the resistor R10 so as to optimize the phase characteristics and then set the mirror current ratio Im1/Im2 so as to suppress the peak current while improving the load response characteristics.
Thus, to suppress the peak current while improving the load response characteristics, what is important is to divide the mirror transistor of the overcurrent protection circuit OCP into a plurality of mirror transistors, and it is not necessarily essential to divide the output transistor.
What follows is an overview of the various embodiments disclosed above.
For example, an overcurrent protection circuit disclosed herein includes a first mirror transistor configured to be driven by a first drive signal, common to a first output transistor, so as to pass a first mirror current, a second mirror transistor configured to be driven by a second drive signal so as to pass a second mirror current, a resistor configured to be connected between a control terminal of each of the first output transistor and the first mirror transistor and a control terminal of the second mirror transistor, and a current restriction unit configured to control the first drive signal such that a sense current, which is a total of the first mirror current and the second mirror current, is restricted to values equal to or less than a predetermined upper limit value (a first configuration).
Here, in the overcurrent protection circuit having the first configuration described above, the current restriction unit may be configured to include a sense resistor configured to convert the sense current to a sense voltage and an operational amplifier configured to regulate the first drive signal in accordance with the sense voltage (a second configuration).
Further, in the overcurrent protection circuit having the first or second configuration described above, the first mirror transistor and the second mirror transistor may be smaller in size than the first output transistor (a third configuration).
Further, in the overcurrent protection circuit having any one of the first to third configurations described above, the resistor may have a resistance value of several tens to several hundreds kΩ (a fourth configuration).
Further, for example, a power supply device disclosed herein is configured to include the first output transistor configured to be connected between an input terminal for an input voltage and an output terminal for an output voltage so as to be driven by the first drive signal, an output feedback circuit configured to generate the first drive signal in accordance with a difference between the output voltage, or a feedback voltage in accordance with the output voltage, and a predetermined reference voltage, and the overcurrent protection circuit having any one of the first to fourth configurations described above (a fifth configuration).
Here, the power supply device having the fifth configuration described above may further be configured to include a second output transistor configured to be connected between the input terminal for the input voltage and the output terminal for the output voltage so as to be driven by the second drive signal (a sixth configuration).
In the power supply device having the sixth configuration described above, the second output transistor may be larger in size than the first output transistor (a seventh configuration).
The power supply device having the seventh configuration described above may be configured such that a size ratio between the first output transistor and the second output transistor is 1:2 (an eighth configuration).
The power supply device having the eighth configuration described above may be configured such that 2/8<Im1/Im2<4/6 holds, where Im1 and Im2 respectively represents the first mirror current and the second mirror current in a steady state (a ninth configuration).
In the power supply device having any one of the fifth to ninth configurations described above, the output feedback circuit may be configured to include an error amplifier configured to generate the first drive signal in accordance with the difference between the output voltage or the feedback voltage and the reference voltage (a tenth configuration).
With the disclosure herein, it is possible to provide an overcurrent protection circuit and a power supply device which are capable of suppressing a peak current while improving load response characteristics.
The various technical features disclosed herein may be implemented in any other manners than in the embodiments described above, and allow for any modifications made without departure from their technical ingenuity. For example, bipolar and MOS field-effect transistors may be interchanged and logic levels of various signals may be inverted as necessary. That is, it should be understood that the above embodiments are illustrative in all respects and are not intended to limit the present disclosure, that the technological scope of the present disclosure is indicated by the claims, and that all modifications within the scope of the claims and the meaning equivalent to the claims are covered.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-185085 | Nov 2021 | JP | national |
This nonprovisional application is a continuation application of International Patent Application No. PCT/JP2022/037106 filed on Oct. 4, 2022, which claims priority Japanese Patent Application No. 2021-185085 filed on Nov. 12, 2021, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2022/037106 | Oct 2022 | WO |
| Child | 18641740 | US |
