OVERLOAD PROTECTION OF A TRANSFORMER LOADED LINE DRIVER

Abstract

A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10GBase-T cabling is provided. The method includes four wire pairs A, B, C and D, a polarity swapping and scrambler state machine that determine if the chosen pair matches the requirements for pair A. A slave Tap state machine generates a rule for correct B, C and D patterns based on a pair chosen as pair A. The cables B, C and D are iteratively swapped to rearrange the pair mapping into the polarity swap state machine, and a deskew state machine identifies the latency difference between the different pairs. If the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.

Description

FIELD OF THE INVENTION

The invention relates generally to electronic communication systems. More particularly, the invention relates to a training pattern to enable recognition of proper wire-pair orientation and correction in electronic communication systems.

BACKGROUND

In Ethernet 10GBase-T cabling, the data is sent over four pairs of wires. Between the transmitter and receiver, the pairs can be swapped with each other, and the wires in a pair can be swapped. These reconfigurations can result in an inverted signal or the latency of the four pairs can differ. 10GBASE-T, or IEEE 802.3an-2006, is a standard to provide 10 gigabit/second connections over conventional unshielded or shielded twisted pair cables, over distances up to 100 m. This standard mandates specific training patterns to enable recognition of the proper correction, but does not provide a means to find the proper corrections from all the possibilities. Accordingly, there is a need to develop an algorithm to efficiently search the possible corrections and identify the correct one.

SUMMARY OF THE INVENTION

The current invention is a method of recognizing inverted signals and latency difference in wire pairs between a transmitter and receiver in 10GBase-T Ethernet cabling due to wire pair mismatch, and correcting the inversion and latency by swapping the cable orders. The method includes providing four pairs of wires, wherein the wires transmit data between the transmitter and the receiver. The wire pairs include pairs A, B, C, and D, whereas the pairs are arranged in a quadrille pattern having two top pairs and two bottom pairs. The method includes providing a pair swapping state machine, where the swapping state machine selects one pair from the top pairs, whereas the selected pair is designated as pair A. A polarity swapping and scrambler lock state machine is provided, where the lock state machine determines if the designated pair A is a correct choice for position A. The lock state machine then determines if the selected pair is inverted. If the selection for A is not correct a next pair of the wires is designated as pair A and the determination is repeated until the requirements for pair A are met and the pair is not inverted. A slave tap state machine is provided, where the tap state machine establishes a rule for a correct B, C, and D pattern based on the determined pair A. The lock state machine is used to designate a second top pair as pair B. The lock state machine is further used to designate a first bottom pair as pair C and to designate a first bottom pair as pair D. A deskew state machine is provided, where the deskew state machine compares all the designations over all possible latencies with the rules generated by the slave tap machine, where if the rules are not satisfied, the cable swap state machine reverses the designated pair C with designated pair D. The deskew state machine is used to re-compare all the designations over all possible latencies with the rules generated by the slave tap machine, where if the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.

DETAILED DESCRIPTION

Details of various embodiments of the present invention are disclosed in the following appendices:

Appendix A.

Appendix B.

Appendix C.

As one of ordinary skill in the art will appreciate, various changes, substitutions, and alterations could be made or otherwise implemented without departing from the principles of the present invention. Accordingly, the examples and drawings disclosed herein including the appendix are for purposes of illustrating the preferred embodiments of the present invention and are not to be construed as limiting the invention.

Claims

1. An rate adaptation system comprising: a first first-in, first-out (FIFO) buffer configured to: serially receive a plurality of data blocks via a first data bus at a rate based on a first clock; andoutput the plurality of data blocks in response to valid read requests;a barrel shift slot register including a plurality of slots, wherein each of the plurality of slots comprise one of a valid read request or a dummy read request, wherein a ratio of a count of the valid read requests from the plurality of slots to a count of the plurality of slots is based on a ratio of a rate of a second clock to a rate of the first clock, wherein a first count of slots of the plurality of slots between a slot of the plurality of slots including a current dummy read request and a slot of the plurality of slots including an immediately previous dummy invalid read request is different than a second count between the slot including the current dummy read request and a slot of the plurality of slots including an immediately next dummy read request; anda rate adaptation register configured to: sequentially cycle through the plurality of slots of the barrel shift register in response to the first clock to provide the valid read requests to the first FIFO buffer and to receive the plurality of data blocks from the first FIFO buffer;skip provision of valid read requests for clock cycles of the first clock associated with slots of the plurality of slots that include dummy read requests; andprovide the plurality of data blocks to a second FIFO buffer.

2. The rate adaptation system of claim 1, wherein the second FIFO buffer is configured to: serially receive a first plurality data blocks from the rate adaptation register; andoutput the plurality of data blocks in response to second valid read requests.

3. The rate adaptation system of claim 2, further comprising another rate adaptation register configured to provide the second valid read requests to the second FIFO buffer in response to the second clock and to receive the plurality of data blocks from the second FIFO buffer, wherein the other rate adaptation register is configured to provide the plurality of data blocks to a second data bus in response to the second clock.

4. The rate adaptation system of claim 1, wherein the first data bus is configured to operate according to a 10GBASE-T standard protocol.

5. The rate adaptation system of claim 1, wherein the second data bus is configured to operate according to a 10GBASE-T standard protocol that is different than the 10GBASE-T standard protocol to which the first data bus is configured to operate.

6. The rate adaptation system of claim 1, wherein the frequency of the first clock is greater than the frequency of the second clock.

7. The rate adaptation system of claim 1, wherein the first clock is a 400 MHz clock and the second clock is a 312.5 MHz clock.

8. The rate adaptation system of claim 1, wherein the barrel shift register includes 32 slots.

9. The rate adaptation system of claim 1, wherein a count of the dummy read requests included in the plurality of slots of the barrel shift register is a number other than a multiple of a count of the plurality of slots.

10. A method comprising: serially receiving a first plurality of data blocks via a first data bus at a first buffer at a rate based on a first clock;providing, from a rate adaptation register, a sequence of requests to the first buffer in response to the first clock, wherein the sequence of requests includes valid read requests and dummy read requests, wherein a count of cycles of the first clock between consecutive dummy read requests varies within the sequence of requests, and wherein a count of the valid read requests included in the sequence of requests is based on a ratio of a rate of a second clock to a rate of the first clock;providing the plurality of data blocks to the rate adaptation register in response to valid read requests of the sequence of requests; andproviding the plurality of data blocks to a second buffer.

11. The method of claim 10, further comprising determining the sequence of requests by reading slots of a barrel shift slot register, wherein each slot of the slots of the barrel shift slot indicates one of the valid read request or the dummy read request.

12. The method of claim 10, further comprising serially providing the plurality of data blocks to a second data bus.

13. The method of claim 12, further comprising, prior to said providing the plurality of data blocks to a second data bus, retrieving the plurality of data blocks from the second buffer.

14. The method of claim 10, wherein said providing, from a rate adaptation register, a sequence of requests to the first buffer in response to the first clock comprises remaining idle during cycles of the first clock associated with requests of the sequence of requests associated with dummy read requests.

15. The method of claim 10, wherein the rate of the first clock is greater than the rate of the second clock.

16. A method comprising: reading slots of a barrel shift register to determine a sequence of requests, wherein each of the slots of the barrel shift register indicate one of a valid read request or a dummy read request, wherein a count of slots of the barrel shift register indicating the dummy read request is a number other than a multiple of a total count of slots of the barrel shift register;providing, from a rate adaptation register, the sequence of requests to a first buffer in response to a first clock;receiving the plurality of data blocks at the rate adaptation register from the first buffer in response to valid read requests of the sequence of requests; andproviding the plurality of data blocks to a second buffer in response to the first clock.

17. The method of claim 16, further comprising providing the plurality of data blocks from the second buffer to another rate adaption register in response to requests received from the other rate adaption register in response to a second clock.

18. The method of claim 17, further comprising providing the plurality of data blocks to a second data bus in response to a second clock.

19. The method of claim 18, further comprising receiving the plurality of data blocks from a first data bus at the first buffer in response to the first clock.

20. The method of claim 19, wherein the second data bus is configured to operate according to a 10GBASE-T standard protocol that is different than the 10GBASE-T standard protocol to which the first data bus is configured to operate.