Patent Application
20120280227
The present invention relates to an oxide semiconductor device and more particularly relates to a semiconductor device containing a field effect transistor in which an oxide film is used as a channel.
Various studies and developments have been made on a display device having a thin film transistor (TFT) device as a driving transistor for electronic devices. This TFT, which makes it possible to save space, has been used as a transistor for driving a display device of a portable apparatus such as a portable phone, a notebook-type personal computer, a PDA and the like. At present, most of portions of such a TFT have been manufactured by silicon-based semiconductor materials typically represented by crystalline silicon and amorphous silicon. This is because of advantages in that the TFT can be manufactured by using conventional manufacturing processes and manufacturing techniques for a semiconductor device. However, when the semiconductor manufacturing process is used, since the processing temperature is 350° C. or higher, there are some limitations to a substrate to be formed. In particular, most of substrates made of glass or flexible substrates have a heat resistant temperature of 350° C. or lower, and it is consequently difficult to form TFTs by using conventional semiconductor manufacturing processes. For this reason, in recent years, studies and developments have been made on a TFT device (oxide TFT) in which an oxide semiconductor material that can be processed at a low temperature is used. Since the oxide TFT can be manufactured at a low temperature, it is possible to form the oxide TFTs onto a substrate, such as a glass substrate and a plastic substrate, which can be flexibly bendable. Thus, a novel device that has not been conventionally known can be manufactured at low costs. Moreover, by utilizing transparency of the oxide material, application to an RFID tag or the like is also available.
It has been known that the electric characteristics of the oxide semiconductor TFT are strongly dependent on a channel film thickness. For this reason, it is very difficult to form a TFT array having uniform characteristics onto a large area substrate. At present, solutions of this problem are mostly dependent on the device. Moreover, IEDM Tech. Dig., pp. 73-76, (2008) (Non-Patent Document 1) and Japanese Patent Application Laid—Open Publication No. 2009-170905 (Patent Document 1) report that attempt the characteristic improvements, it is reported that by stacking two or more oxide semiconducting layers, the field-effect mobility is improved by two or more times in comparison with that of a single layer structure. However, as the film thickness of a lower channel layer increases, the threshold voltage and field-effect mobility greatly vary. In this method also, the thickness of the channel layer strongly influences the TFT characteristics. For this reason, when a large number of TFTs are formed on a large area without controlling the channel film thickness in the conventional technique, variations in the TFT characteristics increase, causing a problem of an extreme reduction in the yield of products.
A preferred aim of the present invention is to reduce the influences of the channel film thickness that cause variations in the TFT characteristics. The above and other preferred aims and novel characteristics of the present invention will be apparent from the description of the present specification and the accompanying drawings.
The typical ones of the inventions disclosed in the present application will be briefly described as follows.
First, the present invention is characterized in that a field-effect transistor includes: a gate electrode, a first semiconducting layer that is formed on the gate electrode interposing a gate insulating layer therebetween; a second semiconducting layer connected to the first semiconducting layer; a source electrode connected to the second semiconducting layer; and a drain electrode connected to the second semiconducting layer, and this structure is characterized in that the first semiconducting layer contains In element and O element, and the second semiconducting layer contains Zn element and O element.
Second, in a method of manufacturing a field-effect transistor, a first process for forming a first semiconducting layer containing In element and O element and a second process for forming a second semiconducting layer containing Zn element and O element on the first semiconducting layer are included.
The present invention makes it possible to reduce the film-thickness dependence of a field-effect transistor.
BRIEF DESCRIPTIONS OF THE DRAWINGS
First, a schematic device structure of the present invention is described in a first example. A method of manufacturing a semiconductor device shown in
Examples of the substrate include a Si substrate, a sapphire substrate, a quartz substrate and a glass substrate, as well as a flexible resin sheet, a so-called plastic film, etc. Examples of the plastic film include polyethylene terephthalate, polyethylene naphthalate, polyetherimide, polyacrylate, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. Examples of the electrode material include: oxide materials in which Al, Ga, In, B or the like is added to ITO or ZnO, and metals, such as Mo, Co, W, Ti, Au, Al, Ni, Pt or the like and composite materials thereof. Moreover, these semiconductor materials may be subjected to a doping treatment, if necessary. The first channel layer is a compound containing at least In element and O element.
Furthermore, compounds containing Zn element, Sn element, Ge element or Si element may be used. Specific examples of the compounds include indium oxide, In—Mn—O (Mn:Sn, Zn, Si, Ge) in which tin, zinc, silicon and germanium are added to indium oxide, etc. In this case, in the constituent elements other than oxygen, the composition ratio of In element is 50% or more. The second channel layer is a compound containing at least Zn element and O element. This may further contain a Sn element. Specific examples of the compound correspond to Zn—O, Zn—Sn—O, etc., without containing In element. In order to improve performances of the oxide semiconductor transistor, after being formed, the oxide semiconductor may be subjected to an annealing treatment. Examples of the insulating film material, oxides and nitrides of silicon, oxides and nitrides of aluminum, and metal oxides, such as Y2O3, YSZ and HfO2, as well as organic insulating polymers, such as a polyimide derivative, a benzocyclobutene derivative, a photoacrylic derivative, a polystyrene derivative, a polyvinyl phenol derivative, a polyester derivative, a polycarbonate derivative, a polyester derivative, a polyvinyl acetate derivative, a polyurethane derivative, a polysulfone derivative, an acrylate resin, an acryl resin, an epoxy resin, etc.
As described above, the invention according to the present example provides an field-effect transistor, and a feature is a structure including: a gate electrode; a first semiconducting layer formed on the gate electrode interposing a gate insulating film between the first semiconducting layer and the gate electrode; a second semiconducting layer connected to the first semiconducting layer; a source electrode connected to the second semiconducting layer; and a drain electrode connected to the second semiconducting layer, the first semiconducting layer containing In element and O element, and the second semiconducting layer containing Zn element and O element. By using this structure, it is possible to reduce the film-thickness dependency of the field-effect transistor. More specifically, it is possible to reduce the film-thickness dependency of the threshold voltage and field-effect mobility on the semiconducting layer. As a result, it is possible to provide a TFT array having uniform characteristics on a large area substrate, and consequently, it is possible to achieve a display device, an RFID tag, etc. using these TFTs.
The basis of the film-thickness dependency will be explained later based upon experimental results, etc.
Note that, the invention according to the present example is not limited to the above-mentioned structure, and various changes may be made within the scope not departing from the technical idea of the present invention.
A manufacturing method of the semiconductor device according to the second example will be described below. First, as shown in
The substrate SUB is made of, for example, a glass, quartz or plastic film, and, if necessary, a coating process of an insulating film is carried out on a surface on the side where the gate electrode GE is formed.
The gate electrode GE is prepared as a single film made of a conductive material, such as molybdenum, chromium, tungsten, aluminum, copper, titanium, nickel, tantalum, silver, cobalt, zinc, gold or other metals, or an alloy film of these, a laminate film of these, or a metal oxide conductive film, such as ITO (In—Sn—O: indium-tin oxide), a laminate film of these and metal, or a metal nitride conductive film, such as titanium nitride (Ti—N), a laminate film of these and metal, other conductive metal compound films, a laminate film of these and metal, a semiconductor having carriers at a high density, or a laminate film of the semiconductor and metal, and its film-forming process is carried out by a vapor deposition method, a chemical vapor deposition (CVD) method, a sputtering method, or the like, and the film is processed by using a combination of a general-use photolithography technique and dry etching or wet etching.
The gate insulating film GI is preferably prepared as an oxide insulating film made of Si—O, Al—O, etc, or may be prepared as an inorganic insulating film formed of a material other than oxides, such as Si—N, or as an organic insulating film formed of perylene, etc. The film-forming process of the gate insulating film GI is carried out by a vapor deposition method, a CVD method, a sputtering method, an application method, or the like, and the film is processed by using a combination of a general-use photolithography technique and dry etching or wet etching.
The first semiconducting layer CH1 is formed of an oxide, such as In—O, In—Zn—O, In—Sn—O, In—Ga—O or In—Si—O and a composite oxide thereof, and its film-forming process is carried out by a sputtering method, a pulsed laser deposition (PLD) method, a CVD method, an application method, a printing process, etc. After completion of the step of forming the first semiconducting layer CH1, a step of removing the first semiconducting layer CH1 except for a predetermined portion is carried out. This step is carried out by using a combination of a general-use photolithography technique and wet etching or dry etching. In the present example, as the first semiconducting layer CH1, In—Sn—O (In:Sn=90:10) is formed with a film thickness of 3 to 60 nm, by a sputtering method, under conditions of a gas pressure of 0.5 Pa (Ar+10% O2), a DC power of 50 W and a growth temperature (room temperature). After completion of this step, the first semiconducting layer CH1 is processed into an island pattern. In this case, it is defined that the “island pattern” refers to a state in which required portions of the first semiconducting layer CH1 are left and the other portion are removed. This term is also used in the same manner in the following descriptions.
Thereafter, as shown in
Thereafter, as shown in
Characteristics of the above-described field-effect transistor and the manufacturing method thereof will be described as follows.
The method is characterized by a first step of forming a first semiconducting layer having In element and O element on a gate insulating film and a second step of forming a second semiconducting layer having Zn element and O element on the first semiconducting film. Providing at least these steps is to achieve a preferred aim of the present invention to achieve the field-effect transistor explained with reference to
In particular, the invention according to the second example is characterized in that, after carrying out the first step, a third step of removing the first semiconducting layer except for a predetermined portion is further carried out. In particular, these characteristics make it possible to achieve a field-effect transistor having a structure as shown in
The effects obtained by this structure are clearly indicated in comparison with a field-effect transistor according to
A comparative example 1 only differs from the second example in that the second semiconducting layer CH2 is formed of an oxide material containing In, and the other points are the same as those of the second example.
The second semiconducting layer CH2 in the comparative example 1 is formed of an oxide, such as In—O, In—Ga—Zn—O, In—Sn—O, In—Zn—O and In—Ga—O, and a composite oxide thereof, and its film-forming process is carried out by a sputtering method, a PLD method, a CVD method, an application method, a printing process, etc. In the present comparative example 1, In—Sn—O was used as the first semiconducting layer CH1 and In—Ga—Zn—O was used as the second semiconducting layer, and the In—Ga—Zn—O film was formed by a sputtering method carried out under the conditions of a gas pressure of 0.5 Pa (Ar+20% O2), an RF power of 50 W and a growth temperature (room temperature).
In this manner, different from the invention according to the comparative example 1, in particular, since the present applied invention allows the first semiconducting layer CH1 to contain In element, the resulting effect of reducing the film-thickness dependency of a field-effect transistor is achieved.
A comparative example 2 only differs from the second example in that the two kinds of second semiconducting layers are not used and only a semiconducting layer with a single layer being used, and the other points are the same as those of first example.
The semiconducting layer CH of the present comparative example 2 is formed in an island pattern so as to isolate devices, and the layer is processed by using a combination of a general-use photolithography technique and wet etching or dry etching.
The semiconducting layer CH is formed of an oxide of Zn, In, Ga and Sn, such as Zn—O, In—O, Ga—O, Sn—O, In—Ga—Zn—O, Zn—Sn—O, In—Sn—O, In—Zn—O, Ga—Zn—O and In—Ga—O, and a composite oxide thereof, and its film-forming process is carried out by a sputtering method, a PLD method, a CVD method, an application method, a printing process, etc. In the present comparative example, by using Zn—Sn—O as a semiconducting layer CH, the layer was formed with a thickness of 5 to 60 nm by a sputtering method carried out under the conditions of a gas pressure of 0.5 Pa (Ar+8% O2), an RF power of 50 W and a growth temperature (room temperature).
In this manner, being different from the invention according to the comparative example 2, in particular, since the present invention has a structure in which a two-layer structure of the first semiconducting layer and the second semiconducting layer is combined with a channel material, the resulting effect of reducing the film-thickness dependency of a field-effect transistor is achieved.
A third example differs from the second example in that a step of simultaneously processing the first semiconducting layer CH1 and the second semiconducting layer CH2 is prepared and in that the source-drain electrode wiring layer SD is connected to both of the semiconducting layers CH. The other points are the same as those of the second example.
The manufacturing method of the semiconductor device according to the present fourth example is as follows. First, as shown in
The first semiconducting layer CH1 is formed of an oxide, such as In—O, In—Zn—O, In—Sn—O, In—Ga—O and In—Si—O, and a composite oxide thereof, and the second semiconducting layer CH2 is formed of an oxide such as Zn—Sn—O, Zn—O, and Sn—O. The film-forming process of these is carried out by a sputtering method, a PLD method, a CVD method, an application method, a printing process, etc. In the present example, as the first semiconducting layer CH1, In—Sn—O (In:Sn=70:30) i s formed with a film thickness of 3 to 60 nm, by a sputtering method, under conditions of a gas pressure of 0.5 Pa (Ar+10% O2), a DC power of 50 W and a growth temperature (room temperature). As the second semiconducting layer CH2, Zn—Sn—O (Zn:Sn=30:70) is formed with a film thickness of 5 to 75 nm, by a sputtering method, under conditions of a gas pressure of 0.5 Pa (Ar+20% O2), an RF power of 50 W and a growth temperature (room temperature). After completion of the steps of sequentially depositing the first semiconducting layer CH1 and the second semiconducting layer CH2 in this manner, a step of removing the first semiconducting layer CH1 and the second semiconducting layer except for predetermined portions is carried out. The processing of this step is carried out by using a combination of a general-use photolithography technique and dry etching or wet etching.
Thereafter, as shown in
Thereafter, as shown in
A TFT manufactured with a channel length of 0.1 mm and a channel width of 2 mm had the same characteristics as those of the TFT manufactured according to the second example. Within a range of 5 nm or more in the film thickness of the first semiconducting layer CH1 and a range of 5 to 50 nm in the film thickness of the second semiconducting layer CH2, a threshold voltage within ±1 V, a field-effect mobility in a range from 45 to 51 cm2/Vs and an ON-state current of 2×10−4 A were obtained. Since changes in characteristics relative to film-thickness variations hardly occurred, it is possible to easily manufacture a TFT array on a large area substrate.
The above-mentioned field-effect transistor and the features of the manufacturing method thereof will be discussed below in comparison with, in particular, the field-effect transistor according to the second example and the manufacturing method thereof.
The invention according to fourth example is characterized in that, after completion of a first step of forming a first semiconducting layer containing In element and O element on a gate insulating film, a second step of forming a second semiconducting layer containing Zn element and O element on the first semiconducting layer is carried out, and after completion of the second step, a sixth step of removing the first semiconducting layer and the second semiconducting layer except for predetermined portions is further carried out.
The field-effect transistor manufactured in this manufacturing method makes it possible to achieve the effect for reducing the film-thickness dependency of a field-effect transistor in the same manner as the second example, in particular, by the structure in which only the source electrode and the second semiconducting layer are directly connected with each other.
The manufacturing method of the semiconductor device according to the present fifth example is as follows. First, as shown in
SU in this order.
Thereafter, as shown in
Thereafter, as shown in
A TFT manufactured with a channel length of 0.1 mm and a channel width of 2 mm had equivalent characteristics as those of the TFT manufactured according to the second example. Within a range of 5 nm or more in the film thickness of the first semiconducting layer CH1 and a range of 5 to 50 nm in the film thickness of the second semiconducting layer CH2, a threshold voltage within ±1 V, a field-effect mobility in a range from 43 to 50 cm2/Vs and an ON-state current of 2×10−4 A were obtained. Since changes in characteristics relative to film-thickness variations hardly occurred, it is possible to easily manufacture a TFT array on a large area substrate.
The manufacturing method of the semiconductor device according to the present sixth example is as follows. First, as shown in
The second semiconducting layer CH2 is formed of an oxide, such as Zn—Sn—O, Zn—O and Sn—O, and its film-forming process is carried out by a sputtering method, a PLD method, a CVD method, an application method, a printing process, etc. The film is processed by using a combination of a general-use photolithography technique and dry etching or wet etching. In the present example, as the second semiconducting layer CH2, Zn—Sn—O (Zn:Sn=30:70) was formed with a film thickness of 5 to 75 nm, by a sputtering method carried out under the conditions of a gas pressure of 0.5 Pa (Ar+20% O2), an RF power of 50 W and a growth temperature (room temperature).
After the film formation, the source-drain electrode SD is processed by using a combination of a general-use photolithography technique and dry etching or wet etching.
The first semiconducting layer CH1 is made from an oxide, such as In—O, In—Zn—O, In—Sn—O, In—Ga—O and In—Si—O, and a composite oxide thereof, and its film-forming process is carried out by a sputtering method, a PLD method, a CVD method, an application method, a printing process, etc. The film is processed by using a combination of a general-use photolithography technique and dry etching or wet etching. In the present example, as the first semiconducting layer CH1, In—Ga—O (In:Ga=95:5) is formed with a film thickness of 3 to 60 nm, by a sputtering method carried out under the conditions of a gas pressure of 0.5 Pa (Ar+10% O2), a DC power of 50 W and a growth temperature (room temperature).
Thereafter, as shown in
Thereafter, as shown in
A TFT manufactured with a channel length of 0.1 mm and a channel width 2 mm had the same characteristics as those of the TFT manufactured in second example. Within a range of 5 nm or more in the film thickness of the first semiconducting layer CH1 and a range of 5 to 50 nm in the film thickness of the second semiconducting layer CH2, a threshold voltage within ±1 V, a field-effect mobility in a range from 42 to 48 cm2/Vs and an ON-state current of 2×10−4 A were obtained. Since changes in characteristics relative to film-thickness variations hardly occurred, it is possible to easily manufacture a TFT array on a large area substrate.
A manufacturing method of the semiconductor device in the present seventh example is as follows. First, as shown in
After the film formation, the source-drain electrode SD is processed by using a combination of a general-use photolithography technique and dry etching or wet etching.
The second semiconducting layer CH2 is made from an oxide, such as Zn—Sn—O, Zn—O and Sn—O, and its film-forming process is carried out by a sputtering method, a PLD method, a CVD method, an application method, a printing process, etc. The film is processed by using a combination of a general-use photolithography technique and dry etching or wet etching. In the present example, as the second semiconducting layer CH2, Zn—O (zinc oxide: 100%) was formed with a film thickness of 5 to 75 nm, by a sputtering method carried out under the conditions of a gas pressure of 0.5 Pa (Ar+20% O2), an RF power of 50 W and a growth temperature (room temperature).
The first semiconducting layer CH1 is made from an oxide, such as In—O, In—Zn—O, In—Sn—O, In—Ga—O and In—Si—O, and a composite oxide thereof, and its film-forming process is carried out by a sputtering method, a PLD method, a CVD method, an application method, a printing process, etc. The film is processed by using a combination of a general-use photolithography technique and dry etching or wet etching. In the present example, as the first semiconducting layer CH1, In—Si—O (In:Si=95:5) is formed with a film thickness of 3 to 60 nm, by a sputtering method carried out under the conditions of a gas pressure of 0.5 Pa (Ar+10% O2), a DC power of 50 W and a growth temperature (room temperature).
Thereafter, as shown in
Thereafter, as shown in
A TFT manufactured with a channel length of 0.1 mm and a channel width of 2 mm had the same characteristics as those of the TFT manufactured according to the second example. Within a range of 5 nm or more in the film thickness of the first semiconducting layer CH1 and a range of 5 to 50 nm in the film thickness of the second semiconducting layer CH2, a threshold voltage within ±1 V, a field-effect mobility in a range from 43 to 47 cm2/Vs and an ON-state current of 2×10−4 A were obtained. Since changes in characteristics relative to film-thickness variations hardly occurred, it is possible to easily manufacture a TFT array on a large area substrate.
A comparative example 3 only differs from the examples 1 to 7 in that, in constituent elements other than oxygen in the first semiconducting layer, the compounding ratio of In element is less than 50%, and the other points are the same as those of examples 1 to 7.
The structure and manufacturing method of the semiconductor device according to the comparative example 3 are the same as those of the seventh example (
The manufacturing method of the semiconductor device is explained below. First, as shown in
After the film formation, the source-drain electrode SD is processed by using a combination of a general-use photolithography technique and dry etching or wet etching.
The second semiconducting layer CH2 is formed of an oxide, such as Zn—Sn—O, Zn—O and Sn—O, and its film-forming process is carried out by a sputtering method, a PLD method, a CVD method, an application method, a printing process, etc. The film is processed by using a combination of a general-use photolithography technique and dry etching or wet etching. In the present example, as the second semiconducting layer CH2, Zn—Sn—O (Zn:Sn=50:50) is formed with a film thickness of 5 to 75 nm, by a sputtering method carried out under the conditions of a gas pressure of 0.5 Pa (Ar+20% O2), an RF power of 50 W and a growth temperature (room temperature).
The first semiconducting layer CH1 is made from an oxide, such as In—O, In—Zn—O, In—Sn—O, In—Ga—O and In—Si—O, and a composite oxide thereof, and its film-forming process is carried out by a sputtering method, a PLD method, a CVD method, an application method, a printing process, etc. The film is processed by using a combination of a general-use photolithography technique and dry etching or wet etching. In the present example, as the first semiconducting layer CH1, In—Si—O (In:Si=40:60) is formed with a film thickness of 3 to 60 nm, by a sputtering method carried out under the conditions of a gas pressure of 0.5 Pa (Ar+10% O2), a DC power of 50 W and a growth temperature (room temperature).
Thereafter, as shown in
Thereafter, as shown in
In the TFT manufactured and compared with the TFT manufactured according to the examples 2 to 7, as the film thickness of the first semiconducting layer CH1 increased, the threshold voltage was shifted so that a field-effect mobility of about 15 to 20 cm2/Vs was exerted. When the compounding ratio of In element became less than 50% in the constituent elements other than oxygen in the first semiconducting layer CH1, the TFT characteristics drastically deteriorated. The reason for this result is presumably because the carriers were reduced due to the reduction of In concentration inside the first semiconducting layer CH1.
When the above-mentioned array is applied to an active-matrix-type liquid crystal display device, each element is formed in a configuration as shown in, for example,
In the foregoing, the invention made by the inventors of the present invention has been concretely described based on the embodiments. However, it is needless to say that the present invention is not limited to the foregoing embodiments and various modifications and alterations can be made within the scope of the present invention.
The present invention relates to an oxide semiconductor device, and can be applied to a semiconductor device containing a field-effect transistor in which an oxide film is used as a channel.
SU . . . Substrate, GE . . . Gate electrode, GI . . . Gate insulating film, CH1 . . . First semiconducting layer, CH2 . . . Second semiconducting layer, tc1 . . . Film thickness of first semiconducting layer, tc2 . . . Film thickness of second semiconducting layer, SE . . . Source electrode, DE . . . Drain electrode, VS . . . Source voltage, VD . . . Drain voltage, VG . . . Gage voltage, SD . . . Source-drain electrode, wiring, CH . . . Semiconducting layer, Rc . . . Resistance value of channel layer, Rc1 . . . Resistance value of first semiconducting layer between channel layer and source-drain electrode, Rc2 . . . Resistance value of second semiconducting layer between channel layer and source-drain electrode, CON . . . Wiring contact hole, BL . . . Barrier layer, 11 . . . Antenna resonance circuit, 12 . . . Rectifier, 13 . . . Modulator, 14 . . . Digital circuit, 15 . . . Reader, 16 . . . Writer, 17 . . . Gate wiring, 18 . . . Gate line driving circuit, 19 . . . Data wiring, 20 . . . Data wiring driving circuit, 21 . . . Thin film transistor, 22 . . . Pixel electrode
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-269436 | Nov 2009 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2010/070816 | 11/22/2010 | WO | 00 | 5/25/2012 |
