Embodiments relate to packaging semiconductor devices. More particularly, the embodiments relate to electronic packages with embedded magnetic power transformers for switched-mode power supply (SMPS) operations.
In existing electronic packaging architectures, the switched-mode power supply (SMPS) primarily utilizes buck circuitry topology and closely related derivatives. The use of such circuitry is largely driven by limitations of presently available transformer architectures. For example, existing package integrated transformers suffer from a high leakage inductance. That is, the inductive coupling of such transformers is too low. As such, so-called isolated SMPS technologies, such as fly-back power supplies, forward power supplies, and full-bridge power supplies (which require low-loss operation of the transformer) are not currently feasible.
Transformers with suitably low losses have been proposed for integration into package architectures, but they are not without issue. One such proposal uses a discrete magnetic core that is clamped around a printed circuit board (PCB). The windings around the magnetic core can then be implemented using the PCB routing. However, the construction and routing techniques used are not suitable for the type of package embedding required for a fully integrated voltage regulator (FIVR) style solution.
Additionally, discrete transformers are too thick for die side assembly for many applications of interest since assembly rules, maximum thicknesses, etc. severely limit the number of locations on the package where such a component could be placed. Another issue with discrete transformers is that most SMPS require highly customized transformer design, as opposed to using a high-volume off-the-shelf component. Therefore, providing customized design of discrete transformers results in a significant increase in the cost.
Described herein are electronic packages with highly coupled transformers, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
As noted above, switched-mode power supply (SNIPS) architectures are currently limited by transformers with relatively high losses. As such, isolated SMPS architectures that provide better performance are not currently a feasible option. Isolated SMPS topologies (such as fly-back, forward, and full-bridge) have several beneficial characteristics. For example, they provide high conversion ratios between the input and output voltage by controlling the turns ratio of the transformer. Controlling the ratio of the turns is difficult for currently used buck converters. Isolated SMPS topologies can also be stacked in order to reduce the voltage handled by each converter. This allows for faster, lower-voltage switches to be used.
Accordingly, embodiments disclosed allow for isolated SMPS topologies to be embedded directly in the package substrate. The highly coupled transformers disclosed herein may facilitate voltage conversion from VIN=12V or larger to VOUT=1.8V or 1.0V in the switching frequency range of 5 MHz to 100 MHz. Such embodiments also allow for the creation of custom highly-coupled transformer arrays instead of relying on individual surface mounted components. As such, cost savings are provided and there is no increase to the Z-height of the electronic package.
In an embodiment, a magnetic core is embedded in the package core layer. Windings are formed around the magnetic core using traces, vias, and plated through holes through the package core layer. The transformers described herein allow for flexibility in deciding the turn ratio. For example transformation ratios may range from 1:1 to 8:1, or even higher. Additionally, the primary winding and the secondary winding may be interleaved to provide a high coupling coefficient. The high coupling coefficient may be provided by forming the secondary windings with a plurality of electrically parallel segments. As such, the secondary winding may be interleaved with the each of the turns of the primary winding. Coupling factors of transformers disclosed herein may be 0.9 or above. Embodiments herein also allow for balancing the resistance of the primary and secondary windings. For example, in a 4:1 transformer, the current in the primary winding will be approximately four times lower than the current in the secondary winding. Since the DC power dissipation is proportional to current squared, it is desirable for the DC resistance in the secondary winding to be much lower than that of the primary winding in order to optimize losses for a fixed volume of copper.
To provide context, an example of an inductor 100 is shown in
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As noted above, the formation of an inductor using an embedded magnetic core provides the foundation for forming transformer architectures such as those described herein. That is, transformers may be fabricated using a primary winding including one or more turns and a secondary winding including one or more turns. Each turn of the primary winding and the secondary winding may have a structure similar to the inductors 100 and 200 described above.
A schematic of a transformer 380 in accordance with such an embodiment is shown in
A primary winding 381 may comprise a plurality of turns that are connected in series. In
A secondary winding 382 may comprise one or more turns. In
Accordingly, embodiments disclosed herein may also comprise a secondary winding that includes a single turn that is formed by a plurality of electrically parallel segments.
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In an embodiment, each turn 481A-D comprises an outer pad 483 and an inner pad 484. The outer pads 483 extend beyond the outer diameter of the magnetic core 420, and the inner pads 484 extend outside an inner diameter of the magnetic core. In an embodiment, each segment includes a plurality of outer PTHs 440OP that extend up from the outer pads 483, and a plurality of inner PTHs 440IP that extend up from the inner pads 484. In an embodiment, each segment further includes a trace 485 that electrically couples the inner PTHs 440IP to the outer PTHs 440OP. Since the ends of each segment are connected to the same pads 483/484, the segments are electrically in parallel and function as a single turn.
In an embodiment, the turns 481A-D may be connected to each other in series. For example, linking traces 489 provide the connection between turns. The linking traces 489 may be on the same layer as the outer pads 483 and the inner pads 484. In an embodiment, the linking traces 489 may start at the outer pad 483 and extend to the inner pad 484 of the next turn 481.
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In an embodiment, the secondary winding 482 may comprise an inner pad 487 and an outer pad 486. The inner pad 487 may extend beyond an inner diameter of the magnetic core 420, and the outer pad 486 may extend past an outer diameter of the magnetic core 420. In an embodiment, the inner pad 487 and the outer pad 486 may be provided on a different routing layer than the inner pad 484 and the outer pad 483 of the primary winding.
In an embodiment, each segment of the secondary winding 482 may comprise an inner PTH 440IS, an outer PTH 440OS, and a trace 488 electrically coupling the inner PTH 440IS to the outer PTH 440OS. In an embodiment, the secondary winding 482 may have any number of segments per turn. For example, the illustrated embodiment is shown as having eight segments. In an embodiment, the number of segments of the secondary winding may be equal to the number of turns of the primary winding. In such an embodiment, a single segment of the secondary winding may be interleaved between each turn of the primary winding. In another embodiment, the number of segments of the secondary winding may be an integer multiple of the number of turns of the primary winding. In such an embodiment, a segment of the secondary winding may be provided between each turn of the primary winding, and one or more segments of the secondary winding may be interleaved between segments of a turn in the primary winding. The ability to provide interleaving of many segments of the primary winding and the secondary winding allows for exceptionally high coupling factors, even when the turn ratio is also high.
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In an embodiment, the secondary winding includes a plurality of segments that are connected in parallel (out of the plane of
In an embodiment, the segments of the secondary winding are interleaved between each turn of the primary winding. That is, two segments of a turn of the primary winding (e.g., traces 585) may be adjacent to each other, and traces 588 of the secondary winding may bracket the two traces 585 of the turn of the primary winding.
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As shown, the PTHs 540 pass through the package substrate core. PTHs 540OP and 540OS are provided outside the outer diameter of the magnetic core 520, and PTHs 540IP and 540IS are provided inside an inner diameter of the magnetic core 520. In an embodiment, the outer PTHs 540OP and 540OS may all be positioned a substantially equal distance from an axial center of the transformer 580. In an embodiment, the inner PTHs 540IS may be positioned closer to the axial center of the transformer 580 than the inner PTHs 540IP.
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In an embodiment, portions of the secondary winding are provided in the second routing layer. For example, an inner pad 587 and an outer pad 586 are provided in the second routing layer. The inner pad 587 is electrically coupled to each of the inner PTHs 540IS, and the outer pad 586 is electrically coupled to each of the outer PTHs 540OS. As such, the inner PTHs 540IS are electrically in parallel, and the outer PTHs 540OS are electrically in parallel. As such, the secondary winding provides single turn with a plurality of electrically parallel segments.
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In an embodiment, portions of the primary winding are provided in the third routing layer. For example, inner pads 584 and outer pads 583 are provided in the third routing layer. Each inner pad 584 may be coupled to a pair of inner PTHs 540IP, and each outer pad 583 may be coupled to a pair of outer PTHs 540OP. The PTHs 540 may be coupled to the pads 583 and 584 by vias that pass through the second routing layer.
As shown, there are eight pairs of inner pads 584 and outer pads 583. This provides a total of eight turns for the primary winding, with each turn comprising a plurality of segments. In an embodiment, the turns are electrically connected to each other in series by a linking trace 589 in the third routing layer. The linking trace 589 connects an outer pad 583 of a first turn to an inner pad 584 of a second turn.
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In an embodiment, one or both of the electronic package 692 and the board 691 may comprise a transformer 680 (indicated with a dashed box). The transformers of the electronic package 692 and the board 691 may be transformers similar to those described above. For example, the transformers 680 may include highly coupled primary and secondary windings. In an embodiment, the transformers 680 may comprise a secondary winding that includes a plurality of segments that are electrically in parallel to provide a single turn. In an embodiment, the primary winding may comprise a plurality of turns. In some embodiments, the each turn of the primary winding may also comprise a plurality of electrically parallel segments.
These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of the invention, the integrated circuit die of the processor may be coupled to an electronic package with a highly coupled transformer, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with another implementation of the invention, the integrated circuit die of the communication chip may be coupled to an electronic package with a highly coupled transformer, in accordance with embodiments described herein.
The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
a power transformer, comprising: a magnetic core that is a closed loop with an inner dimension and an outer dimension; a primary winding around the magnetic core, wherein the primary winding has a first number of first turns connected in series around the magnetic core; and a secondary winding around the magnetic core, wherein the secondary winding has a second number of second turns around the magnetic core, wherein individual ones of the second turns comprise a plurality of secondary segments connected in parallel.
the power transformer of Example 1, wherein the plurality of secondary segments are interleaved with the first turns.
the power transformer of Example 1 or Example 2, wherein the magnetic core is a toroidal shape.
the power transformer of Examples 1-3, wherein individual ones of the first turns comprise a plurality of primary segments connected in parallel.
the power transformer of Example 4, wherein individual ones of the secondary segments are interleaved between primary segments of a single first turn.
the power transformer of Examples 1-5, wherein a number of secondary segments of individual ones of the second turns is equal to the first number of first turns.
the power transformer of Examples 1-6, wherein the first number of first turns is an integer multiple of the second number of second turns.
the power transformer of Example 7, wherein the first number of first turns is four or eight, and the second number of second turns is one.
the power transformer of Examples 1-8, wherein the magnetic core is embedded in a core layer of a package substrate.
an electronic package, comprising: a package core layer; a magnetic core embedded in the package core layer, wherein the magnetic core comprises an inner diameter and an outer diameter; a plurality of routing layers above and below the package core layer; a primary winding around the magnetic core, wherein the primary winding has a first number of first turns; a secondary winding around the magnetic core, wherein the secondary winding has a second number of second turns, and wherein individual ones of the second turns comprise a plurality of secondary segments connected in parallel; and wherein horizontal portions of the primary winding and the secondary winding are provided in the plurality of routing layers, and wherein vertical portions of the primary winding and the secondary winding comprise plated through holes through the package core layer.
the electronic package of Example 10, wherein the first number of first turns is an integer multiple of the second number of second turns.
the electronic package of Example 11, wherein the first number of first turns is four or eight, and wherein the second number of second turns is one.
the electronic package of Examples 10-12, wherein the secondary segments are interleaved with the first turns.
the electronic package of Examples 10-13, wherein individual ones of the second turns comprise: a first pad in a first routing layer inside the inner diameter of the magnetic core; a second pad in the first routing layer outside of the outer diameter of the magnetic core; and wherein individual ones of the secondary segments comprise: a first plated through hole electrically coupling the first pad to a second routing layer on an opposite side of the package core layer; a secondary trace in the second routing layer; and a second plated through hole electrically coupling the secondary trace to the second pad.
the electronic package of Example 14, wherein individual ones of the first turns are electrically coupled to each other in series by a linking trace in a third routing layer adjacent to the first routing layer.
the electronic package of Example 14, wherein individual ones of the first turns comprise a plurality of primary segments connected in parallel.
the electronic package of Example 16, wherein individual ones of the first turns comprise: a third pad in a third routing layer inside the inner diameter of the magnetic core, wherein the third routing layer is adjacent to the first routing layer; a fourth pad in the third routing layer outside of the outer diameter of the magnetic core; and wherein individual ones of the primary segments comprise: a third plated through hole electrically coupling the third pad to the second routing layer on the opposite side of the package core layer; a primary trace in the second routing layer; and a fourth plated through hole electrically coupling the primary trace to the fourth pad.
the electronic package of Example 17, wherein individual ones of the secondary segments are interleaved between primary segments of a single first turn.
the electronic package of Examples 10-18, wherein a number of secondary segments of individual ones of the second turns is equal to the first number of first turns.
the electronic package of Examples 10-19, wherein a number of secondary segments of each second turn is an integer multiple of the first number of first turns.
the electronic package of Examples 10-20, wherein the magnetic core is a toroidal shape.
an electronic system, comprising: a die; an electronic package coupled to the die, wherein the electronic package comprises a power transformer, wherein the power transformer comprises: a magnetic core with an inner diameter and an outer diameter; a primary winding around the magnetic core, wherein the primary winding has a first number of first turns connected in series around the magnetic core; and a secondary winding around the magnetic core, wherein the secondary winding has a second number of second turns around the magnetic core, wherein individual ones of the second turns comprise a plurality of secondary segments connected in parallel.
the electronic system of Example 22, wherein the power transformer is part of an isolated switched-mode power supply (SMPS), wherein the isolated SMPS is configured to transfer the full power of a converter through the power transformer.
the electronic system of Example 23, wherein the isolated SMPS is a fly-back converter topology, a forward converter topology, or a full-bridge converter topology.
the electronic system of Examples 22-24, wherein the first number of first turns is four or eight, and the second number of second turns is one.