The present disclosure relates to a packet processing method. More particularly, the present disclosure relates to a packet processing method and a network device that have multiple packet processing methods and a memory management.
Network interface controller (NIC) circuits are commonly utilized in various network devices for transmitting and processing packets. In some related approaches, the network interface controller circuit uses only a single packet processing method. However, in certain situations (for example, when the packet to be processed has a large data size, when the packets to be processed have a small data size, or when the number of packets to be processed is not large), the operation time taken by this packet processing method could be too long, significantly reducing system operational efficiency. On the other hand, when processing packets, the network interface controller circuit needs to request memory space from the system kernel to store the packets and release the previously used memory space after the packet processing is completed. If the number of packets to be processed is large, the frequent operations of requesting and releasing memory space could also decrease system operational efficiency.
In some aspects of the present disclosure, an object of the present disclosure is, but not limited to, provide a packet processing method and a network device that have multiple packet processing methods and a memory management, so as to make an improvement to the prior art.
In some aspects of the present disclosure, a packet processing method includes following operations: allocating a portion of storage space in a memory circuit as a storage pool, in which the storage pool comprise a plurality of first storage blocks; storing a packet in one of the plurality of first storage blocks when a data size of the packet is less than or equal to a predetermined value, and releasing the one of the plurality of the first storage blocks to the storage pool after the packet is processed; requesting an increase in a number of the plurality of first storage blocks from a kernel when a number of remaining storage blocks in the plurality of first storage blocks that do not store data is less than a threshold value; and requesting at least one second storage block from the kernel to increase a data capacity of the storage pool to store the packet when the data size of the packet is greater than the predetermined value, and releasing the at least one second storage block to the kernel after the packet is processed.
In some aspects of the present disclosure, a network device includes a network interface controller circuit, a central processing unit circuit, and a memory circuit. The network interface controller is circuit configured to receive a packet. The central processing unit circuit is configured to execute a kernel and a network interface controller driver. The memory circuit is electrically coupled to the central processing unit circuit. A portion of storage space of the memory circuit is allocated as a storage pool that includes a plurality of first storage blocks, and the storage pool is configured to request an increase in a number of the plurality of first storage blocks from the kernel when a number of remaining storage blocks in the plurality of first storage blocks that do not store data is less than a threshold value. The network interface controller driver is configured to store the packet in one of the plurality of first storage blocks when a data size of the packet is less than or equal to a predetermined value, release the one of the plurality of the first storage blocks to the storage pool after the packet is processed, request at least one second storage block from the kernel to increase a data capacity of the storage pool to store the packet when the data size of the packet is greater than the predetermined value, and release the at least one second storage block to the kernel after the packet is processed.
These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings
The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification.
In this document, the term “coupled” may also be termed as “electrically coupled,” and the term “connected” may be termed as “electrically connected.” “Coupled” and “connected” may mean “directly coupled” and “directly connected” respectively, or “indirectly coupled” and “indirectly connected” respectively. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other. In this document, the term “circuitry” may be a single system formed with at least one circuit, and the term “circuit” may indicate an object, which is formed with one or more transistors and/or one or more active/passive elements based on a specific arrangement, for processing signals.
As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. For ease of understanding, like elements in various figures are designated with the same reference number.
The network device 100 includes a central processing unit (CPU) circuit 110, a network interface controller (NIC) circuit 120, and a memory circuit 130, where the CPU circuit 110 may be configured to execute a NIC driver 112, a protocol stack 114, and a kernel 116. In some embodiments, the NIC driver 112 may be a driver program executed by the CPU circuit 110, which may be configured to set up or control the NIC circuit 120 to process the received packet P1. In some embodiments, the protocol stack 114 may be a software implementation of computer network protocols, which may be configured to interact with the NIC circuit 120 and the kernel 116 to process the received packet P1. In some embodiments, the kernel 116 may be, but is not limited to, a computer program in the operating system that is configured to manage the data transmission requests of various hardware components.
In some embodiments, the NIC circuit 120 may also be referred to as a network interface card. In some embodiments, the NIC circuit 120 may be a circuitry that implements a specific network standard (such as Ethernet, local area network, etc.), which may allow the network device 100 to interact with other devices on the network. The NIC circuit 120 may transmit or receive packet(s) through the network. In a general mode, under the control of the NIC driver 112, the NIC circuit 120 may transmit the received packet P1 to the protocol stack 114 for parsing. Alternatively, in the general mode, the protocol stack 114 may send a packet P2 to be transmitted through the NIC circuit 120 to other devices (not shown). In some embodiments, when the NIC circuit 120 operate in a loopback mode, the NIC driver 112 may release the received packet P1 (labeled as the packet P1′) back to the NIC circuit 120. Thus, the NIC circuit 120 may determine whether the packet P1 and P1′ are the same, thereby checking whether the connection between the network device 100 and another device that sent the packet P1 is correct.
In some embodiments, the NIC driver 112 may selectively utilize the interrupt function or the poll function to process the packet P1 based on the amount of data in the packet P1. Thus, the appropriate packet processing method may be employed based on the actual amount of data in the received packet P1, in order to improve the efficiency of packet processing. Operations regarding herein will be given later with reference to
The memory circuit 130 is electrically coupled to the CPU circuit 110. In some embodiments, the memory circuit 130 is mainly managed by the kernel 116. In some embodiments, the memory circuit 130 may be configured to store various data, and a portion of the storage space of the memory circuit 130 is configured as a storage pool 135. In some embodiments, storage blocks in the storage pool 135 (i.e., different storage spaces in the memory circuit 130) may be configured to store transient data generated during the process of processing the packet P1. In some embodiments, the NIC driver 112 may adjust the settings of the storage blocks in the storage pool 135 to improve the efficiency of sending and receiving packets. Operations regarding herein will be described later with reference to
In some embodiments, a weight W (as shown in
By the aforementioned setting, when the packet P1 is a packet with a large data size, the NIC driver 112 may utilize the poll function to process the packet P1. On the other hand, when the packet P1 is a packet with a small data size, the NIC driver 112 may utilize the interrupt function to process the packet P1. In other words, depending on the data size of the packet P1 to be processed, the NIC driver 112 may utilize the appropriate packet processing method, thereby avoiding excessive occupation of the processing time of the CPU circuit 110 and improving packet processing efficiency.
For ease of understanding and illustration, an example where the network device 100 processing of the packet P1 in the loopback mode is given with reference to
In some embodiments, before starting to receive packets, the NIC driver 112 may request storage space(s) in the memory circuit 130 from the kernel 116 to configure this storage space as the storage pool 135. For example, the NIC driver 112 may utilize a malloc function (which is a memory allocation function) to request the kernel 116 to allocate a portion of storage space in the memory circuit 130 as the storage pool 135. As shown in
In some embodiments, the NIC driver 112 may compare the data size of the received packet P1 with a predetermined value PV (as shown in
For example, as shown in
Values mentioned in
Under this condition, the NIC driver 112 may add constant data PR to the packet P1 (for example, coming from the port 401) when receiving the packet P1. For example, in the process of processing the packet P1, based on a Linux-based network data structure, the NIC driver 112 may add the constant data PR to the data structure of the packet P1 (for example, to the data field cb in the data structure skb) when reading the packet P1 from the original storage blocks in the storage pool 135 (e.g., the storage blocks 301A to 301D shown in
Operations in the packet processing method 500 can be understood with reference to descriptions of above embodiments, and thus repetitious descriptions are not further given herein. The above description of operations of the packet processing method 500 includes exemplary operations, but the operations are not necessarily performed in the order described above. Operations of the packet processing method 500 may be added, replaced, changed order, and/or eliminated, or may be performed simultaneously or partially simultaneously as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure. For example, operation S530 may be performed simultaneously or partially simultaneously with operation S520 and/or S540.
As described above, the packet processing method and the network device provided by some embodiments of the present disclosure are able to select an appropriate processing method from multiple packet processing options according to the data size of the packet and configure a storage pool, which may be dynamically managed, to assist in accelerating packet processing. As a result, the overall efficiency of sending and receiving packets can be enhanced.
Various functional components or blocks have been described herein. As will be appreciated by persons skilled in the art, in some embodiments, the functional blocks will preferably be implemented through circuits (either dedicated circuits, or general-purpose circuits, which operate under the control of one or more processors and coded commands), which will typically comprise transistors or other circuit elements that are configured in such a way as to control the operation of the circuitry in accordance with the functions and operations described herein. As will be further appreciated, the specific structure or interconnections of the circuit elements will typically be determined by a compiler, such as a register transfer language (RTL) compiler. RTL compilers operate upon scripts that closely resemble assembly language code, to compile the script into a form that is used for the layout or fabrication of the ultimate circuitry. Indeed, RTL is well known for its role and use in the facilitation of the design process of electronic and digital systems.
The aforementioned descriptions represent merely the preferred embodiments of the present disclosure, without any intention to limit the scope of the present disclosure thereto. Various equivalent changes, alterations, or modifications based on the claims of the present disclosure are all consequently viewed as being embraced by the scope of the present disclosure.
Number | Date | Country | Kind |
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202310882418.9 | Jul 2023 | CN | national |