Patent Application
20080082870
The above and other features and advantages of example embodiments will become more apparent by describing in detail example embodiments with reference to the attached drawings. The accompanying drawings are intended to depict example embodiments and should not be interpreted to limit the intended scope of the claims. The accompanying drawings are not to be considered as drawn to scale unless explicitly noted.
Detailed example embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Example embodiments may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but to the contrary, example embodiments are to cover all modifications, equivalents, and alternatives failing within the scope of example embodiments. Like numbers refer to like elements throughout the description of the figures.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
While the data of the four bit lines may be illustrated as included in a single transfer data signal in
Each data input unit 510 may receive an m-bit data signal including n data bits and (m-n) parity bits, where m and n are positive integers, and n is not greater than m. The m-bit data signal may be compressed by k bits to form m/k compressed data signals DQ, where k is a positive integer not greater than m. For example, as shown in
Each data input unit 510 may compress 12-bit data (a single Hamming code) into three compressed data signals DQ, and output the three compressed data signals DQ to a corresponding error detecting and correcting unit 530.
Each error detecting and correcting unit 530 may include a transfer data comparator 531, a fail bit controller 551, a comparison signal generator 561, and/or a fail bit detecting and correcting unit 571. The error detecting and correcting unit 530 may count the number of fail bits using ECC and detect the addresses of fail bits. An error correcting range may be controlled by a user by setting a test mode register set (test MRS or TMRS) signal and inputting the test MRS signal to the parallel bit test device. To correct, for example, 1-bit error for a data signal input as a 12-bit Hamming code, the test MRS signal may be set such that a correction control signal D_CON may be output to the parallel bit test device when one fail bit or less is generated. The activation level of the correction control signal D_CON may be set to logic high or logic low. For example, in the example embodiment illustrated in
Each transfer data comparator 531 may respectively compare input data bits CD0 through CD11 to expected data bits ED0 through ED11, and output error comparison signals ECO_i having information indicating whether the input data bits CD0 through CD11 are the same as the expected data bits ED0 through ED11. The data bits CDi may correspond to a signal loaded and transferred on bit lines BLi, and the expected data bits EDi may correspond to the initially input data bits (the data bits prior to being transferred through bit lines). For example, if data 1101 is input to a Memory Chip and is read as 1100 at a receiving side of PBT device (Parallel Bit Test device), 1100 may correspond to the data bits CDi and 1101 may correspond to the expected data bits EDi.
The data bits CDi may be checked against the expected data bits EDi using XOR gates. For example, the transfer data comparator 531 may include m XOR gates when an m-bit data signal is input. An XOR gate may output 0 when signals input thereto are the same as each other and output 1 when the input signals are different from each other. Thus, it may be determined whether the data bits CDi are the same as the expected data bits EDi using XOR gates.
It may be determined that the data bits CDi are the same as the expected data bits EDi when all the error comparison signals ECOi have a value 0, or that the data bits CDi do not correspond to the expected data bits EDi when any of the error comparison signals ECOi has a value 1. If the data bits CDi do not have any fail bits, the data bits CDi may match the expected data bits EDi.
The fail bit controller 551 may count the number of error comparison signals ECOi having a value 1 and determine whether the correction control signal D_CON may be output at a logic high level in response to the test MRS signal applied thereto.
The fail estimator 620 may receive the 4-bit data signal output from the adder 610 and output the correction control signal D_CON in response to the test MRS signal TMRS. As described above, the test MRS signal TMRS may be set and input by a user such that the correction control signal D_CON is output when the counted number of fail bits is less than a given number. For example, the test MRS signal TMRS may be used to set a threshold of the counted number of fail bits needed to output the correction control signal D_CON.
For example, if the user wants to correct fail bits when the number of fail bits is 2 or less, the test MRS signal TMRS may be set such that the correction control signal D_CON at a logic high level is output when the counted value is 2 or less (for example, when the counted number is 0010, 0001 or 0000).
The fail bit detecting and correcting unit 571, which will be described later, may include OR gates such that fail bits may be corrected when the correction control signal D_CON at a logic high level is applied thereto.
The case where the test MRS signal TMSR is set such that fail bit correction is carried out when the number of fail bits is 1 or less will be explained below.
Referring back to
The comparison signal generator 561 may include m/k XNOR gates. For example, because m=12 and k=4 in the example embodiment of
Each fail bit detecting and correcting unit 571 may include m/k OR gates 573, 575 and 577 and perform OR operations on the error correction signal D_CON and the comparison signals SCO_i to generate correction signals COLi. For example, when the data bit CD5 transferred through the bit line BL5 is a fail bit and the other data bits CD0 through CD4 and CD6 through CD11 do not have errors, D_CON1 may be 1, SCO_0 may be 1, SCO_1 may be 0 and SCO_2 may be 1. When the test MRS signal TMRS is set such that fail bit correction may be carried out when the number of fail bits is one or less, each of the three OR gates 573, 575 and 577 may output 1.
Each output unit 580 may correct a fail bit and output the corrected bit when the correction signals COLi at a logic high level are input thereto. Each output unit 580 may output the compressed data DQi when the correction signals COLi at a logic high level are input thereto and the output value of the adder 610 is 0.
Because the parallel bit test device may detect a fail bit but may not correct the fail bit, the output unit 580 may be located outside the parallel bit test device. However, the output unit 580 may be included in the parallel bit test device together with the error detecting and correcting unit 530.
A fail bit may be corrected such that the address of the fail bit is detected using the comparison signals SCO_i and the error comparison signals ECO_i, and the fail bit may be inverted (for example, because when the fail bit is 0 the original data bit may be 1 in the binary system). For example, the compressed data DQi having a fail bit may be detected using the comparison signals SCO_i and replaced with corrected compressed data.
The logic levels of the correction signals COLi may vary according to the logic devices included in the fail bit detecting and correcting unit 571. For example, if the fail bit detecting and correcting unit 571 uses NOR gates, instead of OR gates 573, the correction signals COLi may have a logic low level.
When the correction signals COLi are applied at a logic level that does not activate correction, the compressed data DQi may not be outputted. For example, data may not be transmitted because a fail bit generated in the data may not be corrected. The parallel bit test device according to an example embodiment may not correct a fail bit and may not output the compressed data DQi when the correction signals COLi at a logic low level are applied thereto.
As described above, a parallel bit test device according to example embodiments may include an adder and may set a test MRS signal according to a fail condition set by a user to detect a number of fail bits. Furthermore, the parallel bit test device may detect the position of a fail bit.
Example embodiments having thus been described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the intended spirit and scope of example embodiments, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2006-0096136 | Sep 2006 | KR | national |
