Parallel circuit comprising a plurality of IGBTs

Abstract

In a parallel circuit (10) comprising a plurality of high-power IGBTs (T1, . . . , T3) which are each driven by a dedicated gate drive circuit (GD1, . . . , GD3), each of the gate drive circuits (GD1, . . . , GD3) having, at its output, a p-channel MOSFET (M1, M3, M5) and an n-channel MOSFET (M2, M4, M6) in a push-pull arrangement and the outputs of the gate drive circuits (GD1, . . . , GD3) being connected to the gates of the IGBTs (T1, . . . , T3) in each case via a gate resistor (R1, . . . , R3), a parallel circuit comprising more than two gate drive circuits is made possible by virtue of the fact that the outputs of the gate drive circuits (GD1, . . . , GD3) are interconnected via a connecting line (11), and that the MOSFETs (M1, . . . , M6) of the gate drive circuits (GD1, . . . , GD3) are in each case connected to a positive or negative supply terminal (P1, . . . , P3 or N1, . . . , N3) via a constant-current source (CS1, . . . , CS6).

Description

TECHNICAL FIELD

[0001] The present invention concerns the field of power electronics. It relates to a parallel circuit comprising a plurality of IGBTs in accordance with the preamble of claim 1.

PRIOR ART

[0002] For a relatively long time power electronic semiconductor modules have been commercially available in which up to six high-power IGBTs with corresponding reverse-connected parallel diodes are arranged and interconnected in such a way that they can either form the individual arms of a three-phase power converter bridge or can be combined by being connected in parallel to form a single phase arm with three-fold current-carrying capacity. Modules of this type are offered by the applicant under the general type designation LoPak5 and have, by way of example, a collector-emitter voltage VCE of 1200 V and a collector current IC of 300 A (see the data sheet 5SYA1528 from ABB Semiconductors AG relating to the module type 5SNS0300U120100 of Jul. 1, 2000).

[0003] The parallel circuit comprising such high-power IGBTs on the power side (i.e. by connecting the collector-emitter paths of the individual IGBTs in parallel) throws up various problems:

[0004] If the IGBTs with their associated gate drive circuits (“gate drives”) are only connected in parallel on the power side without further measures, considerable unequal distribution of the currents between the individual IGBTs can occur dynamically due to different delays in the gate drive circuits during the switching of the IGBTs. Since the individual gates of the IGBTs are not connected to one another, the positive transistor behavior of the IGBTs does not help either.

[0005] If the gates of the IGBTs are likewise connected in parallel, the IGBTs, owing to their fundamental transistor behavior, naturally have the tendency to statically divide the currents identically among themselves: identical transistors have identical ICE/VCE characteristics and—since they have the same VCE and the same gate voltage—they must also draw the same collector-emitter current ICE. Dynamically, however, the currents can differ considerably. The absolute values of the gate resistances as well as the ratio of individual and common resistances in the module influence the balance between the currents.

[0006] The output stage of a gate drive circuit used for such IGBTs is usually a push-pull stage constructed with two MOSFETs (p-channel and n-channel MOSFETs). If two gate drive circuits are connected in parallel, it must be ensured that one gate drive circuit does not break down to the other and that one gate drive circuit does not “charge” the other. The simplest solution is to use individual gate resistors for decoupling the gate drive circuits. However, such a solution can only be realized for two gate drive circuits connected in parallel.

SUMMARY OF THE INVENTION

[0007] It is an object of the invention, therefore, to specify a parallel circuit comprising high-power IGBTs in which more than two gate drive circuits are connected in parallel.

[0008] The object is achieved by means of the totality of the features of claim 1. The essence of the invention is that the MOSFETs in the output stages of the gate drive circuits are in each case connected to a positive or negative supply terminal via a constant-current source and the outputs of the gate drive circuits are interconnected via a connecting line. In this case, the constant-current sources are designed as “weak” constant-current sources and are constructed in a manner known per se from a transistor or MOSFET and diodes and/or resistors.

[0009] In order that the power supplies of the gate drive circuits are at least uniformly loaded, it is advantageous if the positive and negative supply terminals of the gate drive circuits are respectively interconnected by connecting lines.

BRIEF EXPLANATION OF THE FIGURES

[0010] The invention will be explained in more detail below using an exemplary embodiment in connection with the drawing. The single FIGURE shows the circuit diagram of a preferred exemplary embodiment of a parallel circuit according to the invention.

WAYS OF EMBODYING THE INVENTION

[0011] The FIGURE illustrates a parallel circuit comprising three IGBTs T1, . . . , T3 in accordance with a preferred exemplary embodiment of the invention. The IGBTs (Insulated Gate Bipolar Transistors) T1, . . . , T3 with their reverse-connected parallel diodes D1, . . . , D3 may, for example, be part of a power semiconductor module, as was mentioned in the introduction, and as is used to form controlled power converter bridges. The IGBTs are connected in parallel on the power side and thus form, for example, an arm of a power converter bridge with three-fold current-carrying capacity. Each of the IGBTs T1, . . . , T3 is driven by an associated gate drive circuit (“gate drive”) GD1, . . . , GD3 via a gate resistor R1, . . . , R3, of which drive circuit only the output stage equipped with MOSFETs M1, . . . , M6 is illustrated, for the sake of simplicity.

[0012] In each of the gate drive circuits GD1, . . . , GD3, a p-channel MOSFET (M1, M3, M5) and an n-channel MOSFET (M2, M4, M6) in a push-pull arrangement are provided in the output stage. Each of the MOSFETs M1, . . . , M6 is connected to a positive or negative supply terminal P1, . . . , P3 or N1, . . . , N3 via an associated constant-current source CS1, . . . , CS6. The constant-current sources CS1, . . . , CS6 are constructed as “weak” constant-current sources from a transistor or MOSFET and diodes and/or resistors.

[0013] The outputs of the gate drive circuits GD1, . . . , GD3, i.e. the junction points between the MOSFET pairs in the output stage, are interconnected via a common first connecting line 11, and are thus connected in parallel. The positive supply terminals P1, . . . , P3 are interconnected by a second connecting line 12 and the negative supply terminals N1, . . . , N3 are interconnected by a third connecting line 13.

[0014] Although the problem of unequal distribution of the loading between the gate drive circuits GD1, . . . , GD3 remains, i.e. the gate drive circuits to be driven first is always subjected to the greatest loading, the loading is limited to a predetermined value by the circuit construction according to the invention. At the same time, the power supplies of the gate drive circuits GD1, . . . , GD3 are uniformly loaded by the connection of the supply terminals P1, . . . , P3 and N1, . . . , N3.

LIST OF REFERENCE SYMBOLS
10               Parallel circuit
11               Connecting line (gate drive circuit)
12, 13           Connecting line (supply terminals)
CS1, . . . , CS6 Constant-current source
D1, . . . , D3   Diode
GD1, . . . , GD3 Gate drive circuit (gate drive)
M1, . . . , M6   MOSFET transistor
N1, . . . , N3   Negative supply terminal
P1, . . . , P3   Positive supply terminal
R1, . . . , R3   Gate resistor
T1, . . . , T3   IGBT

Claims

1. A parallel circuit (10) comprising a plurality of high-power IGBTs (T1, . . . , T3) which are each driven by a dedicated gate drive circuit (GD1, . . . , GD3), each of the gate drive circuits (GD1, . . . , GD3) having, at its output, a p-channel MOSFET (M1, . . . M3, M5) and an n-channel MOSFET (M2, M4, M6) in a push-pull arrangement and the outputs of the gate drive circuits (GD1, . . . , GD3) being connected to the gates of the IGBTs (T1, . . . , T3) in each case via a gate resistor (R1, . . . , R3), characterized in that the outputs of the gate drive circuits (GD1, . . . , GD3) are interconnected via a connecting line (11), and in that the MOSFETs (M1, . . . , M6) of the gate drive circuits (GD1, . . . , GD3) are in each case connected to a positive or negative supply terminal (P1, . . . , P3 or N1, . . . , N3) via a constant-current source (CS1, . . . , CS6).

2. The parallel circuit as claimed in claim 1, characterized in that the constant-current sources (CS1, . . . , CS6) are constructed from a transistor or MOSFET and diodes and/or resistors.

3. The parallel circuit as claimed in either of claims 1 and 2, characterized in that the positive and negative supply terminals (P1, . . . , P3 and N, . . . , N3) of the gate drive circuits (GD1, . . . , GD3) are respectively interconnected by connecting lines (12 and 13).