Patent Application
20250007417
The present invention relates to parallel connected power converters and more particularly to parallel connected flyback converters using push-pull feedback networks.
Many electronic devices, such as cell phones, laptops, etc., are powered by direct current (dc) power derived from a power supply. Conventional wall outlets generally deliver a high voltage alternating current (ac) power that needs to be converted to regulated dc power in order to be used as a power source for consumer electronic devices. Switch mode power converters, also referred to as switch mode power supplies (SMPSs), are commonly used due to their high efficiency, small size, and low weight.
Non-limiting and non-exhaustive embodiments of parallel connected power converters using push-pull feedback networks are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the teachings herein. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of parallel connected power converters using push-pull feedback networks.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of parallel connected power converters using push-pull feedback networks. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present disclosure.
Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of a (multiple output) switch-mode power converter system. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.
In the context of the present application, when a transistor is in an “off-state” or “off” the transistor blocks current and/or does not substantially conduct current. Conversely, when a transistor is in an “on-state” or “on” the transistor is able to substantially conduct current. By way of example, in one embodiment, a high-voltage transistor comprises an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) with the high-voltage being supported between the first terminal, a drain, and the second terminal, a source. In some embodiments an integrated controller circuit may be used to drive a power switch when regulating energy provided to a load. Also, for purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential against which all other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured. Additionally, according to power electronics theory (i.e., power is related to the rate of change of energy), “power” transfer may be implied by “energy” transfer; conversely, “energy” transfer may be implied by “power” transfer.
Often power converters (i.e., power supplies) are specified and/or rated to provide a maximum output power at a specified output voltage. Such a rating or specification limits the maximum current a power converter may deliver to a load.
However, a problem arises in applications where the output power and corresponding load current exceed the maximum output power rating of the power converter; therefore, there is need to find a way to increase the available output power beyond the power converters specified maximum. In theory, connecting power converters in parallel may avail a load-sharing solution.
Unfortunately, in practice power converters may not readily be connected in parallel due to practical and design-related limitations. Often power converters are not designed to be connected in parallel and circuitry for enhancing performance may interfere with a parallel load-sharing configuration. Accordingly, there is a need to find a load-sharing solution to connecting power converters in parallel.
Parallel connected power converters using push-pull feedback networks are described herein. The power converters may be switch-mode (switching) power converters (SMPSs) controlled by load dependent signals such that switching frequency increases as a function of load. The load dependent signals (i.e., controller signals) may drive the push-pull feedback networks to adjust the voltage regulation feedback signals and to equalize the output current (i.e., output power) from the parallel-connected power converters.
Although the embodiment of
The load 142 is connected between the output node NVo and secondary ground and demands an output power determined by the regulated output voltage Vo and load (output) current IL. Power converter 100a and power converter 100b are connected in parallel between the output node NVo and the secondary ground RTN. As such, power converter 100a and power converter 100b may share the load (i.e., the total load current IL).
As illustrated, power converter 100a provides an output current IL1 and power converter 100b provides an output current IL2 to the load. According to circuit theory, the total load current IL may equal the sum of output currents IL1, IL2 such that the power converter 100a-100b share the total output power (i.e., output voltage Vo times load current IL).
Also as illustrated, power converter 100a and power converter 100b have a flyback configuration. Power converter 100a includes an energy transfer element 102a (e.g., a transformer), a secondary diode D1, controller circuit 107a, and a primary switch 152a. The energy transfer element 102a comprises a primary winding 112a and a secondary winding 99a. The primary switch 152a is electrically coupled to the primary winding 112a; energy (i.e., power) may be transferred to the secondary winding 99a according to a switching cycle of primary switch 152a.
For instance, the controller circuit 107a may provide a gate signal VCS1 to turn primary switch 152a on and off. According to switch mode power supply (SMPS) theory, the gate signal VCS1 may transition (i.e., may vary) according to switching waveform 191a; in turn, a primary current ISW1 energizes primary winding 112a according to switching waveform 192a. As illustrated, both switching waveforms 191a-192a switch according to a switching cycle of period TSW1.
Also, according to SMPS theory, the controller circuit 107a may, in response to a feedback signal FB1, adjust the switching cycle (i.e., the period TSW1) so that the power is delivered to the load 142 with regulated output voltage Vo. For instance, as the load demand increases, the feedback signal FB1 may droop; and in response, the controller circuit 107a may increase and/or adjust the frequency of gate signal VCS1.
Similarly, power converter 100b includes an energy transfer element 102b (e.g., a transformer), a secondary diode D2, controller circuit 107b, and a primary switch 152b. The energy transfer element 102b comprises a primary winding 112b and a secondary winding 99b. The primary switch 152b is electrically coupled to the primary winding 112b; energy (i.e., power) may be transferred to the secondary winding 99b according to a switching cycle of primary switch 152b.
For instance, the controller circuit 107b may provide a gate signal VCS2 to turn primary switch 152b on and off. According to switch mode power supply (SMPS) theory the gate signal VCS2 may transition (i.e., may vary) according to switching waveform 191b; in turn, a primary current ISW2 energizes primary winding 112b according to switching waveform 192b. As illustrated, both switching waveforms 191b-192b switch according to a switching cycle of period TSW2.
Also, according to SMPS theory, the controller circuit 107b may, in response to a feedback signal FB2, adjust the switching cycle (i.e., the period TSW2) so that the power is delivered to the load 142 with regulated output voltage Vo. For instance, as the load demand increases, the feedback signal FB2 may droop; and in response, the controller circuit 107b may increase and/or adjust the frequency of gate signal VCS2.
According to the teachings herein, power converter 100a may include a push-pull feedback network 140a and power converter 100b may include a push-pull feedback network 140b. As illustrated, push-pull feedback network 140a and push-pull feedback network 140b may receive a control signal VCR1 from controller circuit 107a and a control signal VCR2 from controller circuit 107b. Control signals VCR1 and VCR2 may vary with load demand (i.e., the load current Io). For instance, control signal VCR1 may transition according to a switching waveform 193a of period TSW1; and the corresponding switching frequency, as related to the reciprocal of period TSW1, may be a monotonically increasing function of the load demand. Similarly, control signal VCR2 may transition according to a switching waveform 193b of period TSW2; and the corresponding switching frequency, as related to the reciprocal of period TSW2, may be a monotonically increasing function of the load demand.
Power converter 100a includes a primary clamp 110a, an output capacitor C1, a primary current sense element 54a, and a resistor RW1. Additionally, an N-type field effect transistor (NFET) 126a replaces diode D1 and may operate as a synchronous rectifier (SR). Accordingly, NFET 126a may also be referred to as a synchronous rectifier 126a without departing from the scope of the present disclosure.
The controller circuit 107a includes a secondary controller 108a and a primary controller 109a. The primary controller 109a is referenced to ground GND and may receive a current sense signal SENS1 from the primary current sense element 54a. In one application, the primary controller 109a may turn off the primary switch 152a when the primary current ISW1 exceeds a current limit (e.g., ten amperes). Alternatively, and additionally, the primary controller 109a may turn on the primary switch 152a in response to a request signal FL1 from the secondary controller 108a.
The secondary controller 108a is referenced to secondary ground RTN. As illustrated, the secondary controller 108a receives a forward signal FW1 from a forward node 123a via resistor RW1. Additionally, the secondary controller 108a may provide control signal VCR1 and receive feedback signal FB1. In response to the feedback signal FB1, the secondary controller may send a request signal FL1 to the primary controller 109a when there is a demand for more output current IL1.
Similarly, power converter 100b includes a primary clamp 110b, an output capacitor C2, a primary current sense element 54b, and a resistor RW2. Additionally, an N-type field effect transistor (NFET) 126b replaces diode D2 and may operate as a synchronous rectifier (SR). Accordingly, NFET 126b may also be referred to as a synchronous rectifier 126b without departing from the scope of the present disclosure.
The controller circuit 107b includes a secondary controller 108b and a primary controller 109b. The primary controller 109b is referenced to ground GND and may receive a current sense signal SENS2 from the primary current sense element 54b. In one application, the primary controller 109b may turn off the primary switch 152b when the primary current ISW2 exceeds a current limit (e.g., ten amperes). Alternatively, and additionally, the primary controller 109b may turn on the primary switch 152b in response to a request signal FL2 from the secondary controller 108a.
The secondary controller 108b is referenced to secondary ground RTN. As illustrated, the secondary controller 108b receives a forward signal FW2 from a forward node 123b via resistor RW2. Additionally, the secondary controller 108b may provide control signal VCR2 and receive feedback signal FB2. In response to the feedback signal FB2, the secondary controller may send a request signal FL2 to the primary controller 109b when there is a demand for more output current IL2.
Additionally, power converters 100a-b may be of the same type and have matched components and/or similar configurations. For instance, primary clamps 110a-b, output capacitors C1-C2, primary current sense elements 54a-b, and/or resistors RW1-RW2 may have the same values and/or characteristics. Alternatively, and additionally, the controller circuits 107a-b may be of the same type and have matched and/or similar configurations. For instance, controller circuit 107a may be the same type and have the same datasheet as controller circuit 107b.
According to the teachings herein, the push-pull feedback networks 140a-b may receive control signals VCR1, VCR2. The switching frequency of control signal VCR1 may be a monotonically increasing function of output power relating to output current IL1; and the switching frequency of control signal VCR2 may be a monotonically increasing function of output power relating to output current IL2.
As discussed below with regards to
As illustrated, auxiliary resistor RX1 is electrically coupled between node NP1 and feedback node NFB1, and capacitor CP1 is electrically coupled between node NP1 and secondary ground RTN. Additionally, path resistor RSR1 is electrically coupled between node NP1 and the cathode of diode DP1; and path resistor RSN1 is electrically coupled between node NP1 and the drain of NFET MN1.
Also, as illustrated, the anode of diode DP1 receives control signal VCR1. Accordingly, the feedback signal FB1 may also be dependent, at least in part, on control signal VCR1 and on auxiliary resistor RX1, path resistor RSR1, and capacitor CP1. Additionally, the feedback signal FB1 may depend, at least in part, on the switching frequency and amplitude of control signal VCR1. (e.g., switching waveform 193a).
As illustrated, the source of NFET MN1 is electrically coupled to secondary ground RTN, and the gate of NFET MN1 receives control signal VCR2. As such, the NFET MN1 may pull node NP1 to the secondary ground RTN when control signal VCR2 causes NFET MN1 to conduct. Thus, the feedback signal FB1 may also depend, at least in part, on the path resistor RSN1, the switching frequency and the amplitude of control signal VCR2. (e.g., switching waveform 193b).
According to the teachings herein, the dependence of the feedback signal FB1 on control signals VCR1 and VCR2 may be such that the output current IL1 is adjusted to be substantially equal to that of output current IL2. Accordingly, the control signals VCR1 and VCR2 may be such that the power delivered by power converter 100a, is adjusted to be substantially equal to the power delivered by power converter 100b.
As illustrated, auxiliary resistor RX2 is electrically coupled between node NP2 and feedback node NFB2, and capacitor CP2 is electrically coupled between node NP2 and secondary ground RTN. Additionally, path resistor RSR2 is electrically coupled between node NP2 and the cathode of diode DP2; and path resistor RSN2 is electrically coupled between node NP2 and the drain of NFET MN2.
Also, as illustrated the anode of diode DP2 receives control signal VCR2. Accordingly, the feedback signal FB2 may also be a voltage dependent, at least in part, on control signal VCR2 and on auxiliary resistor RX2, path resistor RSR2, and capacitor CP2. Additionally, the feedback signal FB2 may depend, at least in part, on the switching frequency and amplitude of control signal VCR2. (e.g., switching waveform 193b).
As illustrated, the source of NFET MN2 is electrically coupled to secondary ground RTN, and the gate of NFET MN2 receives control signal VCR1. As such, the NFET MN2 may pull node NP2 to the secondary ground RTN when control signal VCR1 causes NFET MN2 to conduct. Thus, the feedback signal FB2 may also depend, at least in part, on the path resistor RSN2, the switching frequency and the amplitude of control signal VCR1. (e.g., switching waveform 193a).
According to the teachings herein, the dependence of the feedback signal FB1 on control signals VCR1 and VCR2 may be such that the output current IL2 is adjusted to be substantially equal to that of output current IL1. Accordingly, the control signals VCR1 and VCR2 may be such that the power delivered by power converter 100b, is adjusted to be substantially equal to the power delivered by power converter 100a.
As illustrated, feedback network 140a may receive the output voltage Vo, control signal VCR1, and control signal VCR2, and may provide the feedback signal FB1. Therefore, in accordance with circuit theory, the feedback signal FB1 may depend on output voltage Vo, control signal VCR1, and control signal VCR2. A direct current (DC) analysis with control signals VCR1, VCR2 set to the secondary ground potential, relates the feedback signal FB1 to the output voltage Vo as a function of a divider ration of divider resistors RA1, RB1.
According to the teachings herein, the control signals VCR1, VCR2 may, by virtue of their alternating current (AC) switching behavior, adjust the feedback signal FB1 so that the output power and corresponding output current (i.e., the output current IL1) of power converter 100a may be shared equally, or approximately shared equally, with the output power and corresponding output current (i.e., the output current IL2) of power converter 100b.
As illustrated, control signal VCR1, by virtue of its electrical connection at the anode of diode DP1 and its characteristic switching behavior (e.g., waveform 193a), may vary the feedback signal FB1. For instance, the control signal VCR1 may push the feedback signal FB1 higher with increasing frequency (i.e., with decreasing period TSW1). In this regard, as provided to feedback network 140a, the control signal VCR1 may function as a push signal VCR1. Accordingly, with regards to feedback network 140a, the control signal VCR1 may also be referred to as a push signal VCR1 without departing from the scope of the present disclosure.
Alternatively, and additionally, the control signal VCR2, by virtue of its electrical connection to the gate of NFET MN1 and its characteristic switching behavior (e.g., waveform 193b), may also vary the feedback signal FB1. For instance, the control signal VCR2 may cause NFET MN1 to pull the feedback signal FB1 lower with increasing frequency (i.e., with decreasing period TSW2). In this regard, as provided to feedback network 140a, the control signal VCR2 may function as a pull signal VCR2. Accordingly, with regards to feedback network 140a, the control signal VCR2 may also be referred to as a pull signal VCR2 without departing from the scope of the present disclosure.
Similarly, as illustrated, feedback network 140b may receive the output voltage Vo, control signal VCR2, and control signal VCR1, and may provide the feedback signal FB2. Therefore, in accordance with circuit theory, the feedback signal FB2 may depend on output voltage Vo, control signal VCR1, and control signal VCR2. A direct current (DC) analysis with control signals VCR1, VCR2 set to the secondary ground potential, relates the feedback signal FB2 to the output voltage Vo as a function of a divider ration of divider resistors RA2, RB2.
According to the teachings herein, the control signals VCR1, VCR2 may, by virtue of their alternating current (AC) switching behavior, adjust the feedback signal FB2 so that the output power and corresponding output current (i.e., the output current IL2) of power converter 100b may be shared equally, or approximately shared equally, with the output power and corresponding output current (i.e., the output current IL1) of power converter 100a.
As illustrated, control signal VCR2, by virtue of its electrical connection at the anode of diode DP2 and its characteristic switching behavior (e.g., waveform 193b), may vary the feedback signal FB2. For instance, the control signal VCR2 may push the feedback signal FB2 higher with increasing frequency (i.e., with decreasing period TSW2). In this regard, as provided to feedback network 140b, the control signal VCR2 may function as a push signal VCR2. Accordingly, with regards to feedback network 140b, the control signal VCR2 may also be referred to as a push signal VCR2 without departing from the scope of the present disclosure.
Alternatively, and additionally, the control signal VCR1, by virtue of its electrical connection to the gate of NFET MN2 and its characteristic switching behavior (e.g., waveform 193a), may also vary the feedback signal FB2. For instance, the control signal VCR2 may cause NFET MN2 to pull the feedback signal FB2 lower with increasing frequency (i.e., with decreasing period TSW1). In this regard, as provided to feedback network 140b, the control signal VCR1 may function as a pull signal VCR1. Accordingly, with regards to feedback network 140a, the control signal VCR1 may also be referred to as a pull signal VCR1 without departing from the scope of the present disclosure.
Step 502 may correspond with using a second power converter (e.g., power converter 100b). The second power may correspond with an output power relating to an output current (e.g., output current IL2). The first power may be transferred based on the frequency of a gate signal (e.g., gate signal VCS2).
Step 503 may correspond with providing a first control signal (e.g., control signal VCR1) at a first switching frequency (see, e.g., waveform 193a). The first control signal may be applied to a first push-pull feedback network (e.g., push-pull feedback network 140a).
Step 504 may correspond with providing a second control signal (e.g., control signal VCR2) at a second switching frequency (see, e.g., waveform 193b). The second control signal may also be applied to the first push-pull feedback network (e.g., push-pull feedback network 140a).
Step 505 may correspond with providing a first feedback signal (e.g., feedback signal FB1) in response to the first and second control signals.
Step 506 may correspond with load sharing. Namely, in response to the first feedback (e.g., feedback signal FB1), the first power may be substantially equal to the second power.
In one example, a power converter system (e.g., system 50) comprises a first power converter (e.g., power converter 100a), a second power converter (e.g., power converter 100b), and a first push-pull feedback network (e.g., push-pull feedback network 140a).
The first power converter comprises a first controller circuit (e.g., controller circuit 107a). The first controller circuit is configured to drive a first switch (e.g., primary switch 152a) according to a first switching frequency (see, e.g., waveforms 191a, 192a in
The second power converter comprises a second controller circuit (e.g., controller circuit 107b). The second controller circuit is configured to drive a second switch (e.g., primary switch 152b) according to a second switching frequency (see, e.g., waveforms 191b, 192b in
The first push-pull feedback network is configured to receive a first push signal (e.g., control signal VCR2) at the second switching frequency and a first pull signal (control signal VCR1) at the first switching frequency. In response, the first push-pull feedback network provides the first feedback signal (e.g., feedback signal FB1) to the first controller circuit such that the first power is substantially equal to the second power.
In another example the power converter system comprises a second push pull feedback network (e.g., push-pull feedback network 140b.
The second push-pull feedback network is configured to receive a second push signal (e.g., control signal VCR1) at the first switching frequency and a second pull signal (control signal VCR2) at the second switching frequency. In response, the second push-pull feedback network provides the second feedback signal (e.g., feedback signal FB2) to the second controller circuit such that the second power is substantially equal to the first power.
Although the embodiments of
For instance,
The above description of illustrated examples of the present disclosure, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of and examples for parallel connected power converters using push-pull feedback networks are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings herein.
The foregoing description may refer to elements or features as being “connected,” “electrically connected,” and/or “coupled” together. As used herein, unless expressly stated otherwise, “electrically connected” and/or “connected” mean that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “electrically coupled” and/or “coupled” mean that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).
Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding whether these features, elements and/or states are included or are to be performed in any particular embodiment.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and/or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.
Although the claims presented here are in single dependency format for filing at the USPTO, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.
This application claims priority from U.S. Provisional Application No. 63/511,287 filed on Jun. 30, 2023, hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63511287 | Jun 2023 | US |
