Patent Application
20220222397
A datacenter may include one or more platforms each including at least one processor and associated memory modules. Each platform of the datacenter may facilitate the performance of any suitable number of processes associated with various applications running on the platform. These processes may be performed by the processors and other associated logic of the platforms. Each platform may additionally include I/O controllers, such as network adapter devices, which may be used to send and receive data on a network for use by the various applications.
Like reference numbers and designations in the various drawings indicate like elements.
Each platform 102 may include platform logic 110. Platform logic 110 includes, among other logic enabling the functionality of platform 102, one or more CPUs 112, memory 114, one or more chipsets 116, and communication interface 118. Although three platforms are illustrated, datacenter 100 may include any suitable number of platforms. In various embodiments, a platform 102 may reside on a circuit board that is installed in a chassis, rack, compossible servers, disaggregated servers, or other suitable structures that includes multiple platforms coupled together through network 108 (which may include, e.g., a rack or backplane switch).
CPUs 112 may each include any suitable number of processor cores. The cores may be coupled to each other, to memory 114, to at least one chipset 116, and/or to communication interface 118, through one or more controllers residing on CPU 112 and/or chipset 116. In particular embodiments, a CPU 112 is embodied within a socket that is permanently or removably coupled to platform 102. CPU 112 is described in further detail below in connection with
Memory 114 may include any form of volatile or non-volatile memory including, without limitation, magnetic media (e.g., one or more tape drives), optical media, random access memory (RAM), read-only memory (ROM), flash memory, removable media, or any other suitable local or remote memory component or components. Memory 114 may be used for short, medium, and/or long-term storage by platform 102. Memory 114 may store any suitable data or information utilized by platform logic 110, including software embedded in a computer readable medium, and/or encoded logic incorporated in hardware or otherwise stored (e.g., firmware). Memory 114 may store data that is used by cores of CPUs 112. In some embodiments, memory 114 may also include storage for instructions that may be executed by the cores of CPUs 112 or other processing elements (e.g., logic resident on chipsets 116) to provide functionality associated with components of platform logic 110. Additionally or alternatively, chipsets 116 may each include memory that may have any of the characteristics described herein with respect to memory 114. Memory 114 may also store the results and/or intermediate results of the various calculations and determinations performed by CPUs 112 or processing elements on chipsets 116. In various embodiments, memory 114 may include one or more modules of system memory coupled to the CPUs through memory controllers (which may be external to or integrated with CPUs 112). In various embodiments, one or more particular modules of memory 114 may be dedicated to a particular CPU 112 or other processing device or may be shared across multiple CPUs 112 or other processing devices.
A platform 102 may also include one or more chipsets 116 including any suitable logic to support the operation of the CPUs 112. In some cases, chipsets 116 may be implementations of graph processing devices, such as discussed herein. In various embodiments, chipset 116 may reside on the same package as a CPU 112 or on one or more different packages. Each chipset may support any suitable number of CPUs 112. A chipset 116 may also include one or more controllers to couple other components of platform logic 110 (e.g., communication interface 118 or memory 114) to one or more CPUs. Additionally or alternatively, the CPUs 112 may include integrated controllers. For example, communication interface 118 could be coupled directly to CPUs 112 via one or more integrated I/O controllers resident on each CPU.
Chipsets 116 may each include one or more communication interfaces 128 (e.g., 128A, 128B). Communication interface 128 may be used for the communication of signaling and/or data between chipset 116 and one or more I/O devices, one or more networks 108, and/or one or more devices coupled to network 108 (e.g., datacenter management platform 106 or data analytics engine 104). For example, communication interface 128 may be used to send and receive network traffic such as data packets. In a particular embodiment, communication interface 128 may be implemented through one or more I/O controllers, such as one or more physical network interface controllers (NICs), also known as network interface cards or network adapters. An I/O controller may include electronic circuitry to communicate using any suitable physical layer and data link layer standard such as Ethernet (e.g., as defined by an IEEE 802.3 standard), Fibre Channel, InfiniBand, Wi-Fi, or other suitable standard. An I/O controller may include one or more physical ports that may couple to a cable (e.g., an Ethernet cable). An I/O controller may enable communication between any suitable element of chipset 116 (e.g., switch 130 (e.g., 130A, 130B)) and another device coupled to network 108. In some embodiments, network 108 may include a switch with bridging and/or routing functions that is external to the platform 102 and operable to couple various I/O controllers (e.g., NICs) distributed throughout the datacenter 100 (e.g., on different platforms) to each other. In various embodiments an I/O controller may be integrated with the chipset (i.e., may be on the same integrated circuit or circuit board as the rest of the chipset logic) or may be on a different integrated circuit or circuit board that is electromechanically coupled to the chipset. In some embodiments, communication interface 128 may also allow I/O devices integrated with or external to the platform (e.g., disk drives, other NICs, etc.) to communicate with the CPU cores.
Switch 130 may couple to various ports (e.g., provided by NICs) of communication interface 128 and may switch data between these ports and various components of chipset 116 according to one or more link or interconnect protocols, such as Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), HyperTransport, GenZ, OpenCAPI, and others, which may each alternatively or collectively apply the general principles and/or specific features discussed herein. Switch 130 may be a physical or virtual (i.e., software) switch.
Platform logic 110 may include an additional communication interface 118. Similar to communication interface 128, this additional communication interface 118 may be used for the communication of signaling and/or data between platform logic 110 and one or more networks 108 and one or more devices coupled to the network 108. For example, communication interface 118 may be used to send and receive network traffic such as data packets. In a particular embodiment, communication interface 118 includes one or more physical I/O controllers (e.g., NICs). These NICs may enable communication between any suitable element of platform logic 110 (e.g., CPUs 112) and another device coupled to network 108 (e.g., elements of other platforms or remote nodes coupled to network 108 through one or more networks). In particular embodiments, communication interface 118 may allow devices external to the platform (e.g., disk drives, other NICs, etc.) to communicate with the CPU cores. In various embodiments, NICs of communication interface 118 may be coupled to the CPUs through I/O controllers (which may be external to or integrated with CPUs 112). Further, as discussed herein, I/O controllers may include a power manager 125 to implement power consumption management functionality at the I/O controller (e.g., by automatically implementing power savings at one or more interfaces of the communication interface 118 (e.g., a PCIe interface coupling a NIC to another element of the system), among other example features.
Platform logic 110 may receive and perform any suitable types of processing requests. A processing request may include any request to utilize one or more resources of platform logic 110, such as one or more cores or associated logic. For example, a processing request may include a processor core interrupt; a request to instantiate a software component, such as an I/O device driver 124 or virtual machine 132 (e.g., 132A, 132B); a request to process a network packet received from a virtual machine 132 or device external to platform 102 (such as a network node coupled to network 108); a request to execute a workload (e.g., process or thread) associated with a virtual machine 132, application running on platform 102, hypervisor 120 or other operating system running on platform 102; or other suitable request.
In various embodiments, processing requests may be associated with guest systems 122. A guest system may include a single virtual machine (e.g., virtual machine 132A or 132B) or multiple virtual machines operating together (e.g., a virtual network function (VNF) 134 or a service function chain (SFC) 136). As depicted, various embodiments may include a variety of types of guest systems 122 present on the same platform 102.
A virtual machine 132 may emulate a computer system with its own dedicated hardware. A virtual machine 132 may run a guest operating system on top of the hypervisor 120. The components of platform logic 110 (e.g., CPUs 112, memory 114, chipset 116, and communication interface 118) may be virtualized such that it appears to the guest operating system that the virtual machine 132 has its own dedicated components.
A virtual machine 132 may include a virtualized NIC (vNIC), which is used by the virtual machine as its network interface. A vNIC may be assigned a media access control (MAC) address, thus allowing multiple virtual machines 132 to be individually addressable in a network.
In some embodiments, a virtual machine 132B may be paravirtualized. For example, the virtual machine 132B may include augmented drivers (e.g., drivers that provide higher performance or have higher bandwidth interfaces to underlying resources or capabilities provided by the hypervisor 120). For example, an augmented driver may have a faster interface to underlying virtual switch 138 for higher network performance as compared to default drivers.
VNF 134 may include a software implementation of a functional building block with defined interfaces and behavior that can be deployed in a virtualized infrastructure. In particular embodiments, a VNF 134 may include one or more virtual machines 132 that collectively provide specific functionalities (e.g., wide area network (WAN) optimization, virtual private network (VPN) termination, firewall operations, load-balancing operations, security functions, etc.). A VNF 134 running on platform logic 110 may provide the same functionality as traditional network components implemented through dedicated hardware. For example, a VNF 134 may include components to perform any suitable NFV workloads, such as virtualized Evolved Packet Core (vEPC) components, Mobility Management Entities, 3rd Generation Partnership Project (3GPP) control and data plane components, etc.
SFC 136 is group of VNFs 134 organized as a chain to perform a series of operations, such as network packet processing operations. Service function chaining 136 may provide the ability to define an ordered list of network services (e.g. firewalls, load balancers) that are stitched together in the network to create a service chain.
A hypervisor 120 (also known as a virtual machine monitor) may include logic to create and run guest systems 122. The hypervisor 120 may present guest operating systems run by virtual machines with a virtual operating platform (i.e., it appears to the virtual machines that they are running on separate physical nodes when they are actually consolidated onto a single hardware platform) and manage the execution of the guest operating systems by platform logic 110. Services of hypervisor 120 may be provided by virtualizing in software or through hardware assisted resources that require minimal software intervention, or both. Multiple instances of a variety of guest operating systems may be managed by the hypervisor 120. Each platform 102 may have a separate instantiation of a hypervisor 120.
Hypervisor 120 may be a native or bare-metal hypervisor that runs directly on platform logic 110 to control the platform logic and manage the guest operating systems. Alternatively, hypervisor 120 may be a hosted hypervisor that runs on a host operating system and abstracts the guest operating systems from the host operating system. Various embodiments may include one or more non-virtualized platforms 102, in which case any suitable characteristics or functions of hypervisor 120 described herein may apply to an operating system of the non-virtualized platform.
Hypervisor 120 may include a virtual switch 138 that may provide virtual switching and/or routing functions to virtual machines of guest systems 122. The virtual switch 138 may include a logical switching fabric that couples the vNICs of the virtual machines 132 to each other, thus creating a virtual network through which virtual machines may communicate with each other. Virtual switch 138 may also be coupled to one or more networks (e.g., network 108) via physical NICs of communication interface 118 so as to allow communication between virtual machines 132 and one or more network nodes external to platform 102 (e.g., a virtual machine running on a different platform 102 or a node that is coupled to platform 102 through the Internet or other network). Virtual switch 138 may include a software element that is executed using components of platform logic 110. In various embodiments, hypervisor 120 may be in communication with any suitable entity (e.g., a SDN controller) which may cause hypervisor 120 to reconfigure the parameters of virtual switch 138 in response to changing conditions in platform 102 (e.g., the addition or deletion of virtual machines 132 or identification of optimizations that may be made to enhance performance of the platform).
Hypervisor 120 may include any suitable number of I/O device drivers 124. I/O device driver 124 represents one or more software components that allow the hypervisor 120 to communicate with a physical I/O device. In various embodiments, the underlying physical I/O device may be coupled to any of CPUs 112 and may send data to CPUs 112 and receive data from CPUs 112. The underlying I/O device may utilize any suitable communication protocol, such as PCI, PCIe, Universal Serial Bus (USB), Serial Attached SCSI (SAS), Serial ATA (SATA), InfiniBand, Fibre Channel, an IEEE 802.3 protocol, an IEEE 802.11 protocol, or other current or future signaling protocol.
The underlying I/O device may include one or more ports operable to communicate with cores of the CPUs 112. In one example, the underlying I/O device is a physical NIC or physical switch. For example, in one embodiment, the underlying I/O device of I/O device driver 124 is a NIC of communication interface 118 having multiple ports (e.g., Ethernet ports).
In other embodiments, underlying I/O devices may include any suitable device capable of transferring data to and receiving data from CPUs 112, such as an audio/video (A/V) device controller (e.g., a graphics accelerator or audio controller); a data storage device controller, such as a flash memory device, magnetic storage disk, or optical storage disk controller; a wireless transceiver; a network processor; or a controller for another input device such as a monitor, printer, mouse, keyboard, or scanner; or other suitable device.
In various embodiments, when a processing request is received, the I/O device driver 124 or the underlying I/O device may send an interrupt (such as a message signaled interrupt) to any of the cores of the platform logic 110. For example, the I/O device driver 124 may send an interrupt to a core that is selected to perform an operation (e.g., on behalf of a virtual machine 132 or a process of an application). Before the interrupt is delivered to the core, incoming data (e.g., network packets) destined for the core might be cached at the underlying I/O device and/or an I/O block associated with the CPU 112 of the core. In some embodiments, the I/O device driver 124 may configure the underlying I/O device with instructions regarding where to send interrupts.
In some embodiments, as workloads are distributed among the cores, the hypervisor 120 may steer a greater number of workloads to the higher performing cores than the lower performing cores. In certain instances, cores that are exhibiting problems such as overheating or heavy loads may be given less tasks than other cores or avoided altogether (at least temporarily). Workloads associated with applications, services, containers, and/or virtual machines 132 can be balanced across cores using network load and traffic patterns rather than just CPU and memory utilization metrics.
The elements of platform logic 110 may be coupled together in any suitable manner. For example, a bus may couple any of the components together. A bus may include any known interconnect, such as a multi-drop bus, a mesh interconnect, a ring interconnect, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, or a Gunning transceiver logic (GTL) bus.
Elements of the data system 100 may be coupled together in any suitable, manner such as through one or more networks 108. A network 108 may be any suitable network or combination of one or more networks operating using one or more suitable networking protocols. A network may represent a series of nodes, points, and interconnected communication paths for receiving and transmitting packets of information that propagate through a communication system. For example, a network may include one or more firewalls, routers, switches, security appliances, antivirus servers, or other useful network devices. A network offers communicative interfaces between sources and/or hosts, and may include any local area network (LAN), wireless local area network (WLAN), metropolitan area network (MAN), Intranet, Extranet, Internet, wide area network (WAN), virtual private network (VPN), cellular network, or any other appropriate architecture or system that facilitates communications in a network environment. A network can include any number of hardware or software elements coupled to (and in communication with) each other through a communications medium. In various embodiments, guest systems 122 may communicate with nodes that are external to the datacenter 100 through network 108.
Current practices in data analytics and artificial intelligence perform tasks such as object classification on unending streams of data. Computing infrastructure for classification is predominantly oriented toward “dense” compute, such as matrix computations. The continuing exponential growth in generated data has shifted some compute to be offloaded to GPUs and other application-focused accelerators across multiple domains that are dense-compute dominated. However, the next step in the evolution in both artificial intelligence (AI), machine learning, and data analytics is reasoning about the relationships between these classified objects. In some implementations, a graph structure (or data structure) may be defined and utilized to define relationships between classified objects. For instance, determining the relationships between entities in a graph is the basis of graph analytics. Graph analytics poses important challenges on existing processor architectures due to its sparse structure.
High-performance large scale graph analytics is essential to timely analyze relationships in big data sets. The combination of low performance and very large graph sizes has traditionally limited the usability of graph analytics. Indeed, conventional processor architectures suffer from inefficient resource usage and bad scaling on graph workloads. Recognizing both the increasing importance of graph analytics and the need for vastly improved sparse computation performance compared to traditional approaches, an improved system architecture is presented herein that is adapted to performing high-performance graph processing by addressing constraints across the network, memory, and compute architectures that typically limit performance on graph workloads.
In the example of
In one example, respective MTC (e.g., 215a-d) may support sixteen threads with only minimal interrupt handling. For instance, each thread in an MTC may execute a portion of a respective instruction, with the MTC switching between the active threads automatically or opportunistically (e.g., switch from executing one thread to the next in response to a load operation by the first thread so as to effectively hide the latency of the load operation (allowing the other thread or threads to operate during the cycles needed for the load operation to complete), among other examples). An MTC thread may be required to finishing executing its respective instruction before taking on another. In some implementations, the MTCs may adopt a barrel model, among other features or designs. STC's may execute a single thread at a time and may support full interrupt handling. Portions of a workload handled by a graph processing core 205 may be divided not only between the MTCs (e.g., with sixteen threads per MTC), but also between the MTCs 215a-d and STCs 220a-b. For instance, STCs 220a-b may be optimized for various types of operations (e.g., load-store forwarding, branch predictions, etc.) and programs may make use of STCs for some operations and the multithreading capabilities of the MTCs for other instructions.
An example graph processing core 205 may include additional circuitry to implement components such as a scratchpad 245, uncore, and memory controller (e.g., 250). Components of the graph processing core 205 may be interconnected via a crossbar interconnect (e.g., a full crossbar 255) that ties all components in the graph processing core 205 together in a low latency, high bandwidth network. The memory controller 250 may be implemented as a narrow channel memory controller, for instance, supporting a narrow, fixed 8-byte memory channel. Data pulled using the memory controller from memory in the system may be loaded into a scratchpad memory region 245 for use by other components of the graph processing core 205. In one example, the scratchpad may provide 2 MB of scratchpad memory per core (e.g., MTC and STC) and provide dual network ports (e.g., via 1 MB regions).
In some implementations, an uncore region of a graph processing core 205 may be equipped with enhanced functionality to allow the MTCs 215a-d and STCs 220a-b to handle exclusively substantive, algorithmic workloads, with supporting work handled by the enhanced uncore, including synchronization, communication, and data movement/migration. The uncore may perform a variety of tasks including copy and merge operations, reductions, gathers/scatters, packs/unpacks, in-flight matrix transposes, advanced atomics, hardware collectives, reductions in parallel prefixes, hardware queuing engines, and so on. The ISA of the uncore can come from the pipelines' (MTCs and STCs) synchronous execution. In one example, the uncore may include components such as a collective engine 260, a queue engine 265, an atomic engine 270, and memory engine 275, among other example components and corresponding logic. An example memory engine 275 may provide an internal DMA engine for the architecture. The queue engine 265 can orchestrate and queue messaging within the architecture, with messages optimized in terms of (reduced) size to enable very fast messaging within the architecture. An example collective engine 260 may handle various collective operations for the architecture, including reductions, barriers, scatters, gathers, broadcasts, etc. The atomic engine 270 may handle any memory controller lock scenarios impacting the memory controller 250, among other example functionality.
More generally, graph algorithms face several major scalability challenges on traditional CPU and GPU architectures, because of the irregularity and sparsity of graph structures. For instance, in traditional cache-based processor architectures, which utilize prefetching, the execution of graph applications may suffer from inefficient cache and bandwidth utilization. Due to the sparsity of graph structures, caches used in such applications are thrashed with single-use sparse accesses and useless prefetches where most (e.g., 64 byte) memory fetches contain only a small amount (e.g., 8-bytes out of 64) of useful data. Further, overprovisioning memory bandwidth and/or cache space to cope with sparsity is inefficient in terms of power consumption, chip area and I/O pin count.
Further analysis of graph algorithms shows additional problems in optimizing performance. For instance, in the execution of graph algorithms, the computations may be irregular in character—they exhibit skewed compute time distributions, encounter frequent control flow instructions, and perform many memory accesses. For instance, for an example graph-based link analysis algorithm for a search engine, the compute time for a vertex in the algorithm is proportional to the number of outgoing edges (degree) of that vertex. Graphs such as the one illustrated in
As additional example shortcomings of conventional computing architectures' availability to handle graph processing, graph algorithms require frequent fine- and coarse-grained synchronization. For example, fine-grained synchronizations (e.g., atomics) may be required in a graph algorithm to prevent race conditions when pushing values along edges. Synchronization instructions that resolve in the cache hierarchy place a large stress on the cache coherency mechanisms for multi-socket systems, and all synchronizations incur long round-trip latencies on multi-node systems. Additionally, the sparse memory accesses result in even more memory traffic for synchronizations due to false sharing in the cache coherency system. Coarse-grained synchronizations (e.g., system-wide barriers and prefix scans) fence the already-challenging computations in graph algorithms. These synchronizations have diverse uses including resource coordination, dynamic load balancing, and the aggregation of partial results. These synchronizations can dominate execution time on large-scale systems due to high network latencies and imbalanced computation.
Additionally, current commercial graph databases may be quite large (e.g., exceed 20 TB as an in-memory representation). Such large problems may exceed the capabilities of even a rack of computational nodes of any type, which requires a large-scale multi-node platform to even house the graph's working set. When combined with the prior observations—poor memory hierarchy utilization, high control flow changes, frequent memory references, and abundant synchronizations—reducing the latency to access remote data is a challenge, combined with latency hiding techniques in the processing elements, among other example considerations. Traditional architectures and their limitations in being able to effectively handle graph algorithms extends beyond CPUs to include traditional GPU—sparse accesses prevent memory coalescing, branches cause thread divergence and synchronization limits thread progress. While GPUs may have more threads and much higher memory bandwidth, GPUs have limited memory capacity and limited scale-out capabilities, which means that they are unable to process large, multi-TB graphs. Furthermore, where graphs are extremely sparse (<<1% non-zeros), typical GPU memory usage is orders of magnitude less efficient, making GPUs all but unusable outside of the smallest graphs, among other example issues.
An improved computing system architecture may be implemented in computing systems to enable more efficient (e.g., per watt performance) graph analytics. In one example, specialized graph processing cores may be networked together in a low diameter, high radix manner to more efficiently handle graph analytics workloads. The design of such graph processing cores builds on the observations that most graph workloads have abundant parallelism, are memory bound and are not compute intensive. These observations call for many simple pipelines, with multi-threading to hide memory latency. Returning to the discussion of
Turning to
Continuing with this example, although the MTCs of an example graph processing core hide some of the memory latency by supporting multiple concurrent threads, an MTC may adopt an in-order design, which limits the number of outstanding memory accesses to one per thread. To increase memory-level parallelism and to free more compute cycles to the graph processing core, a memory offload engine (e.g., 430) may be provided for each block. The offload engine performs memory operations typically found in many graph applications in the background, while the cores continue with their computations. Turning to
Returning to
Besides avoiding the overhead of setting up communication for remote accesses, a DGAS also greatly simplifies programming, because there is no implementation difference between accessing local and remote memory. Further, in some implementations, address translation tables (ATT) may be provided, which contain programmable rules to translate application memory addresses to physical locations, to arrange the address space to the need of the application (e.g., address interleaved, block partitioned, etc.). Memory controllers may be provided within the system (e.g., one per block) to natively support relatively small cache lines (e.g., 8 byte accesses, rather than 64 byte accesses), while supporting standard cache line accesses as well. Such components may enable only the data that is actually needed to be fetched, thereby reducing memory bandwidth pressure and utilizing the available bandwidth more efficiently.
As noted above, a system, implemented as a chiplet, board, rack, or other platform, may include multiple interconnected graph processing cores, among other hardware elements.
A network may be provided in a system to interconnect the component within the system (e.g., on the same SoC or chiplet die, etc.) and the attributes of the network may be specially configured to support and enhance the graph processing efficiencies of the system. Indeed, the network connecting the blocks is responsible for sending memory requests to remote memory controllers. Similar to the memory controller, it is optimized for small messages (e.g., 8 byte messages). Furthermore, due to the high fraction of remote accesses, network bandwidth may exceed local DRAM bandwidth, which is different from conventional architectures that assume higher local traffic than remote traffic. To obtain high bandwidth and low latency to remote blocks, the network needs a high radix and a low diameter. Various topologies may be utilized to implement such network dimensions and characteristics. In one example, a HyperX topology may be utilized, with all-to-all connections on each level. In some implementations, links on the highest levels are implemented as optical links to ensure power-efficient, high-bandwidth communication. The hierarchical topology and optical links enable the system to efficiently scale out to many nodes, maintaining easy and fast remote access.
In some implementations, the system 710 may itself be capable of being further connected to other systems, such as other blade systems in a server rack system (e.g., 750). Multiple systems within the server system 750 may also be equipped with graph processing cores to further scale the graph processing power of a system. Indeed, multiple servers full of such graph processing cores may be connected via a wider area network (e.g., 760) to further scale such systems. The networking of such devices using the proposed graph processing architecture offers networking as a first-class citizen, supports point-to-point messaging, and relies upon a flattened latency hierarchy, among other example features and advantages.
In one example system, a C/C++ compiler (e.g., based on LLVM) may be utilized in the development of software for use with the graph processing systems described herein. For instance, the compiler may support a Reduced Instruction Set Computer (RISC) instruction set architecture (ISA) of the graph processing system, including basic library functions. In some implementations, graph-processing-specific operations, such as the offload engines and remote atomics, are accessible using intrinsics. Additionally, the runtime environment of the system may implement basic memory and thread management, supporting common programming models, such as gather-apply-scatter, task-based and single program, multiple data (SPMD)-style parallelism. Among other tools, an architectural simulator for the graph processing architecture may be provided to simulate the timing of all instructions in the pipelines, engines, memory, and network, based on the hardware specifications. Additional software development tools may be provided to assist developers is developing software for such graph processing systems, such as tools to simulate execution of the software, generate performance estimations of running a workload on the system, performance analysis reports (e.g., CPI stacks and detailed performance information on each memory structure and each instruction), among other example features. Such tools may enable workload owners to quickly detect bottleneck causes, and to use these insights to optimize the workload for graph processing systems.
In some implementations, software developed to perform graph analytics using the improved graph processing architecture discussed herein may be implemented as basic kernels, library overhead may be limited. In networked systems of multiple graph processing cores, the application code does not need to change for multinode execution, thanks to the system-wide shared memory. As an example, a software application may be written to cause the graph processing system to perform a sparse matrix dense vector multiplication (SpMV) algorithm. The basic operation of SpMV may include a multiply-accumulate of sparse matrix elements and a dense vector. A matrix input may be provided (e.g., an RMAT-30 synthetic matrix) stored in compressed sparse row (CSR) format. In one example, a straightforward implementation of SpMV may be programmed, with each thread of the graph processing cores calculating one or more elements of the result vector. The rows are partitioned across the threads based on the number of non-zeros for a balanced execution. It does not make use of DMA operations, and all accesses are non-cached at a default length (e.g., 8-byte), with thread local stack accesses cached by default. Such an implementation may outperform high performance CPU architectures (e.g., Intel Xeon) through the use of a higher thread count and 8-byte memory accesses, avoiding memory bandwidth saturation. In other implementations of an SpMV algorithm may be programmed to execute on the graph processing architecture utilizing selective caching. For instance, accesses to the matrix values are cached, while the sparse accesses to the vector bypass caches. In the compressed sparse row (CSR) representation of a sparse matrix, all non-zero elements on a row are stored consecutively and accessed sequentially, resulting in spatial locality. The dense vector, on the other hand, is accessed sparsely, because only a few of its elements are needed for the multiply-accumulate (the indices of the non-zeros in the row of the matrix). Accordingly, the accesses to the matrix are cached, while the vector accesses remain uncached 8-byte accesses, leading to a further potential performance improvement relative to CPU architectures. Further, an implementation of the SpMV algorithm may be further enhanced using a graph processing architecture, for instance, by a DMA gather operation to fetch the elements of the dense vector that are needed for the current row from memory. These elements may then be stored on local scratchpad. The multiply-accumulate reduction is then done by the core, fetching the matrix elements from cache and the vector elements from scratchpad. Not only does this significantly reduce the number of load instructions, it also reduces data movement: the index list does not need to be transferred to the requesting core, only the final gathered vector elements. While data is gathered, the thread is stalled, allowing other threads that have already fetched their data to compute a result vector element.
Programs, such as the examples above, may be designed to effectively use the graph processing architecture (e.g., using more than 95% of the available memory bandwidth, while not wasting bandwidth on useless and sparse accesses) and realize potentially exponential efficiency improvement over traditional architectures. Further, the improved graph processing architecture provide much higher thread count support (e.g., 144 threads for Xeon, verses thousands of threads (e.g., 16,000+) in the graph processing core implementation), enabling threads to progress while others are stalled on memory operations, efficient small size local and remote memory operations, and powerful offload engines that allow for more memory/compute overlap. Scaling graph processing systems (e.g., with multiple nodes) may yield compounding benefits (even if not perfectly linear, for instance, due to larger latencies and bandwidth restrictions or other example issues) to significantly outperform other multi-node conventional multinode processor configurations. While the examples focus on an SpMV algorithm, it should be appreciated that this example was offered as but one of many example graph algorithms. Similar programs may be developed to leverage the features of a graph processing architecture to more efficiently perform other graph-based algorithms including application classification, random walks, graph search, Louvain community, TIES sampler, Graph2Vec, Graph Sage, Graph Wave, parallel decoding FST, geolocation, breadth-first search, sparse matrix-sparse vector multiplication (SpMSpV), among other examples.
As noted above, sparse workloads exhibit a large number of random remote memory accesses and have been shown to be heavily network and memory bandwidth-intensive and less dependent on compute capability. While the graph processing architecture discussed herein provides efficient support for workloads that are truly sparse (and may be alternatively referred to as “sparse compute” devices), such a graph processing architecture lacks sufficient compute performance to execute dense kernels (e.g., matrix multiply, convolution, etc.) at needed performance in some applications. Dense kernels are a critical component of many critical compute applications such as image processing. Even with matrix computation units included, a challenge remains of effective integration of dense compute and offloading operations with regards to memory movement, matrix operation definition, and controllability across multiple threads.
Traditional offloading techniques (e.g., for offloading to an on-chip accelerator in an SoC) include memory mapped registers. For instance, the pipeline/core can perform the offload of the computation by writing to memory mapped registers present inside the accelerator. These registers may specify configurations as well as data needed to be used for the computation. This may also require the pipeline to monitor/poll registers if it is not sure that the offload engine is idle. In one example of a graph processing, an enhanced offload mechanism may be used to offload dense compute work from the graph processing cores to dense compute cores. There is a hardware managed queue that stores incoming offload instructions and monitors the current status of the pipeline and launches the instructions sequentially, enabling an easy offload mechanism for the software. Multiple graph processing core threads can each use the dense compute bandwidth of the dense compute cores by calling a new ISA function (e.g., by calling the dense.func) without worrying about the status of the dense core and whether other cores are using the dense core at the same time. The offload instruction can also allow efficient and simple passing of the program counter and operand addresses to one of the dense compute cores as well. The queue gives metrics through software readable registers (e.g., the number of instructions waiting (in a COUNT value)) and can help in tracking average waiting requests and other statistics for any dense core.
As noted above, a graph processing architecture may be particularly suited to operate on sparse workloads exhibiting a large number of random remote memory accesses and that are heavily network and memory bandwidth-intensive and less dependent on compute capability. To efficiently address this workload space, a graph processing architecture has a highly scalable low-diameter and high-radix network and many optimized memory interfaces on each die in the system. While this architectural approach provides efficient support for workloads that are truly sparse, providing a system with graph processing cores alone lacks sufficient compute performance to execute dense kernels (e.g., matrix multiply, convolution, etc.) that may be utilized in some application. To correct this performance gap, some systems incorporating a graph processing architecture may further include dense compute cores in addition to the graph processing cores, such as illustrated in the example of
In one example implementation, the compute capability within each dense core is implemented with a 16×16 reconfigurable spatial array of compute elements or systolic array (also referred to herein as a “dense array (DA)”). In some implementations, the reconfigurable array of compute elements of a dense compute core may be implemented as a multi-dimensional systolic array. This array is capable of a variety of floating point and integer operations of varying precisions. In this example, such an array can, in total, at a 2 GHz operating frequency a single dense core can achieve a peak performance of 1 TFLOP of double precision FMAs. Respective dense cores may have a control pipeline responsible for configuring the DA, executing DMA operations to efficiently move data into local buffers, and moving data into and out of the DA to execute the dense computation. The specific characteristics (e.g., memory locations, compute types, and data input sizes) of the operations vary based on the corresponding kernel. These kernels are programmed by software and launched on the control pipeline at a desired program counter (PC) value.
In some implementations, graph processing cores within a system that also include dense compute cores may include a dense offload queue and corresponding hardware circuitry to perform offloads from the graph processing core to the dense compute core control. This offload pipeline is managed intelligently by hardware managed through the dense offload queues (DOQ) to thereby simplify programmability for the software offloading the dense compute. With full hardware management, there is no need for software to check for the idleness of the dense compute or having to manage the contents and ordering of the queue, among other example benefits. The hardware circuitry managing the DOQs may also handle passing of the required program counter (PC) information, the operand, and the result matrix addresses to the control pipeline in a simple manner, among other example features.
In some implementations, a specialized instruction in the graph processing architecture ISA may be provided as a handle for initiating a request to a dense compute core. For instance, the software may use a dense function ISA instruction (e.g., ‘densefunc’) to trigger the offloading of a task from a graph processing core to a dense compute core by sending an instruction packet over the network interconnecting the cores from the graph processing core to one of the dense compute cores. The request may include the address of the target dense compute core, which may be used by the network to route the packet to the appropriate dense compute core. The request packet may be received at the dense offload queue (DOQ) corresponding to the targeted dense compute core.
Turning to
In some implementations, control pipeline 810 may be implemented as a single-threaded pipeline for managing and orchestrating hardware of the dense compute core 605 for performing various functions. For instance, control pipeline 810 may configure the reconfigurable array of compute elements 812 in one of a variety of possible configurations, read data from local or remote memory (e.g., through DMA calls to shared memory), copy/write such data to local scratchpad memory 816 of the dense compute core for use by the array 812, load instructions corresponding to a set of functions, instructions, kernel, or other program (e.g., based on a program counter value) for execution by compute units in the array, move result data (e.g., data generated during execution of the dense workload offloaded to the dense core) from the dense compute core (e.g., from scratchpad (e.g., 816) to memory accessible to a graph processing core (e.g., through a remote atomic), update registers identifying progress of the workload execution by the array of compute circuits, among other example tasks and functions.
Dense offload queue 804 may be utilized to provide hardware-managed orchestration and monitoring of workloads offloaded to the corresponding dense compute core 605 (e.g., from a sparse-compute graph processing core). The dense offload queue 804 may maintain a hardware-based queue of received instructions, may identify when the control pipeline 810 (and compute array 812) are available to handle a next instruction in the queue, and monitor the status of the control pipeline and performance of functions associated with an offload request. In this manner, the dense offload queue 804 may simplify software development for platforms incorporating a mix of sparse graph processing cores and dense processing cores by implementing the orchestration and monitoring of offloaded dense compute tasks in hardware. For instance, a single instruction (e.g., a dense offload instruction (e.g., dense.func)) may be defined in the ISA of the platform to simply and elegantly allow hardware to manage offloading of tasks and the performance of these tasks by a corresponding dense compute core (e.g., 605). The dense offload queue 804 can cause or launch action by the control pipeline 810 including the performance of actions using in crossbar 808, DMA engine 820, and/or micro-DMA engine 814 to appropriately configure the dense compute core hardware to perform a set of particular tasks, kernel, or other program. In certain embodiments, memory interface 822 is coupled to a (e.g., system) memory, e.g., shared memory external from the dense compute core 605. In certain embodiments, other components (e.g., core(s)) are coupled to core 605 via network switch 802, such as other dense compute cores and graph processing cores, among other example elements.
In certain embodiments, a micro-DMA engine 814 is coupled to the array of compute circuits 812, a scratch pad memory 816 (e.g., memory address accessible), and/or a buffer 818 (e.g., not memory address accessible) that bypasses the SPAD. In one embodiment, local scratchpad (SPAD) 816 is used to hold data that is subject to high reuse and bypass SPAD buffer 818 is used for low-reuse to reduce offload latency. Thirty-two parallel input/output ports are used as an example, and it should be understood that other numbers of ports may be utilized, e.g., 64, 128, etc. In certain embodiments, micro-DMA engine 814 is not coupled to memory external to core 605 and/or is not part of a cache coherency hierarchy.
In some implementations, the array of compute circuits 812 of a dense compute core is implemented as a multi-element (e.g., 16 element×16 element) reconfigurable spatial array of compute circuits (e.g., a dense array (DA)) capable of a variety of floating point and integer operations of varying precisions (e.g., a grid of floating-point unit (FPU) and/or arithmetic-logic unit (ALU) blocks). The reconfigurability of the array of compute circuits 812 allows for multiple options for connectivity between its internal compute circuits. In certain embodiments, the connectivity is pre-configured in the array of compute circuits 212 before (e.g., kernel) execution begins. Embodiments herein utilize a reconfigurable array of compute circuits because (i) given optimal array configuration, it provides high compute efficiency for a subset of kernels under a variety of input and output matrix sizes, and the programmability of the DA (e.g., via the μDMA instructions) seamlessly integrates into an ISA (e.g., an ISA for the second core type) with minimal control pipeline modifications, among other example features and benefits.
To achieve the optimal combination of ease of programmability and high compute performance through an array of compute circuits, embodiments herein utilize a DMA engine (e.g., micro-DMA engine) to provide the following features: (i) flexibility in the input/output matrix characteristics (e.g., configurability of row and/or column dimensions as well as the organization of the data structure in memory (e.g., row major or column major)), (ii) supporting the method of data movement and memory access patterns for multiple modes of the array (e.g., multicast, unicast, or systolic mode), and (iii) providing high parallelism at each array input/output to hit the highest performance.
The dense offload queue 804 manages incoming dense function requests passed from graph processing cores in a system. For instance, when a dense function request is received, the DOQ 804 will store it in its local memory buffer (DOQ SRAM 806). Whenever the control pipeline 810 has completed execution of the previous kernel and becomes free (or immediately if its already free), the DOQ 804 pops the function from its queue and launches the corresponding thread on the control pipeline 810. Accordingly, in some implementations, the DOQ 804 is responsible for both queue pointer management in the dense compute core, as well as serializing and launching the dense functions in the order that they were received and monitoring the status of the control pipeline 810 to determine when they need to be popped off the queue. Further, the DOG 804 can load the matrix addresses passed along with a dense functional instruction call (e.g., dense.func) into the register file of the control pipeline 810 and thus enables the control pipeline ease of access to this data, among other example functions.
Table 1 shows the structure of one example implementation of a dense function (dense.func) instruction:
In the example instruction illustrated in Table 1:
Continuing with the example of
In some examples, the dense instruction FIFO 925 may be implemented as a static random access memory (SRAM)-based FIFO that is 64 deep and 256 bits wide. This dense instruction FIFO 925 receives the instruction from the input interface unit 905. It sends the data to a thread launch block 950 when the queue is not empty and the control pipeline 810 is in a thread IDLE state. Due to its depth (in this example), the dense instruction FIFO 925 can hold a maximum of 64 instructions in flight. Accordingly, the DOQ 804 may be equipped with functionality to allow the DOQ 804 to check the status of the control pipeline 810 to know if a thread is currently active. For instance, this can be tracked and observed by a “Thread 0 FULL” bit in a thread control register 960. In some implementations, to optimize performance, the DOQ 804 can monitor thread activity by monitoring this thread control register value directly, for instance, as a single wire from the MSR block 920. When it is determined that the control pipeline 810 is free, the thread launch block 950 can pull data from the dense FIFO queue 925 and cause a corresponding program to be launched by the control pipeline 810 by writing initial values to the register file 965 used by the control pipeline 810 and sending additional data through a pipeline arbiter block 970 for use by the control pipeline 810 in accessing instructions corresponding to the functions identified in the offloaded workload, configuring the dense compute core array, loading the appropriate operand data in local scratchpad of the dense compute core array, and directing the movement of data and execution of instructions in accordance with performance of the functions by the dense compute array.
In some implementations, machine specific registers (MSRs) (e.g., in MSR block 920) may include one or more registers to identify (e.g., to software and/or other compute blocks of a platform) the status of the queue maintained by the DOQ 804, as well as the status of functions launched by the DOQ 804. In one example, the MSRs may include one or more status registers and one or more count registers. Given that the DOQ 804 manages a single queue of a set size (e.g., 64 entries), there may be no need for configuration of address and size, simplifying the registers in MSR block 920. In one example, the MSR status register may be utilized to record and identify the status of the single queue buffer that is managed by the dense offload queue 804. Bit fields in this register may include “full”, “empty”, and exception information. A Count register may be utilized to identify the number of elements currently in the queue. If this value is non-zero, the thread launch block will know to send the information to the control pipeline to launch the thread, among other examples.
Once the DOQ 804 detects that the control pipeline 810 is idle and the queue has a valid instruction waiting, the DOQ 804 uses the instruction information to launch the thread on the control pipeline. Accordingly, the DOQ 804 may begin by pulling the oldest instruction off of the tail of the dense FIFO queue and update the internal FIFO/queue pointers accordingly. The DOQ 804 may then issue a store operation of the Matrix A Address into the control pipeline register file (e.g., an 8 Byte store into R1), as well as issue a store operation of the Matrix B Address into the control pipeline register file (e.g., an 8 Byte store into R2) and a store operation of the Matrix C Address into the control pipeline register file (e.g., an 8 Byte store into R3). The DOQ 804 may additionally issue a store operation of the Start Program Counter (PC) value to the control pipeline thread 0 program counter MSR (e.g., an 8 B store) to identify the first instruction to be executed in a set of instructions or functions embodying the workload to be performed by the dense compute core. The DOQ 804 may then issue a store operation to set the FULL and ENABLE MSR bits in the control pipeline MSR space to kick start the thread. Once these stores are all successful, the thread has been launched and the DOQ's role has concluded for that specific instruction. The DOQ 804 should now return to monitoring the idle status of the control pipeline for launching the next dense.func (if an instruction is waiting on the queue) on the control pipeline. Once an offload instruction is received and queued (or launched) by the DOQ, the DOQ may send an acknowledgement response, such as discussed above.
A dense offload queue (DOQ) may implement a hardware-based state machine and queue to enable offloading of tasks from graph processing cores to dense compute cores simply and efficiently and with minimal status monitoring my software. The DOQ may manage the queue of offload instructions received at a given dense compute core and launch corresponding threads at the hardware level, allowing software to simply utilize a dense offload function call (e.g., dense.func) and information provided through DOQ MSRs, rather than more granular management of dense compute core usage.
A graph processing core 205 may identify 1005 one or more functions in an algorithm (being executed by the graph processing core) that involve dense compute functions. Given the sparse compute architecture of the graph processing core 205 to simplify the software model through the provision of a specialized ISA instruction (e.g., dense.func), which the software may call to trigger the use of this hardware-implemented queue (e.g., the DOQ). In response to identifying the dense workload, the graph processing core 205 may send 1010 a dense offload instruction (e.g., 1015) over the network to a particular dense processing core (e.g., 605). As multiple dense compute cores may be accessible to the graph processing core over the network, the graph processing core (e.g., utilizing one or more of its single-threaded pipelines) may determine (e.g., from a register or table maintained in software), which dense compute core(s) are available and have bandwidth to assist in handling this dense compute workload. Accordingly, the graph processing core may identify the particular dense compute core as a candidate and address the instruction 1015 accordingly.
A dense offload queue (DOQ) 804 may queue 1020 offload instructions (and potentially other instructions) received on the network. As discussed above, the DOG 804 may monitor the status of the dense core control pipeline to determine the availability of dense compute resources. In some implementations, upon queuing a received instruction (e.g., 1020), the DOQ 804 may send 1025 a response (e.g., 1095) back to the requesting graph processing core 205 to acknowledge (e.g., 1055) the instruction. In other implementations, an additional or alternative response may be sent based on the launch of functions corresponding to the instructions, among other example implementations. The queue maintained by the DOQ may be FIFO in that, as the dense compute core finished performing a workload corresponding to the earliest received offload instruction, the DOQ may cause the next received offload instruction to be launched (e.g., 1035) upon determining 1030 that the control pipeline is available (e.g., finished with the preceding instruction's workload). Accordingly, the DOQ 804 may message 1036 the control pipeline 810 to reactivate the control pipeline and provide the control pipeline with the information included in the next received instruction (e.g., 1015). The control pipeline 810 may use this information and launch performance of the corresponding functions by configuring 1040 the dense compute array, moving data 1045 to the local scratchpad of the dense compute core (e.g., from shared memory via DMA calls), and identify the set of functions corresponding to the workload and orchestrate the performance of these functions using the dense compute core's resources (e.g., compute array, scratchpad, local memory, etc.).
After launching 1035 the functions, the DOQ 804 may additionally monitor 1065 the status of the control pipeline 810 to the determine whether the performance of the corresponding functions is complete. This may be identified through a register associated with the control pipeline. In some implementations, the pipeline may deactivate following completion of the functions to indicate its availability and status of the functions, among other example implementations. The control pipeline 810 may also orchestrate the delivery of results or outputs (e.g., 1075) generated from performance of the function(s) by causing 1070 result data to be written to shared memory or other memory accessible to the requesting graph processing core. The graph processing core may access 1080 the result data and utilize these results (in some implementations) in the performance of subsequent sparse compute functions associated with a graph analytic algorithm performed using the graph processing core(s). In some implementations, software may cause a program or algorithm to be parallelized by splitting the workload across multiple graph processing cores and/or dense processing cores. For instance, in one example, a result generated by a dense compute core may be accessed and utilized by another graph processing core, other than the graph processing core that requested the corresponding workload offload, among other examples. In some cases, offloaded functions may be blocking functions, while in other instances, the offloaded functions may be performed in parallel with other functions performed by the requesting graph processing core. Indeed, the platform utilizing both graph processing cores and dense compute cores may be highly flexible in its applications and the programs that may be crafted to perform various graph-based algorithms in efficient and optimized ways.
As noted above, a DOQ may monitor 1065 the status of the control pipeline and determine 1090 when the control pipeline has completed directing the performance of a given workload and is available to be reactivated again to launch a next workload associated with a next offload instruction in the DOQ queue. Indeed, upon identifying the availability of the control pipeline 810, the DOQ 804 may pop the next instruction off the queue and repeat the flow by again launching functions associated with this next instruction and so on in accordance with the programs being run on the platform.
In some instances, it may be desired to simulate one or more of the systems described above. Due to the size of these systems, the simulation may be performed using a distributed simulation system with multiple nodes interconnected with one another via a Message Passing Interface (MPI) protocol. However, simulating large-scale systems (e.g., 710 or 750) that incorporate multiple graph processing devices (e.g., 705, 715, 720, 725, etc.) may be quite difficult, as typical system level simulators usually deploy serial or multi-threaded memory models with monolithic blocks of simulated memory resources, which offer limited memory bandwidth and performance and do not scale for large data-center-level system simulations. Moreover, memory Intensive workloads, such as those consumed by the graph processing systems discussed herein (e.g., Graph Analytics, Sparse AI, etc.) can worsen these issues, making it almost impossible to run this class of workloads for large practical datasets, and limiting datacenter pathfinding and software prototyping.
DRAMsim1, DRAMsim2 and DRAMsim3 are example memory simulators that may typically be used for system simulations. While they are cycle accurate, they are also relatively slow. Other example memory simulators include p-DRAMsim2, which is a single process multi-threaded version of DRAMsim, and GEMS, which can interface with DRAMsim for modeling memory and uses DRAMsim in a monolithic configuration. Each of these, however, simulates system memory as a monolithic block of memory controlled by a single memory controller (MC), which can present memory bottlenecks, memory contention, or other issues.
Each of the computing nodes 1110 may be implemented by a computer system according to
A monolithic model, such as that shown in
To address these issues and others, embodiments herein implement a specialized distributed memory model that offers improved simulation performance (e.g., 1-3 orders of magnitude simulation speed increases) and memory bandwidth that scales with size of the simulated system. This may translate to shorter simulation times, enablement of workload analysis with large real-world datasets, and better performance per dollar (compute requirement, electricity, etc.) with shorter turnaround times. Furthermore, this may enable the performance of rapid cutting-edge workload analysis (especially memory intensive workload domains, e.g., Graph Analytics, Sparse AI, Graph Neural Networks, etc.), architecture pathfinding, and software development, among other example applications. In some implementations, this specialized memory model may also be applicable to or implemented as hardware memory systems, in order to achieve a high bandwidth and high-performance architecture, among other examples. In some embodiments, the scalable, high-performance distributed memory model may be adopted for data-center-scale supercomputing clusters (e.g., those incorporating systems such as 750 or others described above) that scales with the size of the system being simulated (e.g., with the total number of simulated cores) and accelerates system level simulations by 2-3 orders of magnitude.
In certain embodiments, each node 1210 may simulate an equal or substantially equal portion of the system memory. For instance, where the total system memory size is represented by M and there are N nodes 1210 (e.g., where N is the number of system cores simulated), each node 1210 may simulate a memory module 1211 that is of size M/N. Other embodiments may simulate memory chunks 1211 having different sizes. In the example system 1200, each core of a graph processing system may be simulated as a process 1212 with a memory module 1211 (coupled with its own memory controller). The memory module 1211 may be simulated as a separate thread within that process. This parallel distributed memory model forms the building blocks of a scalable distributed simulation model, which grants performance scaling proportional to the scale of system being simulated.
In certain embodiments, a distributed memory model may be designed for maximum flexibility, e.g., by allowing for adjustment of the per-core memory module size configuration option. By setting this option equal to total memory size, the user can force the memory model to use a single memory controller, forcing the model to act as a monolithic model. This design may also be hierarchical, modular, and highly parallelizable. The model's parallelism may be proportional to the number of cores (N) being simulated. For instance, a single thread inside the process may be used to model the core, to model its memory controller, and the attached memory module. It is also possible to make it multithreaded, further extending the parallelism and performance improvement.
Further, by adjusting a memory striping size configuration option, the user can spread sequential data across the nodes 1210 at a chosen granularity, evenly over all the distributed memory controllers (MCs). If the chosen striping size is small, there is high statistical probability of concurrent memory accesses from different cores going to different MCs, thus significantly decreasing the chances of memory contention and hotspots in the memory model. Optionally, to accelerate simulation of a system with a central memory (i.e., with a single MC), users can guide simulator to use memory striping (i.e., simulating a central memory with multiple MCs and memory modules) for speeding up functional simulations, and ignore it (e.g., use single MC) for performance projections. This may allow the user to parallelize memory simulation that would have otherwise rather run serially. This gain can be achieved without altering workloads or their performance. Also, because of the presence of multiple MCs, the total observable memory bandwidth may be Nx times (N is total number of cores being simulated) that of a monolithic model (1×), as it scales up with size of system being simulated, providing improved simulator memory bandwidth for the workloads. These improvements significantly improve simulation speed for memory intensive workloads, such as graph processing workloads, enabling simulation of the computing systems disclosed herein using real world workloads having large datasets.
Functionality of the parallel distributed memory model can be broken down, in some instances, into two key aspects—memory model initialization and memory operation routing.
In the example process 1300, the distributed system simulator is first configured with at least three settings (as shown in 1301 in
At 1302, it is determined whether the total memory size configuration parameter is the same as the per core memory module size configuration parameter. If so, then a single core simulation has been requested with a monolithic memory model at 1304. At 1306, the memory module and memory controller are initialized with a single core, with one process dedicated for the core simulation and one thread dedicated for the memory controller. At 1308, the initialized memory controller loads an input file for the simulation, which may include or represent an image of an initial memory state for the simulation.
If, however, it is determined that the total memory size configuration parameter is not the same as the per core memory module size configuration parameter, then it is determined at 1310 that a distributed model with multiple memory controllers has been selected, and at 1312, a memory module and corresponding memory controller is initiated for each core being simulated in the model (e.g., as shown in
At 1314, a memory controller identifier (ID) (identifying the unique MC) to memory controller process ID (identifying a process/node on which the MC is located) lookup table is created. The lookup table may provide a mapping that shows on which node (e.g., 1210) every MC is located, and allows the processes executing on the node to access partitions on other nodes. That is, in the distributed model, each core being simulated starts a thread dedicated for the MC and memory module, and such a lookup table may be provided to map MC IDs to actual process IDs, enabling faster routing of memory operations.
Next, all of the initialized MCs load their respective portions (equal to the stripe size) of the input file(s), if any, onto their respective simulated memories via 1316-1324. The input file(s) may include or represent an image of an initial memory state for the system simulation. In some embodiments, the MCs may each perform these operations in parallel with one another. Simulators often pre-load workload inputs into a simulated memory to save significant input/output (i.e., data copy) time. The input file(s) may be in a hex format in some embodiments, in which each line has a global memory address and corresponding data that is to be loaded/stored at that address. The operations 1316-1324 may be performed by each MC as it loops over each line of the input file(s).
At 1316, each MC determines an address (ADDR) in a line in an input file, and then, at 1318, determines a target MC ID at which the corresponding data is to be stored. The target MC ID may be determined according to TARGET MC ID=((ADDR/STRIPE SIZE) % (TOTAL MC COUNT)), as shown in
The above operations (i.e., 1316-1324) may continue until the end of the input file(s) is reached, at which point, all distributed MCs may be considered fully initialized and ready for servicing memory requests in parallel with one another, e.g., according to the process 1400 shown in
Turning to
Upon arrival at the destination simulated core, at 1408, the packet is forwarded by the target process to the target MC within that core, and at 1410, the target MC determines a virtual address based on the global physical memory address in the packet (ADDR). This may be done according to VIRTUAL ADDR=(ADDR % STRIPE SIZE)+(ADDR/(STRIPE SIZE*TOTAL MC COUNT))*STRIPE SIZE). At 1412, the target MC performs the operation on the virtual address within its memory module. At 1414, the target MC sends a response operation back to the source core that initiated the memory operation. For example, if the memory operation is a read, the target MC may respond with data in response to the read at its virtual address. The response packet may be formatted according to a MPI format (e.g., the one implemented over the network 1220 of
It can be seen from the chart 1500 that the parallel distributed memory model performance exhibits a classic weak scaling trend, with the performance staying relatively constant as the workload and compute resources are scaled up together. In contrast, the monolithic memory model shows performance degradation to a point where it becomes effectively unfeasible (in terms of turnaround time and resources) to carry out larger simulations. For instance, simulations of 128 cores with the monolithic memory model did not finish after 16 days of uninterrupted runtime. The example chart 1500 highlights the benefits and speedup potentials of the parallel distributed memory model (e.g., with an observed ˜60× speedup for 64 core simulation, which can easily reach beyond 100× speedup based on established trends for larger system configurations) and shows the downside of monolithic memory models.
A parallel distributed model may come with few downsides. The multiple memory endpoints increase implementation complexity of simulator initialization process, and network routing logic. There are additional address decoding and translation passes performed on all memory operations to determine the target MC that the operation must be routed to. Lastly, additional threads may start upon simulator initialization, which might end up using more hardware resources. However, such extra decoding/translation overheads may be minimized, in some implementations, by using pre-computed lookup tables and reduced resource pressure by careful thread management, among other examples.
Example Computer Architectures
Referring now to
The optional nature of additional processors 1615 is denoted in
The memory 1640 may be, for example, dynamic random-access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 1620 communicates with the processor(s) 1610, 1615 via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as Quickpath Interconnect (QPI), or similar connection 1695.
In one embodiment, the coprocessor 1645 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub 1620 may include an integrated graphics accelerator.
There can be a variety of differences between the physical resources 1610, 1615 in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.
In one embodiment, the processor 1610 executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor 1610 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 1645. Accordingly, the processor 1610 issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor 1645. Coprocessor(s) 1645 accept and execute the received coprocessor instructions.
Referring now to
Processors 1770 and 1780 are shown including integrated memory controller (IMC) units 1772 and 1782, respectively. Processor 1770 also includes as part of its bus controller units point-to-point (P-P) interfaces 1776 and 1778; similarly, second processor 1780 includes P-P interfaces 1786 and 1788. Processors 1770, 1780 may exchange information via a point-to-point (P-P) interface 1750 using P-P interface circuits 1778, 1788. As shown in
Processors 1770, 1780 may each exchange information with a chipset 1790 via individual P-P interfaces 1752, 1754 using point to point interface circuits 1776, 1794, 1786, 1798. Chipset 1790 may optionally exchange information with the coprocessor 1738 via a high-performance interface 1739. In one embodiment, the coprocessor 1738 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.
A shared cache (not shown) may be included in either processor or outside of both processors, yet is connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.
Chipset 1790 may be coupled to a first bus 1716 via an interface 1796. In one embodiment, first bus 1716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.
As shown in
Referring now to
Referring now to
Embodiments (e.g., of the mechanisms) disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the disclosure may be implemented as computer programs or program code executing on programmable systems including at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
Program code, such as code 1730 illustrated in
The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.
One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.
Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
Accordingly, embodiments of the disclosure also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.
Thus, different implementations of the processor 2000 may include: 1) a CPU with the special purpose logic 2008 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 2002A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores 2002A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 2002A-N being a large number of general purpose in-order cores. Thus, the processor 2000 may be a general-purpose processor, coprocessor, or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 2000 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.
The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units 2006, and external memory (not shown) coupled to the set of integrated memory controller units 2014. The set of shared cache units 2006 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring-based interconnect unit 2012 interconnects the integrated graphics logic 2008, the set of shared cache units 2006, and the system agent unit 2010/integrated memory controller unit(s) 2014, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units 2006 and cores 2002-A-N.
In some embodiments, one or more of the cores 2002A-N are capable of multi-threading. The system agent 2010 includes those components coordinating and operating cores 2002A-N. The system agent unit 2010 may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 2002A-N and the integrated graphics logic 2008. The display unit is for driving one or more externally connected displays.
The cores 2002A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 2002A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.
Emulation (Including Binary Translation, Code Morphing, Etc.)
In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.
“Logic” (e.g., as found in offload engines, memory managers, memory controllers, network controllers, etc. and other references to logic in this application) may refer to hardware, firmware, software and/or combinations of each to perform one or more functions. In various embodiments, logic may include a microprocessor or other processing element operable to execute software instructions, discrete logic such as an application specific integrated circuit (ASIC), a programmed logic device such as a field programmable gate array (FPGA), a memory device containing instructions, combinations of logic devices (e.g., as would be found on a printed circuit board), or other suitable hardware and/or software. Logic may include one or more gates or other circuit components. In some embodiments, logic may also be fully embodied as software.
Use of the phrase ‘to’ or ‘configured to,’ in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task. In this example, an apparatus or element thereof that is not operating is still ‘configured to’ perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. But a logic gate ‘configured to’ provide an enable signal to a clock does not include every potential logic gate that may provide a 1 or 0. Instead, the logic gate is one coupled in some manner that during operation the 1 or 0 output is to enable the clock. Note once again that use of the term ‘configured to’ does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.
Furthermore, use of the phrases ‘capable of/to,’ and or ‘operable to,’ in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of to, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.
A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as 1's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have been used. For example, the decimal number ten may also be represented as a binary value of 418A0 and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.
Moreover, states may be represented by values or portions of values. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. In addition, the terms reset and set, in one embodiment, refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e. reset, while an updated value potentially includes a low logical value, i.e. set. Note that any combination of values may be utilized to represent any number of states.
The embodiments of methods, hardware, software, firmware, or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.
Instructions used to program logic to perform embodiments of the disclosure may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).
The following examples pertain to embodiments in accordance with this Specification.
Example 1 is a distributed simulation system comprising: a plurality of computing nodes interconnected via a network implementing a Message Passing Interface (MPI) protocol, wherein each computing node is to simulate hardware logic of a core of a graph processing system and to simulate a respective system memory portion of the graph processing system.
Example 2 includes the subject matter of Example 1, wherein each computing node is to simulate the hardware logic of a core of the graph processing system as a process and to simulate the system memory portion as a thread within the process.
Example 3 includes the subject matter of Example 1 or 2, wherein each computing node is to simulate a memory controller corresponding to its respective system memory portion.
Example 4 includes the subject matter of any one of Examples 1-3, wherein the distributed computing system includes N computing nodes and is to simulate M bytes of data, and each computing node is to simulate a system memory portion equal to M/N.
Example 5 includes the subject matter of any one of Examples 1-4, wherein each computing nodes is to initialize its respective simulated system memory portion by: accessing an input file representing an initial state of the system memory; and copying, to the computing node, portions of the input file corresponding to the respective simulated system memory portion.
Example 6 includes the subject matter of Example 5, wherein the input file comprises a plurality of lines, each line mapping a system memory address to corresponding system memory data, and each computing node is to copy the portions of the input file by: determining, for each line of the input file, a target system memory portion based on the system memory address; determine whether the target system memory portion corresponds to the computing node; and copying the system memory data to the computing node based on a determination that the system memory portion corresponds to the computing node.
Example 7 includes the subject matter of Example 6, wherein each computing node is further to copy the portions of the input file by: determining a virtual address of the simulated system memory portion that corresponds to the system memory address; and storing the system memory portion at the virtual address of the simulated system memory portion.
Example 8 includes the subject matter of any one of Examples 1-7, wherein each computing node is to simulate a memory operation performed by the simulated hardware logic by: determining a target computing node of the system based on a system memory address indicated in the memory operation; and routing the memory operation to the target computing node.
Example 9 includes the subject matter of Example 8, wherein the target computing node is different from the computing node simulating the memory operation, and the memory operation is routed over the network via a packet formatted according to the MPI protocol.
Example 10 includes the subject matter of Example 8 or 9, wherein the computing node is to determine the target computing node of the system by: determining a target system memory portion for the memory operation based on the system memory address indicated in the memory operation; and determining the target computing node based on a lookup table mapping each simulated system memory portion to a respective computing node of the system.
Example 11 includes the subject matter of any one of Examples 8-10, wherein the target computing node is to process the memory operation by: determining a target virtual address of the simulated system memory portion of the target computing node based on the system memory address of indicated in the memory operation; and performing the memory operation at the virtual address of the target computing node.
Example 12 includes the subject matter of Example 11, wherein the target computing node is different from the computing node simulating the memory operation, and the target computing node is further to send a response to the computing node simulating the memory operation via a packet formatted according to the MPI protocol.
Example 13 is a method comprising: initializing, at a computing node of a distributed simulation system, a system memory portion representing a subset of a system memory of a graph processing system, wherein initializing the system memory portion comprises: accessing an input file representing an initial state of the system memory; and copying, to the computing node, portions of the input file corresponding to the respective simulated system memory portion; and performing, by the computing node, a functional simulation of a core of the graph processing system, wherein performing the functional simulation comprises simulating one or more memory operations, wherein simulating a memory operation comprises: determining a target computing node of the system based on a system memory address indicated in the memory operation; and routing the memory operation to the target computing node.
Example 14 includes the subject matter of Example 13, wherein the input file comprises a plurality of lines, each line mapping a system memory address to corresponding system memory data, and copying the portions of the input file comprises: determining, for each line of the input file, a target system memory portion based on the system memory address; determine whether the target system memory portion corresponds to the computing node; and copying the system memory data to the computing node based on a determination that the system memory portion corresponds to the computing node.
Example 15 includes the subject matter of Example 14, wherein copying the portions of the input file further comprises: determining a virtual address of the simulated system memory portion that corresponds to the system memory address; and storing the system memory portion at the virtual address of the simulated system memory portion.
Example 16 includes the subject matter of any one of Examples 13-15, wherein determining the target computing node comprises: determining a target system memory portion for the memory operation based on the system memory address indicated in the memory operation; and determining the target computing node based on a lookup table mapping each simulated system memory portion to a respective computing node of the system.
Example 17 includes one or more non-transitory computer-readable media comprising instructions that, when executed by one or more processors, cause the processors to: initialize a system memory portion representing a subset of a system memory of a graph processing system, wherein the instructions are to initialize the system memory portion by: accessing an input file representing an initial state of the system memory; and copying, to the computing node, portions of the input file corresponding to the respective simulated system memory portion; and perform a functional simulation of a core of the graph processing system, the functional simulation comprising one or more memory operations, wherein the instructions are to simulate a memory operation by: determining a target computing node of the system based on a system memory address indicated in the memory operation; and routing the memory operation to the target computing node.
Example 18 includes the subject matter of Example 17, wherein the input file comprises a plurality of lines, each line mapping a system memory address to corresponding system memory data, and the instructions are to copy the portions of the input file by: determining, for each line of the input file, a target system memory portion based on the system memory address; determine whether the target system memory portion corresponds to the computing node; and copying the system memory data to the computing node based on a determination that the system memory portion corresponds to the computing node.
Example 19 includes the subject matter of Example 18, wherein the instructions are to copy the portions of the input file further by: determining a virtual address of the simulated system memory portion that corresponds to the system memory address; and storing the system memory portion at the virtual address of the simulated system memory portion.
Example 20 includes the subject matter of any one of Examples 17-20, wherein determining the target computing node comprises: determining a target system memory portion for the memory operation based on the system memory address indicated in the memory operation; and determining the target computing node based on a lookup table mapping each simulated system memory portion to a respective computing node of the system.
Example 21 includes the subject matter of any one of Examples 17-21, wherein the target computing node is different from the computing node simulating the memory operation, and the instructions are to route the memory operation to the target computing node over a network via a packet formatted according to the MPI protocol.
Example 22 includes the subject matter of any one of Examples 17-21, wherein the instructions are further to process a memory operation request by: determining a target virtual address of the simulated system memory portion of the target computing node based on the system memory address of indicated in the memory operation; and performing the memory operation at the virtual address of the target computing node.
Example 23 includes the subject matter of any one of Examples 17-22, wherein the instructions are to perform the functional simulation of the core by simulating hardware logic of the core as a process and simulating the system memory portion as a thread within the process.
Example 24 includes the subject matter of any one of Examples 17-23, wherein the instructions are further to simulate a memory controller with the system memory portion, the memory controller to process the memory operations.
Example 25 includes an apparatus comprising means to implement any one of Examples 13-24.
Example 26 is a system comprising: a plurality of computing nodes, each node comprising a system memory portion representing a subset of a system memory of a graph processing system, wherein the system memory portion is initialized by: accessing an input file representing an initial state of the system memory; and copying, to the computing node, portions of the input file corresponding to the respective system memory portion; and executing memory operation instructions on cores of the graph processing system comprising, wherein execution of the memory operation instructions comprises: determining a target computing node of the system based on a system memory address indicated in the memory operation instruction; and routing the memory operation instruction to the target computing node.
Example 27 includes the subject matter of Example 26, wherein the input file comprises a plurality of lines, each line mapping a system memory address to corresponding system memory data, and each computing node is to copy the portions of the input file by: determining, for each line of the input file, a target system memory portion based on the system memory address; determine whether the target system memory portion corresponds to the computing node; and copying the system memory data to the computing node based on a determination that the system memory portion corresponds to the computing node.
Example 28 includes the subject matter of Example 27, wherein each node is to copy the portions of the input file further by: determining a virtual address of the simulated system memory portion that corresponds to the system memory address; and storing the system memory portion at the virtual address of the simulated system memory portion.
Example 29 includes the subject matter of Example 26, wherein each node is to determine the target computing node by: determining a target system memory portion for the memory operation based on the system memory address indicated in the memory operation; and determining the target computing node based on a lookup table mapping each simulated system memory portion to a respective computing node of the system.
Example 30 includes one or more non-transitory computer-readable media comprising instructions that, when executed by one or more processors, cause the processors to: initialize a computing node of a distributed graph processing system, the node comprising a system memory portion representing a subset of a system memory of a graph processing system, wherein the system memory portion is initialized by: accessing an input file representing an initial state of the system memory; and copying, to the computing node, portions of the input file corresponding to the respective system memory portion; and execute memory operations, wherein execution of the memory operations comprises: determining a target computing node of the system based on a system memory address indicated in the memory operation instruction; and routing the memory operation instruction to the target computing node.
Example 31 includes the subject matter of Example 30, wherein the input file comprises a plurality of lines, each line mapping a system memory address to corresponding system memory data, and each computing node is to copy the portions of the input file by: determining, for each line of the input file, a target system memory portion based on the system memory address; determine whether the target system memory portion corresponds to the computing node; and copying the system memory data to the computing node based on a determination that the system memory portion corresponds to the computing node.
Example 32 includes the subject matter of Example 31, wherein each node is to copy the portions of the input file further by: determining a virtual address of the simulated system memory portion that corresponds to the system memory address; and storing the system memory portion at the virtual address of the simulated system memory portion.
Example 33 includes the subject matter of Example 30, wherein the instructions are to determine the target computing node by: determining a target system memory portion for the memory operation based on the system memory address indicated in the memory operation; and determining the target computing node based on a lookup table mapping each simulated system memory portion to a respective computing node of the system.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In the foregoing specification, a detailed description has been given with reference to specific example embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. Furthermore, the foregoing use of embodiment and other exemplarily language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as potentially the same embodiment.
This application claims benefit to U.S. Provisional Patent Application Ser. No. 63/295,280, filed Dec. 30, 2021, which is incorporated by reference herein in its entirety.
This invention was made with Government support under Agreement No. HR0011-17-3-0004, awarded by DARPA. The Government has certain rights in the invention.
| Number | Date | Country | |
|---|---|---|---|
| 63295280 | Dec 2021 | US |
