Patent Application
20150363230
This application claims priority to Japanese Patent Application No. 2013-010194 filed on Jan. 23, 2013, the disclosure of which is incorporated herein by reference.
The present invention relates to a method of extracting parallelism underlying in an original program of sequential processing, and a method of producing, using the parallelism extraction method, a parallelized program executed on a multicore processor including a plurality of processor cores.
Multicore processors in which a plurality of processor cores are integrated have been released one after another by microprocessor manufacturers. The movement of using multicore microprocessors has been seen not only in the fields of supercomputers, servers, desktop computers, and PC servers but also in the fields of home information appliances and device embedment (for example, mobile phones, game machines, car navigation systems, digital television receivers, and HDD/DVD recorders and players).
Meanwhile, for the development of next-generation vehicles which are safer, more comfortable, and more energy-saving, it is important to enhance each of a real-time control system for engine control and the like, an information system for external recognition such as person recognition and other vehicle recognition and presentation of information necessary for driving, music, video, and the like, and an integrated control system for integrated control of the control system and the information system.
To enhance the control system, the information system, and the integrated control system, higher functionality of processors is important. For example, to enhance the engine control system which is important for the development of safer, more comfortable, and more energy-saving vehicles, increases in computational load due to enhancement of control algorithms, realization of new control functions, and the like are inevitable.
To solve such a problem of increases in computational load associated with the need to enhance the engine control system, higher functionality of processors used for engine control is essential.
Conventionally, the operating frequency of a processor needs to be increased in order to enhance its functionality. Such a technique is, however, difficult to be applied to apparatuses such as vehicles, for the following reasons: since the power consumption increases with the cube of the operating frequency, a significant increase in power consumption ensues; and safe operation needs to be ensured even in harsh operating environments of vehicles. This creates demand to shift to multicore processors capable of simultaneously achieving faster processing and lower power consumption by integrating a plurality of low-operating frequency processor cores on one chip and causing lower-frequency and lower-voltage processor cores to operate in parallel.
To meet such demand, multicore utilizing techniques in the car industry have been proposed. For example, an electronic control unit using a multicore processor has been proposed in a multicore architecture that employs a unified chassis control (UCC) algorithm, as described in Non Patent Literatures 1 and 2. This multicore processor is made up of three processor cores. The electronic control unit is divided into three functions, and the three functions are assigned to the respective three processor cores for functional distribution. The method is called asymmetric multicore processing (AMP), and can improve throughput by achieving functional distribution but has difficulty in reducing latency. The method also has a problem of being unable to make maximum use of multicore resources unless the load for each function is evenly balanced.
The present invention proposes a method of reducing latency, i.e. increasing speed, by applying parallel processing to engine control which is a main function of a vehicle control system as described later. To perform faster computation for engine control and the like on a multicore processor than conventional processing on one processor core, a method of dividing computation and appropriately assigning computational loads to a plurality of processors to perform the computation, namely, symmetric multicore processing (SMP), is important. This computation method SMP is typically referred to as parallel processing, and a program for parallel processing is referred to as a parallelized program. Producing or generating a parallelized program from an original program of sequential processing that runs on one processor is referred to as program parallelization.
Manual program parallelization has serious problems such as an increase in development period and a resulting increase in software development cost, and a decrease in reliability of the parallelized program. Software for automatically generating a parallelized program from a sequential processing program has been studied in order to solve such problems.
As a conventional parallelization method, a compiler for multigrain parallel processing which has been subjected to research and development by the inventors, called OSCAR compiler, is known (Patent Literature 1). The following describes the typical functions of the OSCAR compiler. A compiler normally means a program for converting a source program to be compiled into a computer-executable program (e.g. a program in a machine language). The parallelization compiler (OSCAR compiler) described below, on the other hand, has a function of generating a source code (an object code in some cases) of a parallelized program from a source code of an original program of sequential processing.
Multigrain parallel processing, which is a feature of the OSCAR compiler, is parallel processing in which coarse grain task parallel processing using parallelism among coarse grain tasks such as loops and subroutines present in the original program, medium grain parallel processing using parallelism in loop iteration level, and near fine grain parallel processing using parallelism in statement level inside basic blocks are combined hierarchically and performed across the whole program. Multigrain parallel processing, which is described in detail in Non Patent Literature 4, is briefly described below with reference to a flowchart in
In the coarse grain parallel processing, the compiler performs “lexical analysis and syntax analysis” in step 1901 and “macro task generation” in step 1902 in the flowchart in
In the coarse grain task parallel processing, the macro tasks generated in each layer are assigned to PGs and executed. Scheduling methods for determining to which PG a macro task is assigned include dynamic scheduling and static scheduling. Whether dynamic scheduling or static scheduling is selected is determined by the parallelization compiler based on the form of the MTG, runtime uncertainty, etc.
In the case where there is runtime uncertainty such as a conditional branch, dynamic scheduling is suitable, and macro tasks are assigned to PGs at runtime by dynamic scheduling. A dynamic scheduling routine operates a macro task execution management table and searches for an earliest executable condition of each macro task, according to the completion or branch direction determination of the macro task. If the macro task is executable, the macro task is enqueued to a ready queue. Macro tasks in the ready queue are sorted according to priority, and the first macro task in the ready queue is assigned to an idle processor core. When generating a dynamic scheduling code, a centralized scheduling method in which one dedicated processor performs scheduling and a distributed scheduling method in which the scheduling function is distributed among processors can be selectively used based on the number of processors used and the synchronization overhead of the system.
In the case where the MTG has only data-dependent edges, on the other hand, static scheduling is suitable. Static scheduling is a method in which the automatic parallelization compiler assigns macro tasks to PGs at compilation. Static scheduling can reduce runtime scheduling overhead, and reduce data transfer and synchronization overhead.
The parallelized program can also be generated in source-to-source form by parallelizable C or Fortran 77, using an API. In this case, for example, to attain executability in various platforms, API portions may be converted to runtime library calls using an OSCAR API standard interpretation system, after which codes for processors are compiled by the compiler in sequence to generate binary code.
Even when the below-mentioned engine control program of sequential processing is input, as an original program, to the conventional OSCAR compiler described using the flowchart in
The reason is explained below. Given that the engine control program has many conditional branches and the like, the conventional OSCAR compiler has difficulty in performing, by static scheduling, parallelization for efficient computation of macro tasks after a conditional branch on the multicore processor including the plurality of processor cores, and has no choice but to perform dynamic scheduling of assigning processor cores at runtime of the parallelized program. Hence, in the case where a process is assigned to a different processor core each time a branch occurs during the execution of the parallelized program, control overhead for process synchronization among cores increases, which results in an insufficient improvement in execution speed by parallelization.
The present invention accordingly proposes an effective parallelism extraction method for extracting parallelism underlying in a program in which basic blocks such as conditional branches and assignment statements continue with no loop processing, to generate a parallelized program suitable for execution on a multicore processor.
A typical example of the invention disclosed in the present application is the following. A method of extracting parallelism of an original program by a computer includes: a process of determining whether or not a plurality of macro tasks to be executed after a condition of one conditional branch included in the original program is satisfied are executable in parallel; and a process of copying the conditional branch regarding which the macro tasks are determined to be executable in parallel, to generate a plurality of conditional branches.
According to a typical embodiment of the present invention, an original program in which basic blocks such as conditional branches and assignment statements continue with no loop processing can be appropriately parallelized. A program that needs real-time processing, such as a control program, can also be appropriately parallelized.
The following describes an embodiment of the present invention with reference to drawings.
This embodiment describes a method of extracting parallelism in an engine control program as an original program in which basic blocks such as conditional branches and assignment statements continue with no loop processing and it is difficult for the program to be parallelized by the conventional parallelization method, and describes a parallelization method using the extraction method. Note that the present invention is applicable to parallelization of not only the engine control program described in this embodiment but also other (control) programs characterized by, for example, continuous basic blocks such as conditional branches and assignment statements.
[Compilation Process]
A process to parallelized program generation, in particular a parallelism extraction process, which is executed on a computer by the compiler according to the embodiment of the present invention for generating a high-performance parallelized program from an original program of sequential processing with many conditional branches, is described below. The parallelization compiler illustrated in
First, the parallelization compiler performs lexical analysis on the source program, and syntax analysis on the program (step 1901). Though the compiler analyzes the program in this embodiment, a programmer (human) may analyze the program in the case where the program is a simple program or the like. Moreover, information of the program necessary for the compiler may be produced upon producing the source program.
Next, the parallelization compiler generates a representation by hierarchical macro tasks of the program, based on the syntax analysis result (step 1902). Here, coarse grain tasks (macro tasks) are generated. In the case where the generated macro tasks are processed parallelly or sequentially in loop iteration level, the macro tasks are decomposed into a plurality of different macro tasks based on memory size of local memory or the like (loop aligned decomposition).
After this, the parallelization compiler analyzes control dependency (control flow) among the generated macro tasks (step 1903), analyzes data dependency among the macro tasks (step 1904), and generates an MFG based on the analysis results (step 1905). The parallelization compiler then analyzes the range of data accessed by each macro task based on the MFG (step 1906).
Following this, the parallelization compiler analyzes the earliest executable condition enabling the earliest execution of the program, using the above-mentioned program analysis results (step 1907). The parallelization compiler determines the number of processors assigned to the macro tasks and the parallel processing segments, to generate an MTG (step 1908).
The parallelization compiler then extracts, for a plurality of macro tasks determined to be executed in the same condition, a conditional branch regarding which the plurality of macro tasks are executable in parallel (e.g. have no data dependency), and copies the extracted conditional branch (“restructuring including conditional branch copying” in step 2909). If the copied conditional branches include a conditional branch to be further copied, the parallelization compiler returns to step 1902 to reanalyze the program after copying and, having performed steps 1902 to 1908, performs step 2909. Step 2909 is repeatedly performed until there is no more conditional branch copying or restructuring.
After this, the parallelization compiler performs task scheduling for determining the execution order of the macro tasks (step 1910). The task scheduling performed here includes memory management and task scheduling, data transfer scheduling, and low power consumption scheduling.
The memory management and task scheduling is scheduling for efficient data transmission/reception of each processor core in the multicore processor via local memory. The data transfer scheduling is scheduling for optimizing data transfer in each processor core and data transfer in the whole multicore processor, such as preload and post-store. The low power consumption scheduling is scheduling for achieving, in the case where a general-purpose processor (CPU), an accelerator (ACC), a data transfer unit (DTU), and the like in the multicore processor are in a wait state, power control of changing the clock frequency to low frequency or disconnecting power depending on the wait time.
The parallelization compiler then generates a parallelized program executable on the multicore processor, based on the task scheduling in step 1910 (step 1911). The parallelized program is generated based on the configuration of the multicore processor, and so includes statements of macro tasks for the general-purpose processor (CPU), macro tasks for the ACC, and macro tasks for the DTU. In the parallelized program generated here, a flat set statement and a flat check statement are inserted in the statements of macro tasks for the general-purpose processor (CPU), macro tasks for the ACC, and macro tasks for the DTU that are dependent on each other. These statements of macro tasks for the ACC and macro tasks for the DTU and the flag area are arranged in at least one memory out of distributed shared memory (URAM), local memory (ILM, DLM), on-chip centralized shared memory, and off-chip centralized shared memory.
The computer 100 is a computer including a processor (CPU) 101, memory 102, a nonvolatile storage device (HDD) 103, and a communication interface 106.
The processor 101 executes a program stored in the memory 102.
The memory 102 is a high-speed volatile storage device such as dynamic random access memory (DRAM), and stores an operating system (OS) and an application program. The basic functions of the computer 100 are realized by the processor 101 executing the operating system, and the functions of the parallelization compiler are realized by the processor 101 executing the application program.
The storage device 103 is a large-capacity nonvolatile storage device such as a magnetic storage device or flash memory, and stores a compiler and an original program executed by the processor 101. In other words, the compiler to be executed by the processor 101 is read from the storage device 103 and loaded into the memory 102, and executed by the processor 101.
The communication interface 106 controls communication between the computer 100 and other computers.
The computer 100 may include an input interface 104 and an output interface 105. The input interface 104 receives input from a keyboard 107 and a mouse 108 which are input devices. The output interface 105 is connected to a display device 109 which is an output device, and outputs a signal for displaying a computation result to the display device 109.
The computer 100 is a system that operates on one or more logically or physically configured computers. The parallelization compiler may run on one computer, or on a virtual computer constructed on a plurality of physical computer resources.
A program to be executed by the processor 101 is provided to each server via a removable medium (CD-ROM, flash memory, etc.) or a network, and stored in the storage device 103 which is a non-temporary storage medium. Each server may accordingly include an interface for reading such a removable medium.
[Overview of Engine Control Program of Sequential Processing]
The following describes an overview of the engine control program including the original program in this embodiment.
The engine control program in this embodiment is written in C, and runs on OSEK/VDX which is a real-time OS for vehicles (for example, see Non Patent Literature 3).
The operation of the program is described below.
In the following description, “task” in the engine control program is the term used in vehicle control programs, and corresponds to the above-mentioned original program input to the parallelization compiler.
In the case where the engine control program is executed on a conventional single-core processor, first a StartOS function which is an API provided by the OSEK/VDX is called from a main function in C, to start the OS.
After this, the execution of tasks periodically executed from the entry task is reserved. In this engine control program, 38 tasks, namely, Task2 to Task39, are defined in total, and the execution of Task22 to Task39 which are periodic tasks is reserved. Task2 to Task21 are tasks indirectly called from the periodic tasks.
Next, the periodic tasks are periodically executed according to a timer in the OS.
[Extraction of Parallelism from Engine Control Program and Parallelization Method]
The following describes the method of extracting parallelism from Task15 in the engine control program and the parallelization method. The parallelization process by the compiler according to the present invention is performed on the premise that the generated parallelized program is executed on a multicore processor RP-X illustrated in
First, the parallelism of Task15 is analyzed. Process steps 1901 to 1908 of the compiler in the parallelism analysis are the same as the process steps of the conventional OSCAR compiler illustrated in
The execution cost of each macro task illustrated in
After the generation of the MTG of Task15main, the compiler advances to “restructuring including conditional branch copying” in step 2909 in
As illustrated in
In the case where conditional branches and assignment statements continue in the structure of the program with no large loop processing, a parallelization compiler that uses the conventional parallelism extraction method has no choice but to perform dynamic scheduling, as mentioned earlier. As can be seen from
It is therefore important to apply static scheduling by using coarse grain parallelization using parallelism among functions or using (near-fine-grain) parallelization using parallelism of assignment statements in order to parallelize the program.
The following describes inline expansion in next step 19072 in the restructuring performed on the original program of sequential processing for improved parallelism.
First, for effective use of parallelism included in sb4 and sb7 in
To shorten the parallel processing time in the MTG after the inline expansion, each conditional branch on the path (critical path) indicating the longest processing time on the MTG is extracted (step 19073), and parallelism among a plurality of macro tasks (i.e. no data dependency among the macro tasks) following a conditional branch from among the extracted conditional branches is extracted (step 19074). The conditional branch is copied based on the extracted parallelism (step 29075).
In the example of the original program used in this embodiment, sb7 is present in the conditional branch. Therefore, even when sb7 is inline-expanded, the inline expansion results are contained within one conditional branch and assigned to a processor as one macro task. Accordingly, to extract parallelism in the conditional branch, the compiler copies the conditional branch. Take, for example, a conditional branch illustrated in
In the state illustrated in
Accordingly, after the MTG is generated from the MFG in
Process flow in the case where parallelism extraction and parallelized program generation by restructuring including conditional branch copying are performed by the compiler according to the present invention has been described above. Conditional branch copying executed here is briefly described below, using a specific example.
In the MTG before conditional branch copying in
Thus, in the MTG after conditional branch copying in
Before branch copying sb6(func5)→Branch sb9
Before branch copying sb7(func6)→After branch copying sb13
Before branch copying sb10(func3)→After branch copying sb16
[Performance Evaluation]
The program obtained by parallelizing the vehicle engine control program described in the embodiment using the parallelism extraction method according to the present invention is executed on the embedded multicore processor RP-X to evaluate its parallel processing performance.
The structure of the embedded multicore processor RP-X used for performance evaluation on the engine control program parallelized by the above-mentioned method is described first.
As illustrated in
Memory in each general-purpose processor core includes an instruction cache (32 KB), a data cache (32 KB), local memory (ILM, DLM: 16 KB), distributed shared memory (URAM: 64 KB), and a data transfer unit. The accelerator cores are accelerators without controllers, and are connected to an on-chip bus (SHwy#1).
Given that 2-core multicore processors have been studied in current engine control systems, 2 SH-4A cores as general-purpose processor cores are used as computation resources in this example Performance is evaluated while fixing the operating frequency of the bus at 324 MHz when changing the operating frequency of the general-purpose cores in order of 648 MHz, 324 MHz, 162 MHz, and 81 MHz. The reason for fixing the operating frequency of the bus and decreasing the operating frequency of the general-purpose cores is to relatively reduce memory access latency, thus bring memory access latency closer to that in the environment of small in-vehicle microcomputers.
The following describes the parallel processing performance evaluation condition on the embedded multicore processor RP-X.
Global variables are typically arranged in the off-chip shared memory. In this case, data can be read in 1 cycle at a cache hit, but 55 cycles are needed to read data at a cache miss. This penalty is significant in programs that run on the order of microseconds such as the engine control program. It is therefore important to arrange global variables in the local memory with low memory access latency. If all global variables are arranged in the local memory, however, the memory capacity is exceeded. Only global variables (about 7.5 Kbytes) without initial values are accordingly arranged in the local memory, so as not to exceed the memory capacity. Besides, arranging synchronization variables for synchronization among processor cores in the off-chip shared memory has significant memory access latency penalty, so that synchronization variables are arranged in the distributed shared memory with low latency. This enables faster processing.
The performance in the case where all global variables are arranged in the shared memory and the performance in the case where part of the global variables are arranged in the local memory and the synchronization variables for synchronization among the processor cores are arranged in the distributed shared memory are evaluated to compare performance depending on memory arrangement.
The following describes the parallel processing performance evaluation result on the embedded multicore processor RP-X.
The foregoing example of the present invention describes the parallelism extraction method which is a feature of the present invention and the program parallelization method using the parallelism extraction method in the case of parallelizing the vehicle engine control program of sequential processing and executing it on the multicore processor. Moreover, after the inline expansion of functions with relatively high execution cost and the parallelism extraction including conditional branch copying are performed to extract parallelism in the original program of sequential processing and the task fusion for applying static scheduling is performed using the compiler according to the present invention, that is, after the original program of sequential processing is restructured, the parallelized program is generated and its parallel processing performance is evaluated on the embedded multicore processor. As a result, in the case where 2 processor cores are used in the vehicle engine control program which has been extremely difficult to be parallelized with conventionally no example of success in parallelization on a multicore processor, performance is improved 1.71 times at 162 MHz in scenario 1, as compared with the case where 1 processor core is used.
This example demonstrates that faster processing can be achieved through parallelization by the compiler, with it being possible to automatically parallelize and speed up the vehicle engine control program. Thus, the method according to the present invention enables an increase in speed by parallel processing, even in a program having many conditional branches and assignment statements such as a vehicle engine control program or a typical control program.
Though the present invention has been described in detail with reference to the attached drawings, the present invention is not limited to such specific structures, and includes various changes and equivalent structures within the scope of the attached claims.
The following are typical aspects of the present invention other than those described in the claims.
(1) A control method of a multicore processor including a plurality of processor cores,
wherein a program executed by the plurality of processor cores includes a set of one or more conditional branches, and
wherein the method controls the multicore processor so that:
two or more processor cores each execute at least one set of a plurality of conditional branches; and
the two or more processor cores each execute one or more macro tasks to be executed after a same condition of the executed set of conditional branches is satisfied.
(2) A method of producing, by a computer, a program executable on a multicore processor including a plurality of processor cores from an original program,
wherein a set of conditional branches having no data dependency among a plurality of macro tasks determined to be executed in a same condition is extracted from the original program,
wherein the extracted set of conditional branches is copied, and
wherein the copied set of conditional branches is assigned to be executed by each of two or more processor cores, to produce the executable program.
(3) A control method of a multicore processor including a plurality of processor cores,
wherein a program executed by the plurality of processor cores includes a set of one or more conditional branches, and
wherein the method controls the multicore processor so that:
one or more processor cores each execute at least one set of one or more conditional branches; and
the one or more processor cores each execute one or more macro tasks to be executed after a same condition of the executed set of conditional branches is satisfied.
(4) The control method according to (3), wherein the set of conditional branches includes one or more branches resulting from one condition determination or one or more conditional branches resulting from one condition determination.
(5) A method of producing, by a computer, a program executable on a multicore processor including a plurality of processor cores from an original program,
wherein a set of conditional branches having no data dependency among a plurality of macro tasks determined to be executed in a same condition is extracted from the original program,
wherein the extracted set of conditional branches is copied, and
wherein the copied set of conditional branches is assigned to be executed by each of one or more processor cores, to produce the executable program.
(6) The method of producing a program according to (5), wherein the set of conditional branches includes one or more branches resulting from one condition determination or one or more conditional branches resulting from one condition determination.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013-010194 | Jan 2013 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2014/050517 | 1/15/2014 | WO | 00 |
