Patent Application
20070283215
For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the accompanying drawings and detailed description, wherein like reference numerals represent like parts:
It should be understood at the outset that although several illustrative embodiments are described below, the present disclosure may be implemented using any number of techniques whether currently known or later developed. The present disclosure should in no way be limited to the illustrative embodiments described and illustrated herein, and may be modified within the scope of the appended claims along with their full scope of equivalents.
Certain terms are used throughout the following claims and discussion to refer to particular system components. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including but not limited to”. Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. Additionally, the term “system” refers to a collection of two or more hardware components, and may be used to refer to an electronic device or circuit, or a portion of an electronic device or circuit.
A low-density parity-check (“LDPC”) code is a type of redundant code that enables accurate detection and correction of the bits of signals sent over a communication channel. The “parity-check” adjectives refer to verifying the transmission using a matrix H, which defines the code, in conjunction with the parity bits to detect and correct errors. The “low-density” adjectives refer to the sparsity of H. Any sparse matrix, including H, has zero for the value of the majority of its elements.
The matrix H is designed such that a zero matrix results when H is multiplied by t, as described by the equation
Ht=0, (1)
wherein t is a non-erroneous, or valid, set of bits. Hence, whenever Ht≠0, it is known that t contains erroneous bits. Each set t consists of the source message, s, combined with the corresponding parity-check bits for that particular s. When a set t is transmitted, the receiving network element receives a vector r, which is equal to t plus n, as described by the equation
r=t+n, (2)
wherein n is the noise added by the channel. Because an LDPC decoder at the receiver designed to recognize the coding scheme, and hence matrix H, it can compute a vector z=Hr. Because r=t+n, and because Ht=0, the vector z is computed using the equation
z=Hr=Ht+Hn=Hn. (3)
The decoding process thus involves finding the sparsest vector x that satisfies the equation:
Hx=z. (4)
The decoding process involves the iterative manipulation of the signal vector expressed as fractional values in several bits. In at least some preferred embodiments, parity check matrix H is arranged into a composite of circularly shifted identity matrices. This composite is represented by a macro matrix Hm, with a 1 value symbolizing a q×q circularly shifted identity matrix and a 0 value symbolize a q×q zero matrix.
In at least some preferred embodiments, the number of alignment units 104 is equal to the maximum row weight in macro matrix Hm, which is equal to the maximum row weight of parity-check matrix H, used by the decoder. The maximum row weight of Hm (as well as H) is the number of non-zero elements appearing in the row with the maximum number of non-zero elements. Because the number of CSUs 102 is equal to the number of columns in Hm, the maximum row weight is preferably less than the number of CSUs 102. In various embodiments, the number of CSUs is less than the number of columns in Hm.
In other preferred embodiments, the number of alignment units 104 is not equal to the number of reverse alignment units 106, but both numbers are less than the number of column store units 102. In yet other preferred embodiments, the number of alignment units 104 and the number of reverse alignment units 106 are greater than the maximum row weight, but less than the number of column store units 102.
For well-defined, low-density parity-check codes, there is a large discrepancy between the maximum row weight of Hm and number of columns in Hm. Exploiting this characteristic by implementing the described embodiments allows for reduction of logic complexity due to a reduction in both the number of alignment units 104 and reverse alignment units 106. A reduction of this type is significant because for macro matrices with a large number of columns, and hence a large number of CSUs 102, the duplication of alignment units 104 and reverse alignment units 106 in order to maintain a one-to-one ratio with the CSUs 102 constitutes a large source of redundancy in the decoder. Depending upon how many units are excised, the described embodiments can eliminate hundreds of thousands to millions of logic gates as compared to designs that maintain a one-to-one ratio. For instance, applying the described architecture to the WiMax (802.16e) context, the number of alignment/reverse alignment pairs can be reduced, saving about 120,000 logic gates. The broad nature of this efficiency boosting implementation allows the architecture to be applied to a decoder used for a variety of code rates and sizes. A code rate is a ratio of non-redundant bits and total bits per message, e.g., ⅓. A code size is the number of columns in the matrix H and can vary over a large range depending on the complexity of the encoding and number of bits in the message.
At block 206, each column store unit 102 keeps a current estimate of bits of the wide word by storing the intrinsic information of these bits with the extrinsic information of these bits passed to it by the router 108. The number of column store units 102 is greater than the number of alignment units 104. At block 208, reverse alignment is performed by the reverse alignment bank 118. The reverse router 110 passes data to the reverse alignment units 106, which generate the memory read addresses. Next, a shuffle network 114 manipulates the data to the format required by the data path, signaling the end of the method 210.
In at least some preferred embodiments, the column store units 102 outnumber the reverse alignment units 106. Also, the number of alignment units 104 equals the number of reverse alignment units 106, and the number of alignment units equals a maximum row weight of the parity-check matrix used by the decoder. In other preferred embodiments, the number of alignment units 104 is not equal to the number of reverse alignment units 106, but both are less than the number of column store units 102.
While several embodiments have been provided in the present disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented.
Also, techniques, systems, subsystems and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as directly coupled or communicating with each other may be coupled through some interface or device, such that the items may no longer be considered directly coupled to each other but may still be indirectly coupled and in communication, whether electrically, mechanically, or otherwise with one another. Other examples of changes, substitutions, and alterations will become apparent to those skilled in the art. It is intended that the following claims be interpreted to embrace all such changes, substitutions, and alterations.
This application claims priority to U.S. Provisional Patent Application No. 60/746,552, Entitled “Interconnect-Efficient, Complexity-Reduced Layered Architecture Of Low Density Parity Check (LDPC) Decoder,” filed on May 5, 2006, incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60746552 | May 2006 | US |
