Patent Application
20240020248
Embodiments generally relate to data handling in artificial intelligence (AI) compute operations. More particularly, embodiments relate to optimized partial data handling hardware for real world AI applications with N-dimensional scene understanding.
Many real world problems such as autonomous driving, automated machines, remote sensing, augmented reality (AR), virtual reality (VR), etc., involve understanding three-dimensional (3D) geometry and the semantics of a scene. The underlying 3D data is often in the form of a point cloud or voxels that provides a natural and expressive representation of a 3D scene. State of the art deep learning methods for different 3D scene understanding tasks may perform multiply and accumulate (MAC) operations directly on 3D point clouds that are spatially sparse (e.g., as much as 95% of the points contain no data). The spatial sparsity in 3D data results in irregular data accesses and compute patterns leading to poor utilization and energy efficiency problems in CPU (central processing unit, e.g., host processor) and/or GPU (graphics processing unit) based implementations.
While recent developments may have been made in using sparse accelerator hardware to convert/rearrange the sparse data into a dense metadata format, there remains considerable room for improvement. More particularly, with this metadata format, the utilization and energy efficiency problems are addressed to some extent but eventually two additional problems result: 1) increased occurrence of memory transactions due to limited data reuse and 2) increased partial data (e.g., data associated intermediate MAC operations). The increased memory transactions may have a negative impact on performance (e.g., compute utilization) and solutions to handling the increased partial data typically lead to increased circuit area and/or power consumption.
The various advantages of the embodiments will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:
As already noted, deep learning methods for different three-dimensional (3D) scene understanding tasks may perform multiply and accumulate (MAC) operations directly on 3D point clouds that are spatially sparse, wherein the spatial sparsity in 3D data results in irregular data accesses and compute patterns leading to poor utilization and energy efficiency problems. Using a sparse accelerator (e.g., pre-processor hardware module) to convert/rearrange the sparse data into a dense metadata format may result in an increased occurrence of memory transactions due to limited data reuse and increased amounts of partial data (e.g., data associated intermediate MAC operations).
Attempting to optimize scheduling for data reuse may result in an even greater amount partial data. To handle partial data, hardware may either use a local temporary memory (e.g., scratchpad) or rely on existing memory in the memory hierarchy to perform read-accumulate-write operations. For a given application space and with such a metadata structure, it may not be possible to restrict the partial data generation to a limited output space (e.g., the data can scatter to any output channel of the Output Feature Map/OFM). Accordingly, adding a temporary memory can limit the overall performance (e.g., frequent stalls will be issued to the compute engines once the temporary memory is full). Frequent reading and writing to the memory also increases the overall power budget. Since in real world artificial intelligence (AI) problems such as autonomous driving, automated machines, remote sensing, augmented reality (AR), virtual reality (VR), etc., the amount of the data to be processed is substantial, and partial data handling becomes even more critical. Moreover, with an increase in the dimensionality (e.g., from 3D to four-dimensional/4D and/or five-dimensional/5D), the relationship between input and output voxel also increases exponentially, which in turn leads to more partial data to handle.
The technology described herein provides an on-the-fly partial data handling approach and an efficient hardware solution to support the data handling. The performance of the proposed hardware does not depend on the exact dimension of the application (N-dimensional scene understanding). The technology described herein does not incorporate extra memory, increase memory transactions, or stall the compute engines (e.g., processing engines/MAC engines). Further, the technology described herein does not have a negative impact on performance, area or power when deployed with existing sparse hardware in this domain.
Embodiments include hardware that handles the accumulation of partial data efficiently for N-dimensional scene understanding. More particularly, the technology described herein includes a check buffer having a set of registers arranged in a pipelined fashion (e.g., Stage 1 to Stage n) and one or more control blocks to navigate the data flow through the stages. The control block(s) keeps track of addresses corresponding to the data in the check buffer. If any address of the incoming partial data matches with any address in the check buffer, those entries are removed (e.g., “popped”) from the pipeline (e.g., irrespective of their current position in the pipe), accumulated and inserted (e.g., fed back) to the tail (e.g., Stage 1) of the pipeline. This approach ensures that the check buffer pipeline contains only unique entries of the partial data, with the most updated values.
Such an approach is different from a bypass network, which can only pop the data on the head of pipeline. Bypass networks are typically used in general-purpose execution engines that can send the output data directly back to the input of another or same compute unit without being written to the memory. A bypass network/engine cannot trace the addresses of all the entries anywhere in the pipeline to pop and accumulate the entries before sending the accumulated results back to the tail of the pipeline. Rather, the head (e.g., Stage n) of the check buffer sends a request to the memory to obtain a previous partial result, wherein the check buffer writes the most updated partial data to the memory after accumulating partial data from the memory with the partial data from the pipeline.
In the enhanced partial accumulation 22, a first result 34 of a first POC (“POC1” containing partial data) enters a pipeline at a first stage (“Stage1”, e.g., tail of the pipeline) during a first cycle. The illustrated first result 34 of the POC1 propagates through the pipeline and a second result 36 of the POC1 (e.g., containing additional partial data) enters the pipeline at the first stage during a fourth cycle. Rather than continuing to propagate through the pipeline, the first result 34 of the POC1 and the second result 36 of the POC1 are removed (e.g., popped) from the pipeline and combined (e.g., accumulated, summed) together to obtain an accumulated result 38 (e.g., accumulated partial data). The accumulated result 38 is inserted back into the pipeline at a subsequent stage (e.g., second stage/“Stage2” after the initial stage) during a fifth cycle. Thus, the accumulation is achieved locally without conducting a memory read request, response or write request transaction as in the traditional partial accumulation 20. Rather, such memory transactions are only conducted when a result of a POC (e.g., “POC4”) reaches the head of the pipeline without matching another result in the pipeline (“pipe”). Similar benefits are achieved with respect to the partial data results of a second POC (“POC2”) in the illustrated example.
Turning now to
As will be discussed in greater detail, embodiments include a check buffer, which is hardware that can perform on-the-fly partial data accumulation by tracing the addresses of all the entries in the pipeline. If a match is found, the check buffer pops the entries irrespective of their position in the pipeline and feeds the popped entries to the tail of the pipeline after accumulation. Also, if all requirements are clear, the check buffer can initiate a memory request to accumulate partial data from the memory with the partial data from the pipeline and write the updated data back to the memory.
Embodiments also include “check buffer inter” hardware that can perform on-the-fly partial data accumulation for a multicycle latency memory with a check buffer. All operations in the check buffer remain intact, but while sending the memory request for an entry at the head of the pipeline, the check buffer will look for a clear signal from the check buffer inter. Otherwise, the data will be circulated back to the tail of the check buffer. In one example, the check buffer inter includes a check buffer and a memory latency matching FIFO (first in first out). The check buffer inter can trace the addresses for data across all stages of the pipeline similarly to a check buffer and stall the memory request from the check buffer for those entries for which a memory read request is already issued or read/write requests are inflight (e.g., avoiding read before write type of hazards).
More particularly, for any system with memory latency greater than one, the check buffer inter is introduced. The check buffer inter includes a check buffer and a memory read/write latency FIFO (first in first out) to avoid “read before write” types of hazards. This latency protection is achieved by stalling the check buffer from sending the memory request again to the same entry for which a read/write request is already inflight and gives more flexibility to merge large amounts of partial data locally before writing back to the memory. Once stalled by the check buffer inter for the above-mentioned scenario, the data from the head of the check buffer is circulated back to the tail of the pipeline to unblock the further pipeline progress. Sending the accumulated or stalled partials back to the tail of the pipeline provides time to accumulate more partial data before writing the accumulated data back to the memory while also not stalling unique requests behind an inflight request. Connecting check buffer and check buffer inter instances back-to-back provides a relatively deeper pipeline to make on-the-fly accumulation even more effective.
Turning now to
A check buffer 66 is responsible for local accumulation of the partial data inside both the collision section 62 as well as the no collision section 64 (e.g., using two independent instances). Once the check buffer 66 ensures that none of the partial data belonging to the same address are in the pipeline, the data at the head (e.g., Stage n) of the check buffer 66 is passed on to the next phase of the memory interface 50. If the check buffer 66 is inside the collision section 62, the data and address of the partial data at the head (Stage n) is passed on to the no collision section 64. If the check buffer 66 is inside the no collision section 64, the data and address of the partial data at the head (Stage n) are passed on to a check buffer inter 68.
The check buffer inter 68 functions similar to that of the check buffer 66 by performing on-the-fly accumulation. In addition, however, the check buffer inter 68 accounts for the L1 memory 54 read/write latency to ensure that the most updated partial data is written to the memory 54 without any read before write kind of hazard. An accumulator 70 associated with the check buffer inter 68 accumulates partial data from the memory 54 with updated partial data from the pipeline in the check buffer inter 68. Address generation and memory arbitration are handled by an address generator 72 and a control and arbiter 74, respectively. The collision section 62 and the no collision section 64, along with the check buffer inter 68 are instantiated once per memory port to match the targeted throughput.
With continuing reference to
With continuing reference to
With continuing reference to
Another benefit provided by the technology described herein is less circuit area. For example, a local memory module deep enough and wide enough to support the partial data would be significantly larger than a check buffer with enough stages to support the same amount of partial data. Similarly, a local memory with extra depth to account for L1 memory read-write latency would be significantly larger than a check buffer inter as described herein. Other benefits provided by the technology described herein include reduced overall execution time of the workload (e.g., enabled by on-the-fly accumulation and the bypassing of frequent memory accesses) and less power consumption (e.g., providing suitability for lower power applications). The technology described herein also provides significant advantages in terms of compute utilization and reduction in memory transactions across different workloads.
Computer program code to carry out operations shown in the method 120 can be written in any combination of one or more programming languages, including an object oriented programming language such as JAVA, SMALLTALK, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. Additionally, logic instructions might include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, state-setting data, configuration data for integrated circuitry, state information that personalizes electronic circuitry and/or other structural components that are native to hardware (e.g., host processor, central processing unit/CPU, microcontroller, etc.).
Illustrated processing block 122 provides for removing first intermediate partial data and first incoming partial data from a first pipeline of a first check buffer in response to a first accumulation condition in which the first intermediate partial data and the first incoming partial data share a first address in a memory. In one example, block 122 removes the first intermediate partial data from an intermediate stage of the first pipeline and removes the first incoming partial data from an initial stage (e.g., Stage 1) of the first pipeline. In an embodiment, the first address is in a memory bank collision state (e.g., the first address targets the same memory bank as another address currently being processed). Block 124 combines (e.g., adds, accumulates) the first intermediate partial data and the first incoming partial data to obtain first accumulated partial data and block 126 inserts the first accumulated partial data into the first pipeline. In one example, block 126 inserts the first accumulated partial data into a subsequent stage (e.g., Stage 2) after the initial stage of the first pipeline. The method 120 therefore enhances performance at least to the extent that using the check buffer to accumulate intermediate partial data reduces memory transactions, increases compute utilization (e.g., through reduced back pressure on the compute engines), reduces circuit area, improves multi-ported memory scalability, decreases overall execution time and/or decreases power consumption.
Illustrated processing block 132 provides for removing second intermediate partial data and second incoming partial data from a second pipeline of a second check buffer in response to a second accumulation condition in which the second intermediate partial data and the second incoming partial data share a second address in memory, wherein the second address is in the memory bank non-collision state. Block 134 combines (e.g., adds, accumulates) the second intermediate partial data and the second incoming partial data to obtain second accumulated partial data and block 136 inserts the second accumulated partial data into the second pipeline (e.g., at or near the tail of the second pipeline). The method 130 therefore enhances performance at least to the extent that using the check buffer to accumulate intermediate partial data reduces memory transactions, increases compute utilization (e.g., through reduced back pressure on the compute engines), reduces circuit area, improves multi-ported memory scalability, decreases overall execution time and/or decreases power consumption.
Illustrated processing block 142 removes third outgoing partial data from a third pipeline of a third check buffer in response to a latency condition in which the third outgoing partial data is associated with a pending memory transaction (e.g., read latency register and/or write latency register). Block 144 inserts the third accumulated partial data into an initial stage of the third pipeline. The method 140 therefore further enhances performance at least to the extent that feeding the outgoing partial data back into the pipeline avoids read before write types of hazards (e.g., ensuring that only the latest updated partial data from the check buffer inter is accumulated with the corresponding entry of the partial data from the memory).
Illustrated processing block 152 provides for provides for removing third intermediate partial data and third incoming partial data from the third pipeline of the third check buffer in response to a third accumulation condition in which the third intermediate partial data and the third incoming partial data share a third address in memory. Block 154 combines (e.g., adds, accumulates) the third intermediate partial data and the third incoming partial data to obtain third accumulated partial data and block 156 inserts the third accumulated partial data into the third pipeline (e.g., at or near the tail of the third pipeline). The method 150 therefore enhances performance at least to the extent that using the check buffer to accumulate intermediate partial data reduces memory transactions, increases compute utilization (e.g., through reduced back pressure on the compute engines), reduces circuit area, improves multi-ported memory scalability, decreases overall execution time and/or decreases power consumption.
Turning now to
In the illustrated example, the system 280 includes a host processor 282 (e.g., central processing unit/CPU) having an integrated memory controller (IMC) 284 that is coupled to a system memory 286 (e.g., dual inline memory module/DIMM including a plurality of DRAMs). In an embodiment, an IO (input/output) module 288 is coupled to the host processor 282. The illustrated IO module 288 communicates with, for example, a display 290 (e.g., touch screen, liquid crystal display/LCD, light emitting diode/LED display), mass storage 302 (e.g., hard disk drive/HDD, optical disc, solid state drive/SSD) and a network controller 292 (e.g., wired and/or wireless). The host processor 282 may be combined with the IO module 288, a graphics processor 294, and an AI accelerator 296 (e.g., specialized processor) into a system on chip (SoC) 298. In an embodiment, the AI accelerator 296 includes a sparse accelerator 300, an L1 memory 306 and logic 304 (e.g., memory interface including one or more of configurable or fixed-functionality hardware) coupled to the sparse accelerator 300 and the L1 memory 306.
The logic 304 performs one or more aspects of the method 120 (
The logic 354 may be implemented at least partly in configurable or fixed-functionality hardware. In one example, the logic 354 includes transistor channel regions that are positioned (e.g., embedded) within the substrate(s) 352. Thus, the interface between the logic 354 and the substrate(s) 352 may not be an abrupt junction. The logic 354 may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate(s) 352.
The processor core 400 is shown including execution logic 450 having a set of execution units 455-1 through 455-N. Some embodiments may include a number of execution units dedicated to specific functions or sets of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic 450 performs the operations specified by code instructions.
After completion of execution of the operations specified by the code instructions, back end logic 460 retires the instructions of the code 413. In one embodiment, the processor core 400 allows out of order execution but requires in order retirement of instructions. Retirement logic 465 may take a variety of forms as known to those of skill in the art (e.g., re-order buffers or the like). In this manner, the processor core 400 is transformed during execution of the code 413, at least in terms of the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic 425, and any registers (not shown) modified by the execution logic 450.
Although not illustrated in
Referring now to
The system 1000 is illustrated as a point-to-point interconnect system, wherein the first processing element 1070 and the second processing element 1080 are coupled via a point-to-point interconnect 1050. It should be understood that any or all of the interconnects illustrated in
As shown in
Each processing element 1070, 1080 may include at least one shared cache 1896a, 1896b. The shared cache 1896a, 1896b may store data (e.g., instructions) that are utilized by one or more components of the processor, such as the cores 1074a, 1074b and 1084a, 1084b, respectively. For example, the shared cache 1896a, 1896b may locally cache data stored in a memory 1032, 1034 for faster access by components of the processor. In one or more embodiments, the shared cache 1896a, 1896b may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.
While shown with only two processing elements 1070, 1080, it is to be understood that the scope of the embodiments are not so limited. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of processing elements 1070, 1080 may be an element other than a processor, such as an accelerator or a field programmable gate array. For example, additional processing element(s) may include additional processors(s) that are the same as a first processor 1070, additional processor(s) that are heterogeneous or asymmetric to processor a first processor 1070, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processing element. There can be a variety of differences between the processing elements 1070, 1080 in terms of a spectrum of metrics of merit including architectural, micro architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processing elements 1070, 1080. For at least one embodiment, the various processing elements 1070, 1080 may reside in the same die package.
The first processing element 1070 may further include memory controller logic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, the second processing element 1080 may include a MC 1082 and P-P interfaces 1086 and 1088. As shown in
The first processing element 1070 and the second processing element 1080 may be coupled to an I/O subsystem 1090 via P-P interconnects 10761086, respectively. As shown in
In turn, I/O subsystem 1090 may be coupled to a first bus 1016 via an interface 1096. In one embodiment, the first bus 1016 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the embodiments are not so limited.
As shown in
Note that other embodiments are contemplated. For example, instead of the point-to-point architecture of
Example 1 includes a performance-enhanced computing system comprising a sparse accelerator, a memory, and a memory interface coupled to the sparse accelerator and the memory, the memory interface including logic coupled to one or more substrates, wherein the logic includes a first check buffer to remove first intermediate partial data and first incoming partial data from a first pipeline of the first check buffer in response to a first accumulation condition in which the first intermediate partial data and the first incoming partial data share a first address in the memory, combine the first intermediate partial data and the first incoming partial data to obtain first accumulated partial data, and insert the first accumulated partial data into the first pipeline.
Example 2 includes the computing system of Example 1, wherein the first intermediate partial data is removed from an intermediate stage of the first pipeline and the first incoming partial data is removed from an initial stage of the first pipeline.
Example 3 includes the computing system of Example 2, wherein the first accumulated partial data is inserted into a subsequent stage after the initial stage of the first pipeline.
Example 4 includes the computing system of any one of Examples 1 to 3, wherein the first address is to be in a memory bank collision state.
Example 5 includes the computing system of Example 4, wherein the logic further includes a second check buffer, the second check buffer to remove second intermediate partial data and second incoming partial data from a second pipeline of the second check buffer in response to a second accumulation condition in which the second intermediate partial data and the second incoming partial data share a second address in the memory, wherein the second address is to be in a memory bank non-collision state, combine the second intermediate partial data and the second incoming partial data to obtain second accumulated partial data, and insert the second accumulated partial data into the second pipeline.
Example 6 includes the computing system of any one of Examples 1 to 4, wherein the logic further includes a third check buffer, the third check buffer to remove third outgoing partial data from a third pipeline of the third check buffer in response to a latency condition in which the third outgoing partial data is associated with a pending memory transaction, insert the third outgoing partial data into an initial stage of the third pipeline, remove third intermediate partial data and third incoming partial data from the third pipeline in response to a third accumulation condition in which the third intermediate partial data and the third incoming partial data share a third address in the memory, combine the third intermediate partial data and the third incoming partial data to obtain third accumulated partial data, and insert the third accumulated partial data into the third pipeline.
Example 7 includes a semiconductor apparatus comprising one or more substrates, and logic coupled to the one or more substrates, wherein the logic includes a first check buffer and is implemented at least partly in one or more of configurable or fixed-functionality hardware, the first check buffer to remove first intermediate partial data and first incoming partial data from a first pipeline of the first check buffer in response to a first accumulation condition in which the first intermediate partial data and the first incoming partial data share a first address in a memory, combine the first intermediate partial data and the first incoming partial data to obtain first accumulated partial data, and insert the first accumulated partial data into the first pipeline.
Example 8 includes the semiconductor apparatus of Example 7, wherein the first intermediate partial data is removed from an intermediate stage of the first pipeline and the first incoming partial data is removed from an initial stage of the first pipeline.
Example 9 includes the semiconductor apparatus of Example 8, wherein the first accumulated partial data is inserted into a subsequent stage after the initial stage of the first pipeline.
Example 10 includes the semiconductor apparatus of any one of Examples 7 to 9, wherein the first address is to be in a memory bank collision state.
Example 11 includes the semiconductor apparatus of Example 10, wherein the logic further includes a second check buffer, the second check buffer to remove second intermediate partial data and second incoming partial data from a second pipeline of the second check buffer in response to a second accumulation condition in which the second intermediate partial data and the second incoming partial data share a second address in the memory, wherein the second address is to be in a memory bank non-collision state, combine the second intermediate partial data and the second incoming partial data to obtain second accumulated partial data, and insert the second accumulated partial data into the second pipeline.
Example 12 includes the semiconductor apparatus of any one of Examples 7 to 10, wherein the logic further includes a third check buffer, the third check buffer to remove third outgoing partial data from a third pipeline of the third check buffer in response to a latency condition in which the third outgoing partial data is associated with a pending memory transaction, and insert the third outgoing partial data into an initial stage of the third pipeline.
Example 13 includes the semiconductor apparatus of Example 12, wherein the third check buffer is further to remove third intermediate partial data and third incoming partial data from the third pipeline in response to a third accumulation condition in which the third intermediate partial data and the third incoming partial data share a third address in the memory, combine the third intermediate partial data and the third incoming partial data to obtain third accumulated partial data, and insert the third accumulated partial data into the third pipeline.
Example 14 includes at least one computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to remove, by a first check buffer, first intermediate partial data and first incoming partial data from a first pipeline of the first check buffer in response to a first accumulation condition in which the first intermediate partial data and the first incoming partial data share a first address in a memory, combine, by the first check buffer, the first intermediate partial data and the first incoming partial data to obtain first accumulated partial data, and insert, by the first check buffer, the first accumulated partial data into the first pipeline.
Example 15 includes the at least one computer readable storage medium of Example 14, wherein the first intermediate partial data is removed from an intermediate stage of the first pipeline and the first incoming partial data is removed from an initial stage of the first pipeline.
Example 16 includes the at least one computer readable storage medium of Example 15, wherein the first accumulated partial data is inserted into a subsequent stage after the initial stage of the first pipeline.
Example 17 includes the at least one computer readable storage medium of any one of Examples 14 to 16, wherein the first address is to be in a memory bank collision state.
Example 18 includes the at least one computer readable storage medium of Example 17, wherein the instructions, when executed, further cause the computing system to remove, by a second check buffer, second intermediate partial data and second incoming partial data from a second pipeline of the second check buffer in response to a second accumulation condition in which the second intermediate partial data and the second incoming partial data share a second address in the memory, wherein the second address is to be in a memory bank non-collision state, combine, by the second check buffer, the second intermediate partial data and the second incoming partial data to obtain second accumulated partial data, and insert, by the second check buffer, the second accumulated partial data into the second pipeline.
Example 19 includes the at least one computer readable storage medium of any one of Examples 14 to 17, wherein the instructions, when executed, further cause the computing system to remove, by a third check buffer, third outgoing partial data from a third pipeline of the third check buffer in response to a latency condition in which the third outgoing partial data is associated with a pending memory transaction, and insert, by the third check buffer, the third outgoing partial data into an initial stage of the third pipeline.
Example 20 includes the at least one computer readable storage medium of Example 19, wherein the instructions, when executed, further cause the computing system to remove, by the third check buffer, third intermediate partial data and third incoming partial data from the third pipeline in response to a third accumulation condition in which the third intermediate partial data and the third incoming partial data share a third address in the memory, combine, by the third check buffer, the third intermediate partial data and the third incoming partial data to obtain third accumulated partial data, and insert, by the third check buffer, the third accumulated partial data into the third pipeline.
Example 21 includes a method of operating a performance-enhanced computing system, the method comprising removing first intermediate partial data and first incoming partial data from a first pipeline of the first check buffer in response to a first accumulation condition in which the first intermediate partial data and the first incoming partial data share a first address in a memory, combining, by the first check buffer, the first intermediate partial data and the first incoming partial data to obtain first accumulated partial data, and inserting, by the first check buffer, the first accumulated partial data into the first pipeline.
Example 22 includes an apparatus comprising means for performing the method of Example 21.
Embodiments may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in hardware, or any combination thereof. For example, hardware implementations may include configurable logic, fixed-functionality logic, or any combination thereof. Examples of configurable logic (e.g., configurable hardware) include suitably configured programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and general purpose microprocessors. Examples of fixed-functionality logic (e.g., fixed-functionality hardware) include suitably configured application specific integrated circuits (ASICs), combinational logic circuits, and sequential logic circuits. The configurable or fixed-functionality logic can be implemented with complementary metal oxide semiconductor (CMOS) logic circuits, transistor-transistor logic (TTL) logic circuits, or other circuits.
Example sizes/models/values/ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the computing system within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
The term “coupled” may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms “first”, “second”, etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.
As used in this application and in the claims, a list of items joined by the term “one or more of” may mean any combination of the listed terms. For example, the phrases “one or more of A, B or C” may mean A; B; C; A and B; A and C; B and C; or A, B and C.
Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments can be implemented in a variety of forms. Therefore, while the embodiments have been described in connection with particular examples thereof, the true scope of the embodiments should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.
