Patent Application
20130071986
This document relates to the subject matter of a joint research agreement between Intermolecular, Inc. and Elpida Memory, Inc.
The present invention generally relates to the field of dynamic random access memory (DRAM), and more particularly to electrode processing for improved DRAM performance.
Dynamic Random Access Memory utilizes capacitors to store bits of information within an integrated circuit. A capacitor is formed by placing a dielectric material between two electrodes formed from conductive materials. A capacitor's ability to hold electrical charge (i.e., capacitance) is a function of the surface area of the capacitor plates A, the distance between the capacitor plates d, and the relative dielectric constant or k-value of the dielectric material. The capacitance of is given by:
where εo represents the vacuum permittivity.
The dielectric constant is a measure of a material's polarizability. Therefore, the higher the dielectric constant of a material, the more charge the capacitor can hold. Therefore, if the k-value of the dielectric is increased, the area of the capacitor can be decreased and maintain the desired cell capacitance. Reducing the size of capacitors within the device is important for the miniaturization of integrated circuits. This allows the packing of millions (mega-bit (Mb)) or billions (giga-bit (Gb)) of memory cells into a single semiconductor device. The goal is to maintain a large cell capacitance (generally ˜10 to 25 fF) and a low leakage current (generally <10−7 A cm−2). The physical thickness of the dielectric layers in DRAM capacitors could not be reduced unlimitedly in order to avoid leakage current caused by tunneling mechanisms which exponentially increases as the thickness of the dielectric layer decreases.
Traditionally, SiO2 has been used as the dielectric material and semiconducting materials (semiconductor-insulator-semiconductor [SIS] cell designs) have been used as the electrodes. The cell capacitance was maintained by increasing the area of the capacitor using very complex capacitor morphologies while also decreasing the thickness of the SiO2 dielectric layer. Increases of the leakage current above the desired specifications have demanded the development of new capacitor geometries, new electrode materials, and new dielectric materials. Cell designs have migrated to metal-insulator-semiconductor (MIS) and now to metal-insulator-metal (MIM) cell designs for higher performance.
Typically, DRAM devices at technology nodes of 80 nm and below use MIM capacitors wherein the electrode materials are metals. These electrode materials generally have higher conductivities than the semiconductor electrode materials, higher work functions, exhibit improved stability over the semiconductor electrode materials, and exhibit reduced depletion effects. The electrode materials must have high conductivity to ensure fast device speeds. Representative examples of electrode materials for MIM capacitors are metals, conductive metal oxides, conductive metal silicides, conductive metal nitrides (i.e. TiN), or combinations thereof. MIM capacitors in these DRAM applications utilize insulating materials having a dielectric constant, or k-value, significantly higher than that of SiO2 (k=3.9). For DRAM capacitors, the goal is to utilize dielectric materials with k values greater than about 40. Such materials are generally classified as high-k materials. Representative examples of high-k materials for MIM capacitors are non-conducting metal oxides, non-conducting metal nitrides, non-conducting metal silicates or combinations thereof. These dielectrics may also include additional dopant materials.
A figure of merit in DRAM technology is the electrical performance of the dielectric material as compared to SiO2 known as the Equivalent Oxide Thickness (EOT). A high-k material's EOT is calculated using a normalized measure of silicon dioxide (SiO2 k=3.9) as a reference, given by:
where d represents the physical thickness of the capacitor dielectric.
As DRAM technologies scale below the 40 nm technology node, manufacturers must reduce the EOT of the high-k dielectric films in MIM capacitors in order to increase charge storage capacity. The goal is to utilize dielectric materials that exhibit an EOT of less than about 0.8 nm while maintaining a physical thickness of about 5-20 nm.
One class of high-k dielectric materials possessing the characteristics required for implementation in advanced DRAM capacitors are high-k metal oxide materials. Titanium dioxide (TiO2) is one metal oxide dielectric material which displays significant promise in terms of serving as a high-k dielectric material for implementation in DRAM capacitors.
The dielectric constant of a dielectric material may be dependent upon the crystalline phase(s) of the material. For example, in the case of TiO2, the anatase crystalline phase of TiO2 has a dielectric constant of approximately 40, while the rutile crystalline phase of TiO2 can have a dielectric constant of approximately >80. Due to the higher-k value of the rutile-phase, it is desirable to produce TiO2 based DRAM capacitors with the TiO2 in the rutile-phase. The relative amounts of the anatase phase and the rutile phase can be determined from x-ray diffraction (XRD). From Eqn. 1 above, a TiO2 layer in the rutile-phase could be physically thicker and maintain the desired capacitance. The increased physical thickness is important for lowering the leakage current of the capacitor. The anatase phase will transition to the rutile phase at high temperatures (>800 C). However, high temperature processes are undesirable in the manufacture of DRAM devices.
The crystal phase of an underlying layer can be used to influence the growth of a specific crystal phase of a subsequent material if their crystal structures are similar and their lattice constants are similar. This technique is well known in technologies such as epitaxial growth. The same concepts have been extended to the growth of thin films where the underlying layer can be used as a “template” to encourage the growth of a desired phase over other competing crystal phases.
Therefore, there is a need to develop a DRAM electrode which promotes the growth of the rutile-phase in a TiO2 dielectric layer during formation of the dielectric layer. Such a DRAM electrode would enable a DRAM capacitor with high cell capacitance, small area, low leakage current, and fast device speed.
Generally, as the dielectric constant of a material increases, the band gap of the material decreases. This leads to high leakage current in the device. As a result, without the utilization of countervailing measures, capacitor stacks implementing high-k dielectric materials may experience large leakage currents. High work function electrodes (e.g., electrodes having a work function of greater than 5.0 eV) may be utilized in order to counter the effects of implementing a reduced band gap high-k dielectric layer within the DRAM capacitor. Metals, such as platinum, gold, ruthenium, and ruthenium oxide are examples of high work function electrode materials suitable for inhibiting device leakage in a DRAM capacitor having a high-k dielectric layer. The noble metal systems, however, are prohibitively expensive when employed in a mass production context. Moreover, electrodes fabricated from noble metals often suffer from poor manufacturing qualities, such as surface roughness, poor adhesion, and form a contamination risk in the fab.
Conductive metal oxides, conductive metal silicides, conductive metal nitrides, or combinations thereof comprise other classes of materials that may be suitable as DRAM capacitor electrodes. Generally, transition metals and their conductive binary compounds form good candidates as electrode materials. The transition metals exist in several oxidation states. Therefore, a wide variety of compounds are possible. Different compounds may have different crystal structures, electrical properties, etc. It is important to utilize the proper compound for the desired application.
In one example of materials suitable for use as DRAM capacitor electrodes, molybdenum has several binary oxides of which MoO2 and MoO3 are two examples. These two oxides of molybdenum have different properties. MoO2 is conductive and has shown great promise as an electrode material in DRAM capacitors. MoO2 has a distorted rutile crystal structure and can serve as an acceptable template to promote the deposition of the rutile-phase of TiO2 as discussed above. MoO2 also has a high work function (can be >5.0 eV depending on process history) which helps to minimize the leakage current of the DRAM device. However, oxygen-rich phases (MoO2+x) of MoO2 degrade the performance of the MoO2 electrode because they act more like insulators and have crystal structures that do not promote the deposition of the rutile-phase of TiO2. For example, MoO3 (the most oxygen-rich phase) is a dielectric material and has an orthorhombic crystal structure.
Generally, a deposited thin film may be amorphous, crystalline, or a mixture thereof. Furthermore, several different crystalline phases may exist. The thin film may exhibit different physical, chemical, and structural properties throughout the thickness of the film following deposition. As an example, the top part of the thin film may exhibit different properties from the bottom part of the film. Therefore, processes (both deposition and post-treatment) must be developed to maximize the formation and uniformity through the depth of the film of crystalline MoO2 and to minimize the presence of MoO2+x phases. The MoO2+x phases may form during the deposition of the electrode and may not be evenly distributed throughout the layer thickness. The MoO2 electrode material may be deposited using any common deposition technique such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PE-ALD), atomic vapor deposition (AVD), ultraviolet assisted atomic layer deposition (UV-ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). Typically, the MoO2 electrode material must be annealed after deposition to fully crystallize the film. Even if the anneal is performed under an inert gas such as nitrogen, the presence of MoO2+x phases are observed and the effective k-value of the TiO2 dielectric subsequently deposited on such an electrode is lower than desired.
Therefore, there is a need to develop methods for producing an electrode system that maximize the presence of crystalline conductive metal oxide layers and promote the growth of the high k phase in a subsequently deposited dielectric layer, while simultaneously providing the high work function and manufacturability characteristics required for next generation DRAM capacitors.
In some embodiments of the present invention, an etch process is performed after the deposition of the electrode layer but before the electrode layer is annealed. The etch step results in a electrode layer with a higher density after the anneal step. The etch step may be any one of a wet etch technique, a reactive ion etch (RIE) technique, or an ion milling etch technique. The technique may be applied to either the first electrode, the second electrode, or both.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The drawings are not to scale and the relative dimensions of various elements in the drawings are depicted schematically and not necessarily to scale.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The drawings are not to scale and the relative dimensions of various elements in the drawings are depicted schematically and not necessarily to scale.
The techniques of the present invention can readily be understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
A detailed description of one or more embodiments is provided below along with accompanying figures. The detailed description is provided in connection with such embodiments, but is not limited to any particular example. The scope is limited only by the claims and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided for the purpose of example and the described techniques may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the embodiments has not been described in detail to avoid unnecessarily obscuring the description.
Those skilled in the art will appreciate that each of the first electrode layer, the dielectric layer, and the second electrode layer may be formed using well known techniques such as ALD, PE-ALD, AVD, UV-ALD, CVD, PECVD, or PVD. Generally, because of the complex morphology of the DRAM capacitor structure, ALD, PE-ALD, AVD, or CVD are preferred methods of formation. However, any of these techniques are suitable for forming each of the various layers discussed below. Those skilled in the art will appreciate that the teachings described below are not limited by the technology used for the deposition process.
In
In the next step, the substrate with first electrode layer, 500, would then be annealed in a reducing atmosphere or an inert atmosphere (i.e. N2 or Ar) to reduce the concentration of the oxygen-rich components. Generally, the reducing atmosphere will comprise H2, or NH3 mixed with an inert gas. A specific example of a reducing atmosphere that is available commercially is forming gas wherein the H2 concentration can range between about 1 and 25% mixed with N2. The annealing in the reducing atmosphere may utilize either thermal energy or plasma energy to activate the reducing atmosphere. Alternatively, the first electrode layer may be annealed using a Rapid Thermal Annealing (RTA) technique wherein the temperature is quickly raised in the presence of a nitrogen containing gas such as N2, forming gas, NH3, etc. Examples of the possible annealing treatments are further described in U.S. application Ser. No. 13/084,666 filed on Apr. 12, 2011, entitled “METHOD FOR FABRICATING A DRAM CAPACITOR” and is incorporated herein by reference.
In the next step, dielectric layer, 504, would then be formed on the annealed first electrode layer, 502. A wide variety of dielectric materials have been targeted for use in DRAM capacitors. Examples of suitable dielectric materials comprise SiO2, a bilayer of SiO2 and SixNy, SiON, Al2O3, HfO2, HfSiOx, ZrO2, Ta2O5, TiO2, SrTiO3 (STO), BaSrTiOx (BST), PbZrTiOx (PZT) or doped versions of the same. These dielectric materials may be formed as a single layer or may be formed as a hybrid or nanolaminate structure. A specific dielectric material of interest is the rutile-phase of TiO2.
In the next step, the second electrode layer, 506, is formed on dielectric layer, 504. The second electrode layer may be a conductive binary metal compound material as described above, a metal, or a combination thereof.
In the next step, the substrate with etched first electrode layer, 602, comprising MoO2 would then be annealed in a reducing atmosphere or an inert atmosphere (i.e. N2 or Ar) to reduce the concentration of the oxygen-rich components and increase the relative amount of MoO2 phases. Typically, the annealing step will be performed in a temperature range between about 400 C and about 650 C. Generally, the reducing atmosphere will comprise H2, or NH3 mixed with an inert gas. A specific example of a reducing atmosphere that is available commercially is forming gas wherein the H2 concentration can range between about 1 and 25% mixed with N2. The annealing in the reducing atmosphere may utilize either thermal energy, plasma energy or RTA to activate the reducing atmosphere. The reducing atmosphere will crystallize the first electrode layer if there is an amorphous component and reduce the MoO2+x species to MoO2. It is desirable that the crystalline MoO2 phase account for ≧40% of the first electrode.
In the next step, dielectric layer, 604, would then be formed on the annealed first electrode layer, 602. In this example, a layer of TiO2 that exists predominantly (>30%) in the rutile-phase is formed as the dielectric layer, 604. The rutile-phase of TiO2 grows preferentially over the anatase-phase due to the distorted rutile-phase crystal structure of the underlying predominantly MoO2 electrode material. The TiO2 layer generally has a physical layer thickness between 5 nm and 20 nm and exhibits a k value of >40.
In the next step, the second electrode layer, 606, is formed on dielectric layer, 604. The second electrode layer may be a conductive binary metal compound material as described above, a metal, or a combination thereof. Although
The effect of the etch step was evaluated through the investigation summarized in Table 1 below. First electrode layers were deposited on a substrate using an ALD technique. The nominal thickness of the as deposited films was in the range of about 30 nm to about 37 nm. The RIE steps were conducted at a power of 250 W for 30 seconds using CHF3. The ion milling steps were conducted at a power of 250 W for 60 seconds using Ar. The Anneal steps were conducted at a temperature of 525 C for 10 minutes in reducing atmospheres of either H2/N2 or H2/Ar. The anneal atmosphere is listed in the parenthesis in the sequence. The data indicate that the as deposited first electrode comprises a mixture of molybdenum oxide phases including MoO2, MoO2+x and MoO3. MoO3 has a bulk density of about 4.7 g/cm3 and is an insulator. MoO2 has a bulk density of about 6.5 g/cm3 and is a good conductor. As illustrated in the comparison between sequences 1) and 2), the post-anneal density for the etched sample (sequence 1) is close to the bulk density of MoO2 while the post-anneal density for the sample that was simply annealed in a reducing atmosphere (sequence 2) showed only a modest increase in density after the anneal and the density is closer to that of MoO3. Additionally, the resistivity for the sample in sequence 2) is very high and is another indication that much of the sample consists of MoO2+x phases. The results are similar when comparing sequences 3) and 4) wherein the annealing atmosphere was changed to H2/Ar. Again, the etched sample (sequence 3) exhibits a high density and low resistivity after the anneal step. The data from sequences 3) and 4) suggest that the H2/Ar annealing atmosphere may be advantageous over the H2/N2 annealing atmosphere. The H2/Ar annealing atmosphere appears to be more effective at removing any MoO2+x phases that might be present. Finally, sequence 5) illustrates that similar results may be obtained by using an ion milling etch step followed by an anneal step in a reducing atmosphere. Similar trends would be expected for wet etch techniques. For example, MoO2+x phases are slightly soluble in water while MoO2 is insoluble in water. Therefore, the MoO2+x phases would be preferentially removed during a wet etch step.
An example of a specific application of some embodiments of the present invention is in the fabrication of capacitors used in the memory cells in DRAM devices. DRAM memory cells effectively use a capacitor to store charge for a period of time, with the charge being electronically “read” to determine whether a logical “one” or “zero” has been stored in the associated cell. Conventionally, a cell transistor is used to access the cell. The cell transistor is turned “on” in order to store data on each associated capacitor and is otherwise turned “off” to isolate the capacitor and preserve its charge. More complex DRAM cell structures exist, but this basic DRAM structure will be used for illustrating the application of this disclosure to capacitor manufacturing and to DRAM manufacturing.
As was described previously in connection with
Although various embodiments that incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.
