Partial Response Transmission System

Abstract

A partial response signaling system includes a transmitter circuit configured to equalize input data in response to a control signal and to transmit a partial response signal through a transmission medium; and a receiver circuit configured to recover an output data from the partial response signal and to generate the control signal based on the partial response signal and an expected signal to output the control signal to the transmitter circuit.

Description

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing an eye opening in a duo-binary signal as an example of the partial response signal;

FIG. 2 is a diagram showing a conventional method of duo-binary signaling as an example of partial response transmission;

FIG. 3 is a block diagram showing a conventional partial response signaling system;

FIG. 4 is a block diagram showing a receiver side FIR filter in the conventional partial response signaling system;

FIG. 5 is a diagram showing conventional sampling timings of the partial response signal;

FIG. 6 is a block diagram showing the configuration of a partial response signaling system according to a first embodiment of the present invention;

FIG. 7 is a block diagram showing an example of a transmitter side equalizing circuit and an output buffer in the partial response signaling system according to the first embodiment of the present invention;

FIG. 8 is a block diagram showing another example of the transmitter side equalizing circuit and the output buffer in the partial response signaling system according to the first embodiment of the present invention;

FIG. 9 is a block diagram showing the configuration of the partial response signaling system according to a second embodiment of the present invention;

FIG. 10 is a block diagram showing the configuration of the partial response signaling system according to a third embodiment of the present invention;

FIG. 11 is a block diagram showing configuration of the partial response signaling system according to a fourth embodiment of the present invention;

FIG. 12 is a block diagram showing the configuration of the partial response signaling system according to a fifth embodiment of the present invention;

FIG. 13 is a diagram showing the effect of a transition guarantee encoding circuit in the partial response signaling system according to the fifth embodiment of the present invention;

FIG. 14 is a block diagram showing the configuration of the partial response signaling system according to a sixth embodiment of the present invention;

FIG. 15 is a diagram showing an example of encoding by a 2-bit transition guarantee encoding circuit in the partial response signaling system according to the sixth embodiment of the present invention;

FIG. 16 is a block diagram showing the configuration of the partial response signaling system according to a seventh embodiment of the present invention;

FIG. 17 is a block diagram showing an example of a clock data recovery circuit in the partial response signaling system of the present invention; and

FIG. 18 is a block diagram showing another example of the clock data recovery circuit in the partial response signaling system of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a partial response signaling system of the present embodiment will be described with reference to the attached drawings.

First Embodiment

FIG. 6 is a block diagram showing configuration of a partial response signaling system according to the first embodiment of the present invention. As shown in FIG. 6, the partial response signaling system has a transmitter circuit 101, a transmission medium 102 and a receiver circuit 103. A data input 104 is equalized and waveform-shaped by a transmitter side equalizing circuit 107, and then outputted to the transmission medium 102 by an output buffer 108, A partial response signal passing through the transmission medium 102 reaches the receiver circuit 103 and is supplied to a clock data recovery circuit 109 and an adaptive equalization control circuit 110 in the receiver circuit 103. The adaptive equalization control circuit 110 of the receiver circuit 103 transmits a control signal 111 determined based on difference data between the signal and an expected partial response signal, to the transmitter side equalizing circuit 107. Thus, the characteristics of the transmitter side equalizing circuit 107 are adjusted. A voltage value of the expected partial response signal is given as analog reference voltage Dn in the adaptive equalization control circuit 110. By comparing this voltage with a voltage Yn of the supplied partial response signal 106, the difference data sign(en) is obtained. That is, the relationship is expressed by the following equation:

sign(e_n)=sign(D_n−Y_n)

In case that the transmitter side equalizing circuit 107 is configured by an FIR filter, algorithm called as Sign-Sign Least Mean Square is used and an adjusting method is expressed by the following equation:

w _n+1 ^k =w _n ^k+μ·sign(e_n)·{circumflex over (x)}_n−kwhere w_n^k is a k-th tap coefficient of the FIR filter and μ is an adjusting step.

• {circumflex over (X)}_n−k is a data output 105 corresponding to the tap coefficient. Through the operation of the above-mentioned equations, the characteristics of the transmitter side equalizing circuit 107 are updated. With such a feedback loop configuration containing such a transmission medium 102, the characteristics of the transmitter side equalizing circuit 107 are optimized so that the expected partial response signal 106 may be obtained as an input of the clock data recovery circuit 109. The clock data recovery circuit 109 obtains the data output 105 through recovery of an optimum timing clock with respect to the partial response signal 106.

However, when the partial response signal 106 generated by using the transmitter side equalizing circuit 107 is optimized, since a signal outputted from the output buffer 108 is supplied to the receiver circuit 103 through the transmission medium 102 having unclear characteristics, it is impossible to uniquely determine how reference level D_n of the expected partial response signal 106 is set. Therefore, a new adjusting mechanism for setting the suitable reference level D_n is required, resulting in complexity of a system and increase in power consumption.

One feature of the partial response signaling system according to the first embodiment of the present invention is in that the difference data sign(e_n) is obtained without adjusting the reference level D_n. The partial response signal 106 has levels of odd number which is generally expressed by 2m−1 or 4m−3 (m=2n, n is a natural number). Thus, when a highest level and a lowest level of the partial response signal 106 are defined as V_max and V_min, respectively, the signal contains a medium level corresponding to V_mid=(V_max+V_min)/2. When the partial response signal is a differential signal, the medium level V_mid is equal to intermediate level of the differential signal and can be uniquely determined on the receiver side irrespective of the characteristics of the transmission medium 102. Comparison with the intermediate level of the differential signal can be easily performed by using a differential decision circuit 112. Therefore, when the data output

• ({circumflex over (x)}_n)105 is V_mid, the difference data,

sign(e_n)=sign(V_mid−Y_n)|{circumflex over (x)}_n=V_mid

is obtained from the differential decision circuit 112 by using the intermediate potential of the difference as a threshold value. Thereby, the characteristics of the transmitter side equalizing circuit 107 are optimized without adjusting the reference signal Dn.

FIG. 7 is a block diagram showing an example of the transmitter side equalizing circuit and the output buffer. The circuit shown in FIG. 7 is a 6-tap FIR filter and has delay circuits (D) 202 to 206 and variable output drivers 207 to 212 corresponding to multiplying circuits and outputting data corresponding to predetermined weights. Since a data input 201 of the transmitter side FIR filter is digital data to be transmitted, the data is always a 1-bit signal. Accordingly, by driving the transmission medium in parallel using the variable output drivers 207 to 212, the 1-bit data supplied to each of the drivers can be multiplied and added. Since such combination between the transmitter side equalizing circuit and the output buffer permits waveform shaping without performing multi-bit operations, very high-speed operations can be achieved, thereby obtaining the data output 213.

FIG. 8 shows another example of the transmitter side equalizing circuit and the output buffer. The circuit shown in FIG. 8 is a 6-tap FIR filter and has delay circuits (D) 302 to 307, parallel serial converting circuits (P2S) 308 to 313, and variable output drivers 314 to 319 corresponding to multiplying circuits. A delay circuit sequence is formed for each bit of a parallel data input. The parallel serial converting circuits 308 to 313 include circuits 309, 311, and 313 which receive data from the respective outputs of the corresponding delay circuit sequence and serially output the data. The parallel to serial converting circuits 308 to 313 also include circuits 310, 312 which receive data from the output of the corresponding delay circuit in one delay circuit sequence and the output of the delay circuit previous to the corresponding delay circuit in another delay circuit sequence and serially output the data. The parallel to serial converting circuits 308 to 313 further include the circuit 308 which receives data from the input and the output of the first delay circuit in one delay circuit sequence. The variable output drivers 314 to 319 are provided for the parallel to serial converting circuits (P2S) 308 to 313. This circuit is different from the circuit shown in FIG. 7 in that parallel data inputs 301 supplied in parallel pass through the delay circuits and parallel-serial converted to form input data of the variable output drivers. With such a configuration, the operation speed of the delay circuits 302 to 307 which are often constituted by a flip-flop is reduced to a half. Therefore, with such a circuit configuration, the much faster operation of the transmitter side equalizing circuit can be achieved to obtain the data output 320.

In this manner, by adopting the configuration shown in FIG. 6, the waveform of the partial response signal can be equalized without using a receiver side FIR filter with limited operation speed. For this reason, the high-speed partial response signaling system can be realized.

SECOND EMBODIMENT

FIG. 9 is a block diagram showing the configuration of the partial response signaling system according to the second embodiment of the present invention. The circuit shown in FIG. 9 has the configuration obtained by adding a decision feedback type equalizing circuit 412 to the partial response signaling system shown in FIG. 6. Waveform distortion of the signal caused by the transmission medium 402 includes not only inter-symbol interference due to loss by the transmission medium 402 but also signal reflection” which is caused by discontinuity in the transmission medium 402 and in which influence of data transmitted previously appears with a large delay on the receiver side. When this reflection cannot be ignored, it is dealt with by using the decision feedback type equalizing circuit 412. Since the decision feedback type equalizing circuit 412 only needs to address the influence appearing with the large delay with respect to the received data, there is a sufficient timing margin for operation. That is, the operation speed does not limit the transmission speed of the partial response signaling system.

THIRD EMBODIMENT

FIG. 10 is a block diagram showing the configuration of the partial response signaling system according to the third embodiment of the present invention. The circuit shown in FIG. 10 has the configuration obtained by adding a receiver side equalizing circuit 508 in the receiver circuit 503 of the partial response signaling system shown in FIG. 6. Unlike the receiver side FIR filter 1609 shown in FIG. 3, the receiver side equalizing circuit 508 has fixed characteristics. The receiver side equalizing circuit 508 has a waveform-shaping function. The adaptive equalization control circuit 511 optimizes transmission characteristics of the transmitter side equalizing circuit 506 on the basis of a signal waveform-distorted by the transmission medium 502 and waveform-shaped by the receiver side equalizing circuit 508. As a result, an expected partial response signal 509 is obtained as an output of the receiver side equalizing circuit 508. An equalizing circuit which can operate at a high speed, though not with a high accuracy, such as a high-pass filter using a passive element is used for the receiver side equalizing circuit 508.

FOURTH EMBODIMENT

FIG. 11 is a block diagram showing the configuration of the partial response signaling system according to the fourth embodiment of the present invention. The circuit shown in FIG. 11 has the configuration obtained by adding a transition guarantee encoding circuit 607 to the partial response signaling system shown in FIG. 6. A partial response signal 606 has inter-symbol interference inherent to the partial response signal. Thus, when a binary phase comparator which is advantageous to speed-up is used, a correct clock cannot be recovered by a clock data recovery circuit 610. For this reason, in the partial response signaling in the present embodiment, it is noted that the inter-symbol interference inherent to the partial response signal can be predicted and a data sequence in which clock can be recovered even with the influence of inter-symbol interference can be also predicted. By using the transition guarantee encoding circuit 607, an n-bit parallel data input 604 is encoded to a (n+a)-bit data so that the output of the circuit 601 may contain the clock recoverable data sequence. As a result, the clock recovery circuit 610 of the receiver circuit 603 can recover the correct clock. Thus, high-speed partial response signaling system can be achieved. Here, given that an output of a transition guarantee encoding circuit 607 is n bits, the bit length becomes longer due to coding and the output becomes (n+a) bits (n, a are natural numbers).

FIFTH EMBODIMENT

FIG. 12 is a block diagram showing the configuration of the partial response signaling system according to the fifth embodiment of the present invention. FIG. 12 shows a duo-binary signaling system as one kind of partial response transmission, which has a configuration obtained by adding a 2-bit transition guarantee encoding circuit 707 to the partial response signaling system shown in FIG. 6. In the duo-binary signaling, when a symbol-rate signal which includes 010/101 sequence is supplied, clock recovery becomes difficult by the inter-symbol interference. However, when a data sequence (0011/1100) which transits in units of two bits is supplied, the clock can be recovered without any problem. Accordingly, by using the 2-bit transition guarantee encoding circuit 707, a data input 704 is encoded so that an output of the transmitter circuit 701 may contain clock recoverable 2-bit transition. FIG. 13 shows an example of the duo-binary signal and sampling timings 801 and 802 in case where the data sequence which varies in the symbol rate is inhibited. By assuring 2-bit transition, a correct value against a central threshold value can be determined at the sampling timing 802. As a result, the clock data recovery circuit 710 of the receiver circuit 703 can recover a correct clock from the received duo-binary signal 706, thereby an achieving high-speed duo-binary signaling system. Here, given that the input of the 2-bit transition guarantee encoding circuit 707 is n bits, the bit length becomes longer due to coding and the output becomes (n+a) bits (n, a are natural numbers)

SIXTH EMBODIMENT

FIG. 14 is a block diagram showing the configuration of the partial response signaling system according to the sixth embodiment of the present invention. FIG. 14 shows a duo-binary signaling system as one kind of partial response signaling, in which a data input 904 of a 2-bit transition guarantee encoding circuit 907 in a transmitter circuit 901 is 8 bits and an output thereof is 10 bits. FIG. 15 shows an example of coding performed by the 2-bit transition guarantee encoding circuit 907. By encoding lower 3 bits of the 8-bit input data to 5 bits, 2-bit transition of 0011 or 1100 is contained in 10-bit output data. Here, x is any value.

SEVENTH EMBODIMENT

FIG. 16 is a block diagram showing the configuration of the partial response signaling system according to the seventh embodiment of the present invention. FIG. 16 shows a duo-binary signaling system as one kind of partial response signaling, which has the configuration obtained by adding a transition guarantee encoding circuit 1106 to a transmitter circuit 1101 and a receiver side equalizing circuit 1109 and a decision feedback type equalizing circuit 1114 to a receiver circuit 1103 in the partial response signaling system shown in FIG. 6.

FIG. 17 is a block diagram showing an example of a clock data recovery circuit used in the partial response signaling system according to the seventh embodiment of the present invention. A partial response signal input 1201 is decided by decision circuits 1202 and 1203 which respectively operate in response to clocks at different timing. Each decision result is supplied to a binary type phase comparator 1204 and a phase comparison result is output in binary. According to the comparison result, the phase of an oscillation circuit 1205 changes and accordingly, timings of recovered clocks 1206 which drive the decision circuits 1202 and 1203 also changes. Such a feedback loop constituted from the decision circuits 1202 and 1203, the binary type phase comparator 1204 and the oscillation circuit 1205 allows timing of the recovered clock 1206 to be an optimum timing for the partial response signal input 1201. According to the clock of the optimum timing, data decided by the decision circuit 1202 becomes a recovery data output 1207.

FIG. 18 is a block diagram showing another example of a clock data recovery circuit in the partial response signaling system according to the seventh embodiment of the present invention. A clock data recovery circuit in FIG. 18 has the configuration obtained by replacing the oscillation circuit 1205 in the clock data recovery circuit in FIG. 17 with a variable delay circuit 1306 which operates in response to a clock input 1305. In the clock data recovery circuit in FIG. 18, a recovered clock 1307 is obtained by varying delay by the variable delay circuit 1306 on the basis of a phase comparison result by a binary phase comparator 1304.

As described above, in the partial response signaling system of the present invention, a high-speed data signal can be equalized to a partial response signal in waveform without being limited by the operating speed of the receiver side equalizing circuit, typically receiver side FIR filter circuit, which processes multi-bit data. Furthermore, high-speed clock data recovery can be achieved without being limited operating speed of the Mueller-Muller phase comparator and operational problems of the oversampling binary phase comparator.

Claims

1-15. (canceled)

16. A signaling system comprising: a transmitter circuit configured to equalize input data in response to a control signal and to transmit a partial response signal through a transmission medium; anda receiver circuit configured to recover an output data from said partial response signal and to generate said control signal based on said partial response signal and an expected signal to output said control signal to said transmitter circuit.

17. The signaling system according to claim 16, wherein said transmitter circuit comprises a transmitter side equalizing circuit configured to equalize the input data in response to said control signal.

18. The signaling system according to claim 16, wherein said transmitter circuit comprises: a 2-bit transition guarantee encoding circuit configured to encode the input data of n parallel bits into (n+2)-bit data containing transition in units of 2 bits to generate an input coded data; anda transmitter side equalizing circuit configured to equalize the input coded data in response to said control signal.

19. The signaling system according to claim 16, wherein said transmitter circuit comprises: a transition guarantee encoding circuit configured to encode the input data of n parallel bits into (n+m)-bit data [containing m-bit transition and] to generate input coded data; anda transmitter side equalizing circuit configured to equalize the input coded data in response to said control signal.

20. The signaling system according to claim 17, wherein said transmitter side equalizing circuit comprises an FIR (Finite Impulse Response) filter.

21. The signaling system according to claim 20, wherein said FIR filter comprises: a plurality of delay circuits connected in serial; anda plurality of variable output drivers connected to outputs of said plurality of delay circuits and a head input of said plurality of delay circuits and configured to output data corresponding to predetermined weights.

22. The signaling system according to claim 20, wherein said FIR filter comprises: a plurality of stages of delay circuits;a plurality of parallel-serial converting circuits every two of which correspond to one of said plurality of stages, wherein one of said two parallel-serial converting circuit receives a parallel input data of one of said delay circuits of said corresponding stage and a parallel output data of another of said delay circuits of said corresponding stage and serially output the parallel data, and the other of said two parallel-serial converting circuit receives a parallel output data of said one delay circuit of said corresponding stage and the parallel output data of said another delay circuit of said corresponding stage and serially output the parallel data; anda plurality of variable output drivers provided for said plurality of parallel-serial converting circuits and configured to output data corresponding to predetermined weights.

23. The signaling system according to claim 17, wherein said receiver circuit comprises: a clock data recovery circuit configured to recover said output data from said partial response signal; andan adaptive equalization control circuit configured to generate said control signal from said partial response signal and said output data.

24. The signaling system according to claim 17, wherein said receiver circuit comprises: an adder configured to add a feedback signal to said partial response signal to generate an added partial response signal;a clock data recovery circuit configured to recover said output data from the added partial response signal;an adaptive equalization control circuit configured to generate said control signal from the added partial response signal and said output data; anda decision feedback type equalizing circuit configured to generate said feedback signal from said output data.

25. The signaling system according to claim 17, wherein said receiver circuit comprises: a receiver side equalizing circuit configured to equalize said partial response signal to generate an equalized partial response signal;a clock data recovery circuit configured to generate said output data from the equalized partial response signal; andan adaptive equalization control circuit configured to generate said control signal from said partial response signal and said output data.

26. The signaling system according to claim 17, wherein said receiver circuit comprises: a clock data recovery circuit configured to recover said output data from said partial response signal; andan adaptive equalization control circuit configured to generate said control signal from said partial response signal and said output data.

27. The signaling system according to claim 18, wherein said receiver circuit comprises: a clock data recovery circuit configured to recover said output data from said partial response signal; andan adaptive equalization control circuit configured to generate said control signal from said partial response signal and said output data.

28. The signaling system according to claim 18, wherein said receiver circuit comprises: a receiver side equalizing circuit configured to equalize said partial response signal to generate an equalized partial response signal;an adder configured to add a feedback signal to the equalized partial response signal to generate an added partial response signal;a clock data recovery circuit configured to recover said output data from the added partial response signal;an adaptive equalization control circuit configured to generate said control signal from the added partial response signal and said output data; anda decision feedback type equalizing circuit configured to generate the feedback signal from said output data.

29. The signaling system according to claim 27, wherein said clock data recovery circuit comprises: first and second decision circuits configured to operate in response to first and second recovered clocks and to output decision results of said partial response signal, said first and second recovered clocks having different timings;a binary type phase comparator configured to compare the decision results from said first and second decision circuits and to recover said output data; andan oscillation circuit configured to output said first and second recovered clocks based on a comparison result by said binary type phase comparator.

30. The signaling system according to claim 27, wherein said clock data recovery circuit comprises: first and second decision circuits configured to operate in response to first and second recovered clocks and to output decision results of said partial response signal, said first and second recovered clocks having different timings;a binary type phase comparator configured to compare the decision results to recover said output data; anda variable delay circuit configured to output said first second recovered clocks based on the comparison results by said binary type phase comparator and an input clock.

31. A transmitter circuit operating to equalize input data in response to a control signal generated based on a partial response signal and an expected signal in said transmitter circuit, and to transmit said partial response signal to a receiver circuit through a transmission medium.

32. A receiver circuit operating to recover an output data from said partial response signal received from a transmitter circuit and to generate a control signal based on said partial response signal and an expected signal to output said control signal to said transmitter circuit.

33. The signaling system according to claim 28, wherein said clock data recovery circuit comprises: first and second decision circuits configured to operate in response to first and second recovered clocks and to output decision results of said partial response signal, said first and second recovered clocks having different timings;a binary type phase comparator configured to compare the decision results from said first and second decision circuits and to recover said output data; andan oscillation circuit configured to output said first and second recovered clocks based on a comparison result by said binary type phase comparator.

34. The signaling system according to claim 28, wherein said clock data recovery circuit comprises: first and second decision circuits configured to operate in response to first and second recovered clocks and to output decision results of said partial response signal, said first and second recovered clocks having different timings; a binary type phase comparator configured to compare the decision results to recover said output data; anda variable delay circuit configured to output said first second recovered clocks based on the comparison results by said binary type phase comparator and an input clock.