Patent Application
20250240008
This application claims the benefit under 35 U.S.C. § 119 (a) of European Patent Application No. 24152953.6 filed Jan. 19, 2024, the contents of which are incorporated by reference herein in their entirety.
The present disclosure relates to a Passgate Gate-Driver Control system, a Gate-Driver Control for such Passgate Gate-Driver Control system, a Pass Gate Charge-Injector for such Gate-Driver Control and an Input Voltage Sensing Timer for such Passgate Gate-Driver Control system.
Passgate switches are components in digital circuitry used for switching signals or controlling the flow of data within a circuit. They play a role in integrated circuits, especially in Complementary Metal-Oxide-Semiconductor CMOS technology. Passgate switches typically include two transistors, one P-channel Metal-Oxide-Semiconductor (PMOS) and one N-channel Metal-Oxide-Semiconductor (NMOS), that work together to form a transmission gate. The PMOS transistor may operate as a switch when the input signal at the gate terminal of the PMOS transistor is at a low voltage level (logic 0), while the NMOS transistor may function as a switch when the input signal at the gate of the NMOS transistor is at a high voltage level (logic 1). When the control signals (i.e., input signals) of these transistors are appropriately manipulated, the passgate switch allows signals to pass through or be blocked, essentially acting as an on/off switch for the flow of data or electrical signals.
Passgate switches are used in various digital circuit applications, such as multiplexers, logic gates, flip-flops, and more complex circuits. They enable efficient routing of signals, data transmission, and manipulation within these circuits, contributing to the overall functionality and operation of electronic devices.
Overshoot and Undershoot voltage during switching passgate switches can damage system due to overvoltage stresses. External Resistor-Inductor-Capacitive (RLC) components of Printed-Circuit-Board (PCB) and mismatch in passgate capacitance due to size dissimilarity between the NMOS and PMOS are key offenders that cause overshoot voltage.
A summary of aspects of certain examples disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects and/or a combination of aspects that may not be set forth.
The present disclosure aims to overcome the drawbacks identified in the background section.
This present application proposes a gate driver control scheme to control a passgate switch so that no-overshoot will be observed at the output during switching. An improved Gate Driver Control is proposed that includes a Pass Gate Charge-Injector. The Gate Driver Control may further include an Input Voltage Sensing Timer. The Gate Driver Control may further include an Output Voltage Sensing Timer. This solution of the present disclosure enables fast switching of the passgate while achieving no-overshoot across wide-supply-voltage range while consuming no active current.
According to an aspect of the present disclosure, a Passgate Gate-Driver Control system is presented. The Passgate Gate-Driver Control system may include a Gate-Driver Control. The Passgate Gate-Driver Control system may further include a passgate switch comprising a PMOS transistor and an NMOS transistor. The Gate-Driver Control may include a Pass Gate Charge-Injector arranged to alter a charging speed and/or a discharging speed of an electrical charge at a gate of the PMOS and/or NMOS transistor.
In an embodiment, the Passgate Gate-Driver Control system may include two passgate switches each driven by a separate Gate-Driver Control.
In an embodiment, a first Gate-Driver Control may linearly control a switching ON and OFF state of a first passgate switch. A second Gate-Driver Control may linearly control a switching ON and OFF state of a second passgate switch.
According to an aspect the present disclosure, a Gate-Driver Control is presented. The Gate-Driver Control may be a part of the Passgate Gate-Driver Control system having one or more of the above-described features. The Gate-Driver Control Gate-Driver Control may include a Pass Gate Charge-Injector arranged to alter a charging speed and/or a discharging speed of an electrical charge at a gate of a PMOS and/or NMOS transistor of a passgate switch.
In an embodiment, the Gate-Driver Control may further include an Input Voltage Sensing Timer arranged to provide a first ONE-SHOT signal to the Pass Gate Charge-Injector for speeding up a turning ON of the passgate switch for a time duration. The time duration may be determined by an input voltage through the Input Voltage Sensing Timer.
In an embodiment, the Gate-Driver Control may further include an Output Voltage Sensing Timer arranged to provide a second ONE-SHOT signal to the Pass Gate Charge-Injector to enforce a slowing down of the speeding up of the turning ON of the passgate switch after speeding up the turning ON of the passgate switch for the time duration.
According to an aspect of the present disclosure, a Pass Gate Charge-Injector is presented. The Pass Gate Charge-Injector may be a part of a Gate-Driver Control having one or more of the above described features. The Pass Gate Charge-Injector may be arranged to alter a charging speed and/or a discharging speed of an electrical charge at a gate of a PMOS and/or NMOS transistor of a passgate switch.
In an embodiment, the Pass Gate Charge-Injector may be arranged to receive a first ONE-SHOT signal from an Input Voltage Sensing Timer of the Gate-Driver Control for speeding up a turning ON of the passgate switch for a time duration. The time duration may be determined by an input voltage through the Input Voltage Sensing Timer.
In an embodiment, the Pass Gate Charge-Injector may be arranged to receive a second ONE-SHOT signal from an Output Voltage Sensing Timer of the Gate-Driver Control to enforce a slowing down of the speeding up of the turning ON of the passgate switch after speeding up the turning ON of the passgate switch for the time duration.
According to an aspect of the present disclosure, an Input Voltage Sensing Timer is presented for a Passgate Gate-Driver Control system having one or more of the above described features. The Input Voltage Sensing Timer may be arranged to provide a first ONE-SHOT signal to a Pass Gate Charge-Injector for speeding up a turning ON of a passgate switch of the Passgate Gate-Driver Control system for a time duration. The time duration may be determined by an input voltage through the Input Voltage Sensing Timer.
Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbol indicate corresponding parts, in which:
The figures are intended for illustrative purposes only, and do not serve as restriction of the scope of the protection as laid down by the claims.
It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the present disclosure is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present disclosure should be or are in any single example of the present disclosure. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same example.
Furthermore, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
As described in the background, overshoot and undershoot voltage during switching passgate switches can be damaging. Overshoot voltage can be manifested as voltage ringing during switching. Lowering the slew rate of the gate voltage during switching mitigates the overshoot but reduces the switching transition time, slowing down the system. Limitation of low-supply current and requirement for large supply variation from, e.g., 1.08 to 5.5V are key challenges to overcome.
To overcome the problems of having overshoot voltage at the OUTPUT, the present disclosure presents an electrical mechanism to create a “fast-start, slow-after” response which can speed up the transition time in a linear fashion. The solution of the present disclosure includes a new gate driver control system to generate such response. As will be explained in more detail below, the Gate Driver Control takes in signals from various pins sources such as the SELECT pin, INPUT and OUTPUT nets. These signals may then regulate the Pass Gate Charge-Injector to speed-up or slow-down the electrical charging and discharging of the passgate switch to control the overshoot and undershoot phenomena. In addition, the electrical mechanism does not have any active current while being adaptable to supply, input voltage and output voltage variation.
The solution of the present disclosure advantageously enables a low-power, wide-supply passgate switch gate-driver control for “fast-start, slow-after” response to prevent no-overshoot when switching.
In an embodiment of the present disclosure, the Gate-Driver Control 110 includes a Pass Gate Charge-Injector 112, an Input Voltage Sensing Timer 114 and an Output Voltage Sensing Timer 116, which will be further explained below.
The proposed Passgate Gate-Driver Control system architecture 100 enables No-overshoot when switching passgates 106, 108.
The overall function of the proposed gate driver (i.e., Passgate Gate-Driver Control 110) is to linearly control the switching ON and OFF state of the passgate switches 106, 108, which are the passgate switch 0 (106) and passgate switch 1 (108) in
The control mechanism of the Pass Gate Charge-Injector 112 may depend on gate control signals from the Input Voltage Sensing Timer 114 and Output Voltage Sensing Timer 116 to achieve a “fast-start, slow-after” response. The Voltage Sensing Elements 114, 116 ensure accurate timing sequencing of the charging and discharge speed of electrical charge to the gates of the passgate switch 106, 108. The “fast-rising, slow-after” response alleviate the voltage overshoot and undershoot during the switching passgate switches 106, 108 while achieving fast switching transition time from one passgate switch to the other.
Advantageously, the system 100 and in particular the implementation of the gate driver control as Passgate Gate-Driver Control 110 of the present disclosure ensures adaptability to wide-supply voltages while consuming substantially no direct current (DC).
As SEL_IN goes from HIGH-to-LOW, MN2 and MP4 turns OFF, MN3 and MP3 turns ON. At the same time during the transition state, MN1 is triggered with a ONE-SHOT signal, Spulse_a. As MN1 is turned-ON, net Vb1 will be pulled to ground and MP1, MP2, MP5 and MN4 will be turned-ON which generate a bias current, Ibias through this network circuit. This bias network will first dominate MN3 and MP3 during the turning-ON transition state. The activated Ibias through MP1 is mirrored to MP2 and MN4 as Ibias2 and Ibias4, respectively. MP2 and MP4 quickly injects large electrical charge to the NMOS and PMOS gate, respectively. Consequently, a “fast-rising” response will be observed at VN and VP where the voltage VN goes quickly from LOW-to-HIGH and VP from HIGH-to-LOW.
The ONE-SHOT of Spulse_a through MP1, MP2, MP5 and MN4 is to speed up the turning ON of the passgate switch for a short duration. The duration of Spulse_a will be determined by the input voltage, VIN through the Input Voltage Sensing Timer 114. This is to ensures the right amount of charge is injected as to not cause overshoot at the output but still retain a fast turning-ON time. Once the ONE-SHOT signal ends, the Gate Driver Control will start to slow down turning-ON of the passgate switch 106, 108 through MN3 and MP3 turns ON. The RC elements R1 with C1 and R2 purpose is to slow down the rising and falling voltage of VN and VP, respectively during the transition time of turning ON passgate switch 106, 108. The “slow-after” response is further enforced with the Output Voltage Sensing Timer circuit 116. The output voltage, VOUT is detected through the biasing MP6 when the voltage is below one Vth below the supply voltage and the Output Voltage Sensing Timer 116. The Output Voltage Sensing Timer 116 would activate and generate a ONE-SHOT signal, Spulse_b to turn-ON this network and further enforce a “slow-after” response. When the voltage at VN and VP settles and the passgate switch is ON, MN3 and MP3 are the primary pull-down device for net VP and pull-up device for net VN, respectively. This network branch will be ON throughout the turning ON time of the passgate switch.
As can be seen, the OUTPUT plot exhibit a “fast-start, slow-after” response to prevent no-overshoot during switching (the fast-start is depicted 302; the slow-after is depicted 304). VP and VN shows the gate voltage of the passgate switch 106, 108 which are controlled by the Gate-Driver Control 110. When the Gate-Driver Control 110 is activated through SEL_IN going from High-to-LOW, we can observe the ONE_SHOT signals, Spulse_a and subsequently Spulse_b activating.
The pulse width of the ONE-SHOT signal, Spulse_a, may be determined by the voltage level of VIN through the Input Voltage Sensing Timer 114, such as shown in the example embodiment of
The ONE-SHOT Spulse_a is generated when node x and y are both HIGH momentarily as shown in Table 2.
The Spulse_b signal may be determined through the Output Voltage Sensing Timer 116, such as shown in the example embodiment of
To further enhance the Output Voltage Sensing Timer 116, a comparator 602 may be used as a bypass mechanism to deactivate Spulse_b. This occurs when IN0 and IN1 are both in a HIGH-state. An example embodiment of comparator 602 is shown in
The Input Voltage Sensing Time 114 and the Output Voltage Sensing Timer 116 may each include an equivalent resistor element 800, such as shown in
The solution of the present disclosure advantageously enables a wide-supply and input/output voltage range. The supply may, e.g., be in a range from 1.08V to 5.5V. The OUTPUT range may, e.g., be in a range from 0V to 5.5V.
The solution of the present disclosure advantageously allows a low supply current. The Gate-Driver Control 110 does not require any active circuit that consumes current.
Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 24152953.6 | Jan 2024 | EP | regional |
