Passive-matrix type liquid crystal display apparatus and drive circuit thereof with single analog switch/adjusted scanning voltage based operation

Abstract

A segmented electrode drive circuit of a passive-matrix type liquid crystal display apparatus includes one analog switch in each of segmented electrodes, supplies “0” as a control signal in the first slot of a three-slot selecting period so as to make the electrical potential of a segmented electrode zero. “1” is supplied as a control signal in the second slot so as to bring the output terminal of an analog switch selected by the data signal into a high-impedance state. As a result, the electric potential of the segmented electrode in the high-impedance state becomes an average electric potential of scanning electrodes capacitive-coupled with the segmented electrode.

Description

FIELD OF THE INVENTION

The present invention relates to a passive-matrix type liquid crystal display apparatus, and more particularly relates to a passive-matrix type liquid crystal display apparatus using ferroelectric liquid crystals and a drive circuit thereof.

BACKGROUND OF THE INVENTION

FIG. 20 shows the structure of a drive circuit of a passive-matrix type liquid crystal display apparatus disclosed in Japanese Publication for Unexamined Patent Application (Tokukaihei) No. 6-18848 (1994). In this structure, two analog switches are provided for each segmented electrode Yi (i=1 to m). For instance, when an analog switch 261 connected to a segmented electrode Y 1 is turned ON, a voltage V 3 is applied to the segmented electrode Yi. In other cases, an analog switch 241 is turned ON, and a voltage V 1 is applied to the segmented electrode Yi.

FIG. 21 shows a drive circuit on the source side of an active-matrix type liquid crystal display apparatus disclosed in Japanese Publication for Unexamined Patent Application (Tokukaihei) No. 5-100635 (1993). In this drive circuit structure, a voltage to be applied to the active-matrix type liquid crystal display apparatus is determined by selecting a power source from external power sources V 0 to V 7 according to the values of high order bits D 1 to D 3 of data retained in a latch circuit 201 , and by turning ON/OFF an analog switch 206 according to the values of low order bits D 4 and D 5 and a timing control signal 209 .

FIGS. 22 and 19 are block diagrams showing examples of the structure of a drive circuit of a conventional ferroelectric liquid crystal display apparatus and the waveforms of drive voltages. A drive circuit 71 on the scanning side, for driving scanning electrodes L, includes a shift register 76 and an analog switch array 77 . The drive circuit 71 selects one voltage waveform from three voltage waveforms, V CA , V CB and V CC , shown in FIG. 19 , based on the value of input two-bit data YI, and applies the selected waveform to the scanning electrodes.

A drive circuit 72 on the segment side, for driving segmented electrodes S, includes a shift register 73 , a latch 74 , and an analog switch array 75 . The drive circuit 72 selects one voltage waveform from two voltage waveforms, V SD and V SE , shown in FIG. 19 , based on data XI retained in the latch 74 , and applies the selected waveform to the segmented electrodes.

FIG. 23 shows an example of the waveforms used by a drive scheme for a ferroelectric liquid crystal display apparatus, which was suggested by the present inventors and disclosed in Japanese Publication for Unexamined Patent Application (Tokukaihei) No. 8-50278 (1996). In this drive scheme, a multiple gray scale display is achieved with a ferroelectric liquid crystal display apparatus by forming one pixel from three sub-pixels A ijA , A ijB and A ijC which are driven by three lines of scanning electrodes L iA , L iB and L iC (i=0, 1, . . . ), and one line of segmented electrode S j (j=0, 1, . . . ) as shown in FIG. 11 , and by applying different selection voltage waveforms V CA , V CB and V CC shown in FIG. 23 , to the three lines of scanning electrodes, respectively.

However, the above-mentioned conventional structure suffers from the following drawbacks.

In the drive circuit on the segment side of the conventional passive-matrix type liquid crystal display apparatus, two analog switches are required for one output level of each output terminal. When forming the drive circuit as an integrated circuit, if the number of output terminals and the area of a chip are fixed, the area for each analog switch can be increased by decreasing the number of analog switches per output terminal, and the output resistance of each output terminal can be reduced by an amount corresponding to the increase.

The technique disclosed in Japanese Publication for Unexamined Patent Application (Tokukaihei) No. 5-100635 (1993) above is a technique for decreasing the number of analog switches per output terminal in the drive circuit on the source side of the active-matrix type liquid crystal display apparatus. However, a scheme to obtain a plurality of output levels using one analog switch as a drive circuit of a passive-matrix type liquid crystal display apparatus has not yet been proposed.

A conventional ferroelectric liquid crystal display apparatus achieves bright and dark displays by using bistability of ferroelectric liquid crystals and aligning the molecule long axis of a ferroelectric liquid crystal molecule in one of the stable states with the polarization axis of a polarizing plate. With the use of ferroelectric liquid crystals with negative dielectric anisotropy, the memory angle changes depending on the root-mean-square value of a bias voltage applied, and the memory angle becomes larger with an increase in the root-mean-square value.

For example, in the drive scheme disclosed in Japanese Publication for Unexamined Patent Application (Tokukaihei) No. 8-50278 (1996) above, four kinds of voltage waveforms are applied to the segmented electrodes, and a variation of the root-mean-square value of the bias voltage is relatively wide. Therefore, even when the polarizing plate is positioned according to one bias state, if the display pattern changes into another bias state, the memory angle changes and the contrast is lowered.

The memory angle of the ferroelectric liquid crystal also changes depending on temperature. Therefore, even when the polarization axis of the polarizing plate is positioned according to a memory angle at a certain temperature, the memory angle varies as the temperature changes, and the contrast is lowered.

SUMMARY OF THE INVENTION

The first object of the present invention is to provide a segment drive circuit of a passive-matrix type liquid crystal display apparatus, capable of giving a plurality of output levels using one analog switch.

The second object of the present invention is to reduce the variation of the root-mean-square value of bias voltage and to prevent a lowering of the contrast in a ferroelectric liquid crystal display apparatus providing a multiple gray scale display using more than one kind of voltage waveforms.

The third object of the present invention is to compensate for a change in the memory angle of ferroelectric liquid crystals caused by a change in temperature, and to prevent a lowering of the contrast.

In order to achieve the first object, a passive-matrix type liquid crystal display apparatus of the present invention includes a pixel formed by a liquid crystal lying at each intersection of scanning electrodes and segmented electrodes, and is constructed so that a single analog switch is connected to each segmented electrode, a first electric potential is generated in the segmented electrode through the single analog switch connected thereto, by bringing the single analog switch into a conductive state and injecting a predetermined electric charge into the segmented electrode, and an electric potential different from the first electric potential is generated in the segmented electrode by bringing the single analog switch into a non-conductive state and adjusting a voltage to be applied to the scanning electrode.

In this structure, first, the analog switch is brought into a conductive state and a predetermined electric charge is injected into the segmented electrode so as to cause the segmented electrode to have the first electric potential corresponding to the predetermined electric charge. Next, when the analog switch is brought into a non-conductive state, since the electric charge does not enter into nor leave from the segmented electrode connected to this analog switch, the predetermined electric charge is retained on the segmented electrode.

The predetermined electric charge, Q, is given by

Q=CV

where C is the capacity of liquid crystal located between the scanning electrode and the segmented electrode, and V is the potential difference between the scanning electrode and the segmented electrode. Since Q and C are constant, when the voltage to be applied to the scanning electrode is changed, the electric potential of the segmented electrode varies according to the change. Namely, it is possible to produce an electric potential different from the first electric potential in the segmented electrode by adjusting the voltage to be applied to the scanning electrode.

Consequently, in the structure where the number of analog switches connected to the segmented electrode is arranged to be one, more than one kind of electric potentials can be produced in the segmented electrode, thereby simplifying the structure of the drive circuit on the segmented electrode side. For example, when forming the drive circuit by an IC, if the area of a silicon wafer and the number of output terminals per IC are fixed, the area of each analog switch can be increased and the output impedance can be lowered as compared to the structure requiring a plurality of analog switches for each output terminal. On the other hand, if a lowering of the output impedance is not required, it is possible to reduce the area of the silicon wafer per IC on condition that the number of output terminals is fixed. It is therefore possible to produce a drive circuit of a passive-matrix type liquid crystal display apparatus at reduced costs.

Moreover, in the passive-matrix type liquid crystal display apparatus, the liquid crystals are preferably ferroelectric liquid crystals. Since the ferroelectric liquid crystals have memory effects, and a higher response speed than that of nematic liquid crystals, it is possible to provide a passive-matrix type liquid crystal display apparatus capable of achieving a large-capacity display.

The liquid crystals are more preferably ferroelectric liquid crystals with negative dielectric anisotropy.

In order to achieve the second object, another passive-matrix type liquid crystal display apparatus of the present invention includes a pixel formed by a liquid crystal lying at each intersection of scanning electrodes and segmented electrodes, and is constructed so that the liquid crystal is a ferroelectric liquid crystal and a voltage is applied to the scanning electrode in a non-selecting period, the voltage having a waveform formed by a bipolar pulse with a pulse height V a and a bipolar pulse with a pulse height V b , V a and V b satisfying

V a <( V max +V min )/2 <V b

where V max is a maximum of pulse heights of voltages to be applied to the segmented electrode and V min is a minimum thereof.

In this structure, by applying a bipolar pulse having pulse heights V a and V b satisfying

V a <( V max +V min )/2 <V b

to the scanning electrode in the non-selecting period, the root-mean-square value of the bias voltage is equalized as compared to the conventional structure disclosed by, for example, Japanese Publication for Unexamined Patent Application (Tokukaihei) No. 8-50278 (1996), where a bipolar pulse represented by V c =(V max +V min )/2 is applied to the scanning electrode.

More specifically, when the voltage waveforms to be applied to the segmented electrode has more than two pulse heights, the root-mean-square value of the bias voltage is equalized by periodically applying a waveform with a pulse height which is close to the minimum of the above-mentioned pulse heights and a waveform with a pulse height which is close to the maximum thereof rather than taking the average of these pulse heights as the pulse height of a non-selection voltage.

The memory angle of the ferroelectric liquid crystals varies depending on the root-mean-square value of the bias voltage applied. It is possible to reduce the change of the memory angle and improve the contrast by equalizing the root-mean-square value of the bias voltage in the manner mentioned above.

In order to achieve the second object, still another passive-matrix type liquid crystal display apparatus includes a pixel formed by a liquid crystal lying at each intersection of scanning electrodes and segmented electrodes, and is constructed so that the liquid crystal is a ferroelectric liquid crystal and a voltage is applied to the scanning electrodes in a non-selecting period, the voltage having a waveform formed by a first unipolar pulse of two slots having a pulse height V x and a second unipolar pulse with the pulse height V x and a polarity opposite to that of the first unipolar pulse, V x being either V a or V b satisfying

V a <( V max +V min )/2 <V b

where V max is a maximum of a pulse heights of voltages to be applied to the segmented electrodes and V min is a minimum thereof.

In this structure, the root-mean-square value of the bias voltage can be equalized as compared to the conventional structure where a bipolar pulse represented by V c =(V max +V min )/2 is applied to the scanning electrode in the non-selecting period. As a result, the change of the memory angle of the ferroelectric liquid crystal is reduced, and the contrast is improved.

In order to achieve the third object, yet another passive-matrix type liquid crystal display apparatus of the present invention includes a pixel formed by a liquid crystal lying at each intersection of scanning electrodes and segmented electrodes, and is constructed so that the liquid crystal is a ferroelectric liquid crystal, a DC voltage varying according to a measured change in temperature of the liquid crystal is superimposed over a drive voltage applied to the scanning electrodes.

With the use of the bistable states, the ferroelectric liquid crystal is constructed so as to achieve a bright state by aligning the long axis of the liquid crystal molecule in one of bistable state with the polarization axis of the polarizing plate to transmit light and a dark state when the liquid crystal molecule enters into the other of bistable state. However, in the ferroelectric liquid crystal, since the memory angle varies with a change in temperature, even if the long axis of the liquid crystal molecule in one of the stable states is aligned with the polarization axis at certain a temperature, the long axis of the molecule and the polarization axis become out of alignment with a change in temperature, resulting in a lowering of the contrast.

In this structure, the change of the memory angle caused by a temperature change can be compensated by measuring a change in the temperature of the ferroelectric liquid crystal and superimposing a DC current having a voltage corresponding to the temperature change on the drive voltage to be applied to the scanning electrode. Such a compensation is achieved because when a weak DC voltage is kept applied to the ferroelectric liquid crystal molecule in the stable state, the liquid crystal molecule moves in a direction at an angle corresponding to the value of the DC voltage without causing a switching. Therefore, even when the temperature of the ferroelectric liquid crystal varies due to a variation of ambient temperature and heat generated by the liquid crystal display apparatus, it is possible to prevent a lowering of the contrast.

Further, in the above-mentioned structure, it is preferred that the blanking voltage is applied to the scanning electrode before the selecting period, a voltage for cancelling the superimposed DC component is applied to the scanning electrode after the blanking voltage and before the selecting period.

In this arrangement, since the superimposed DC component is canceled to achieve a DC balance, it is possible to stabilize the drive characteristics of ferroelectric liquid crystal. In particular, when the ferroelectric liquid crystal has negative dielectric anisotropy, the response speed becomes fastest at a voltage V min , and a switching is not effected even if a voltage greater than the voltage V min is applied. If a voltage greater than the voltage V min is applied after the blanking voltage and before the selecting period, it is possible to achieve a DC balance without affecting a switching operation, and to prevent a lowering of the contrast.

Furthermore, in order to achieve the above-mentioned first object, a drive circuit of a passive-matrix type liquid crystal display apparatus of the present invention is a drive circuit for a passive-matrix type liquid crystal display apparatus having a pixel formed by a liquid crystal lying at each intersection of scanning electrodes and segmented electrodes, and is constructed so that each output terminal connected to the segmented electrode is formed by a single analog switch. In this structure, since the structure of the drive circuit on the segmented electrode side is simplified, it is possible to achieve a compact drive circuit capable of being produced at reduced costs.

For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the structure of a segmented electrode drive circuit in a ferroelectric liquid crystal display apparatus according to one embodiment of the present invention.

FIG. 2 is a cross sectional view showing the structure of a liquid crystal panel in the ferroelectric liquid crystal display apparatus.

FIG. 3 ( a ) is an explanatory view showing how the ferroelectric liquid crystal molecule sealed in the liquid crystal panel is switched between bistable states, and

FIG. 3 ( b ) is a perspective view showing the state of the ferroelectric liquid crystal molecule in a smectic C phase.

FIG. 4 is a block diagram showing the schematic structures and the connection of the liquid crystal panel, a scanning electrode drive circuit for driving the scanning electrodes of the liquid crystal panel, and a segmented electrode drive circuit for driving the segmented electrodes thereof.

FIG. 5 is a circuit diagram showing the structure of the scanning electrode drive circuit.

FIG. 6 is a waveform illustration showing the waveforms of drive voltages applied by the scanning electrode drive circuit and the segmented electrode drive circuit.

FIG. 7 is a circuit diagram of a part of a RC equivalent circuit of the scanning electrode and the segmented electrode.

FIG. 8 is a circuit diagram of a part of a RC equivalent circuit of the scanning electrode and the segmented electrode.

FIG. 9 is an explanatory view showing the display of an oscilloscope when measuring the waveforms of drive voltages applied to the segmented electrodes by the segmented electrode drive circuit.

FIG. 10 is an explanatory view showing the display of the oscilloscope when measuring the waveforms of drive voltages applied to the segmented electrodes by the segmented electrode drive circuit.

FIG. 11 is an explanatory view showing the electrode structure of a ferroelectric liquid crystal display apparatus according to another embodiment of the present invention.

FIG. 12 is a graph showing a pulse width r at which 90% or 10% of the liquid crystal molecules in the pixel switch against the pulse height V S of the first pulse when two pulses having the same width are continuously applied.

FIG. 13 is a waveform illustration showing the. waveforms of drive voltages applied to the scanning electrodes and the segmented electrodes of the ferroelectric liquid crystal display apparatus of FIG. 11 in the selecting period.

FIG. 14 is a waveform illustration showing the waveforms of drive voltages applied to the scanning electrodes and the segmented electrodes of the ferroelectric liquid crystal display apparatus of FIG. 11 in the non-selecting period.

FIG. 15 is a waveform illustration showing another example of the waveforms of drive voltages applied to the scanning electrodes and the segmented electrodes of the ferroelectric liquid crystal display apparatus of FIG. 11 in the non-selecting period.

FIG. 16 is a graph showing the temperature dependence of the memory angle. FIG. 17 is a graph showing changes in the amount of transmitted light when a voltage was further applied after the liquid crystal molecules were brought into the first or second stable state.

FIG. 18 is a waveform illustration showing the waveforms of drive voltages applied to the scanning electrodes in a ferroelectric liquid crystal display apparatus according to still another embodiment of the present invention.

FIG. 19 is a waveform illustration showing the waveforms of drive voltages according to the JOERS/Alvey drive scheme.

FIG. 20 is a block diagram showing an example of a drive circuit of a conventional passive-matrix type liquid crystal display apparatus.

FIG. 21 is a block diagram showing an example of a drive circuit of a conventional active-matrix type liquid crystal display apparatus.

FIG. 22 is a block diagram showing an example of the structure of a drive system of a conventional ferroelectric liquid crystal display apparatus.

FIG. 23 is a waveform illustration showing the waveforms of drive voltages used for achieving a gray scale display with a conventional ferroelectric liquid crystal display apparatus.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment 1

The following description will discuss one embodiment of the present invention with reference to FIGS. 1 to 10 .

First, the structure of a liquid crystal panel 1 of a ferroelectric liquid crystal display apparatus (passive-matrix type liquid crystal display apparatus) of this embodiment will be explained.

As illustrated in FIG. 2 , the liquid crystal panel 1 includes two pieces of substrates 2 and 3 positioned to face each other. The substrates 2 and 3 are formed by light transmitting material such as glass. On a surface of the substrate 2 , a plurality of transparent segmented electrodes S made of, for example, indium tin oxide (hereinafter referred to as “ITO”) are arranged parallel to each other. These segmented electrodes S are covered with a transparent insulating film 4 made of, for example, silicone oxide (SiO 2).

On the other hand, on the surface of the substrate 3 , transparent scanning electrodes L made of, for example, ITO are arranged parallel to each other in a direction orthogonal to the segmented electrodes S. These scanning electrodes L are also covered with an insulating film 5 made of the same material as that of the insulating film 4 .

Alignment films 6 and 7 to which a uniaxial aligning treatment such as rubbing treatment has been applied are placed on the insulating films 4 and 5 , respectively. As the alignment films 6 and 7 , for example, polyvinyl alcohol is used.

The substrates 2 and 3 are fastened with a sealing agent 9 so that the alignment films 6 and 7 face each other, and the space between the substrates 2 and 3 is filled with ferroelectric liquid crystals (hereinafter referred to as the “FLC”) 8 to form a liquid crystal layer. The FLC 8 is injected through an inlet (not shown) provided in the sealing agent 9 and sealed in the space between the alignment films 6 and 7 by, for example, vacuum injection. After injecting the FLC 8 , the inlet is closed with the sealing agent 9 .

The substrates 2 and 3 are sandwiched between two pieces of polarizing plates 10 and 11 which are positioned so that the polarization axes thereof cross each other at right angles. The space between the scanning electrodes L and the segmented electrodes S are arranged to be about 1.5 μm. By narrowing the cell gap to such a degree, the molecules of the FLC 8 show bistability.

The FLC 8 can be prepared by mixing a ferroelectric liquid crystal material (product name: SCE-8) produced by Merck Ltd. with a compound represented by the following general formula (Formula 1) in a ratio of 9 to 1. The dielectric anisotropy of the ferroelectric liquid crystal material is negative. The alignment films 6 and 7 are achieved by, for example, PSI-A-2101 (product name) available from Chisso Co., Ltd.

Formula 1

As illustrated in FIG. 3 ( b ), a liquid crystal molecule 51 of the FLC 8 has a spontaneous polarization P S in a direction perpendicular to the molecular long axis direction. The liquid crystal molecule 51 receives a force proportional to the vector product of the spontaneous polarization P S and an electric field E produced by a potential difference between a voltage applied to the scanning electrode L and a voltage applied to the segmented electrode S, and moves on the surface of a conical locus 55 . As shown in FIG. 3 ( a ), the liquid crystal molecule 51 is brought into a stable state at position P 1 by an electric field E, and is brought into a stable state at position P 2 by the electric field E inverted.

Therefore, by aligning one of the polarization axes of the polarizing plates 10 and 11 with the long axis of the liquid crystal molecule 51 at either position P 1 or P 2 , it is possible to achieve two display states, bright and dark states. More specifically, a pixel having the liquid crystal molecule 51 in one of the stable states exhibits a bright display state, while a pixel having the liquid crystal molecule 51 in the other stable state shows a dark display state.

A force proportional to the product of the square of the electric field E and the dielectric anisotropy Δε as the difference in the dielectric constant between the directions of the molecular long axis and the molecular short axis is exerted on the liquid crystal molecule 51 as well as the force of the above-mentioned electric field E. Therefore, the force, F, exerted on the liquid crystal molecule 51 is given by the following equation.

F=K 0 ×P S ×E+K 1 ×Δε×E 2

where K 0 and K 1 are constants.

Therefore, in the ferroelectric liquid crystal whose dielectric anisotropy Δε is negative, when the electric field E increases, an increase in the force produced by the effect of the negative dielectric anisotropy Δε becomes greater than an increase in the force produced by the spontaneous polarization P S in an electric field E min , and the force exerted on the liquid crystal molecule 51 is maximized in the electric field E min . Moreover, since it is considered that the memory pulse width is in inverse proportion to the force exerted on the liquid crystal molecule 51 , the memory pulse width is minimized in the electric field E min . Consequently, the ferroelectric liquid crystal with negative dielectric anisotropy Δε has a minimum memory pulse width τ min against a specific voltage V min , i.e., showing a so called τ−V min characteristic.

Here, the JOERS/Alvey drive scheme (hereinafter referred to as the “J/A drive scheme”) presented as “The JOERS/Alvey Ferroelectric Multiplexing Scheme” by the Defense Research Agency in the FLC International Conference (1991) will be explained as an example of conventional drive schemes using the τ−V min characteristic for reference.

In this drive scheme, as shown in FIG. 19 , V CA is applied to the scanning electrodes L in the selecting period, and V CB is applied to the scanning electrodes L in a blanking period before the selecting period. V CC is applied to the scanning electrodes L in other periods. When the switching of the display state is not intended, V SD is applied to the segmented electrodes S. On the other hand, when the switching of the display state is intended, V SE is applied to the segmented electrodes S.

A voltage waveform V A-D produced at a pixel by a voltage waveform V CA applied to the scanning electrode L and a voltage waveform V SD applied to the segmented electrode S has a pulse height of −V 1 in the first slot and a pulse height of 2V 0 +V 1 in the second slot. Here, 2V 0 +V 1 >V min . The state of the pixel is not switched by the voltage waveform V A-D .

A voltage waveform V A-E produced at a pixel by a voltage waveform V CA applied to the scanning electrode L and a voltage waveform V SE applied to the segmented electrode S has a pulse height of V 1 in the first slot and a pulse height of 2V 0 −V 1 in the second slot. The state of the pixel is switched by the voltage waveform V A-E .

When a voltage waveform V CB (V 0 <V min ) shown in FIG. 19 is applied as a blanking voltage to the scanning electrode L twice before the selecting period, the liquid crystal molecules forming the pixels on the scanning electrode turn into one of the stable states after the voltage waveform V B-D or V B-E is applied twice. Thereafter, by applying the voltage waveform V A-D or V A-E depending on whether the state of the pixel is to be switched or not, the pixel is brought into a desired display state. It is thus possible to control the display state of each pixel.

The following description will discuss a drive circuit provided for driving the liquid crystal panel 1 in the ferroelectric liquid crystal display apparatus of this embodiment.

As illustrated in FIG. 4 , the drive circuit is formed by a scanning electrode drive circuit 31 and a segmented electrode drive circuit 32 . The scanning electrode drive circuit 31 is a circuit for applying a voltage to the scanning electrodes L of the liquid crystal panel 1 , and its output terminals are connected to the scanning electrodes L (L 0 to L F ) of the liquid crystal panel 1 . The output terminals of the segmented electrode drive circuit 32 are connected to the segmented electrodes (S 0 to S F ).

In order to simplify the explanation, in FIG. 4 , the liquid crystal panel 1 includes 16 lines of scanning electrodes L and 16 lines of segmented electrodes to form 16×16 pixels. In practice, it is possible to arrange any number of lines of scanning electrodes L and segmented electrodes S according to a desired number of pixels. The intersection of scanning electrode L i (i=0 to F) and segmented electrode S j (j=0 to F) is indicated as a pixel A ij in the explanation below.

The scanning electrode drive circuit 31 is formed by a shift register 36 and an analog switch array 37 . The shift register 36 is synchronous with a latch pulse LP of positive logic, and outputs a three-bit scanning signal YI to the analog switch array 37 from each output stage. A control signal CB and source voltages V c0 to V c4 are supplied to the analog switch array 37 .

When the control signal CB is “0”, the scanning electrode drive circuit 31 makes the electric potential of all of the scanning electrodes L zero irrespectively of the scanning signal YI. When the control signal CB is “1”, the scanning electrode drive circuit 31 supplies a voltage waveform corresponding to the value of the scanning signal YI to the scanning electrodes L. This voltage waveform will be discussed in detail later.

Here, the internal structure of the scanning electrode drive circuit 31 will be explained in further detail. As illustrated in FIG. 5 , in the analog switch array 37 of the scanning electrode drive circuit 31 , one switching circuit SW is provided for each scanning electrode L. For instance, a switching circuit SW L1 is connected to a scanning electrode L 1 . Each switching circuit SW is formed by a decoder 102 , and five analog switches 103 .

Next, the structure of the segmented electrode drive circuit 32 will be discussed. As illustrated in FIG. 4 , the segmented electrode drive circuit 32 is formed by a shift register 33 , a latch 34 , and an analog switch array 35 . A data signal XI and a clock CK are supplied to the shift register 33 . The shift register 33 outputs the data signal XI to the latch 34 based on the clock CK. The output data signal XI is synchronized with a latch pulse LP of negative logic, and is held in the latch 34 . A control signal SB and a source voltage V S are supplied to the analog switch array 35 . In this case, the source voltage V S is 0 V.

The internal structure of the segmented electrode drive circuit 32 is shown in FIG. 1 . The shift register 33 is formed by the registers 105 . The latch 34 is achieved by a register 106 . The analog switch array 35 is formed by the same number of analog switches 107 as the segmented electrodes S.

When the control signal SB is “0”, the output of the analog switch 107 has an electric potential of zero irrespectively of the data signal XI. When the control signal SB is “1”, the output of the analog switch 107 has an electric potential of zero or a high impedance state depending on the data signal XI.

Next, the following description will discuss a drive voltage to be applied to the liquid crystal panel 1 by the scanning electrode drive circuit 31 and the segmented electrode drive circuit 32 .

The switching circuits SW in the analog switch array 37 of the scanning electrode drive circuit 31 are supplied with V c0 =2V 0 , V c1 =1/2V 0 , V c2 =0, V c3 =−1/2V 0 , and V c4 =2V 0 , and output one of the voltage waveforms V CA , V CB , V CC , V CD , V CE and V CF shown in FIG. 6 to the scanning electrodes L based on the scanning signal YI and the control signals CB and SK. The scanning signal YI is input as a three-bit signal (Y 0 Y 1 Y 2 ). The relationship among the input scanning signal YI, control signals CB and SK, and the output voltage waveform is shown below.

TABLE 1
(Y 0 Y 1 Y 2 )	000	001	010	011	100	101
Voltage	V CA	V CB	V CC	V CD	V CE	V CF
waveform
CB = 0	V C2	V C2	V C2	V C2	V C2	V C2
SK = arbitrary
value
CB = 1	V C2	V C2	V C1	V C1	V C1	V C2
SK = 0
CB = 1	V C0	V C4	V C4	V C2	V C3	V C2
SK = 1

For example, 5, 4, 4, 3, 2, 1, 1, 0, 5, 4 . . . are supplied in this order as the scanning signal YI (decimal notation), the voltage waveforms V CF , V CE , V CE , V CD , V CC , V CB , V CB , V CA , V CF , V CE . . . are successively applied to the scanning electrode L 0 , and the voltage waveforms V CE , V CF , V CE , V CE , V CD , V CC , V CB , V CB , V CA , V CF . . . are successively applied to the scanning electrode L 1 .

The voltage waveform V CA is a selection voltage to be applied to the scanning electrode during the selecting period. The voltage waveform V CB is a blanking voltage to be applied to the scanning electrode before the selecting period. The voltage waveforms V CC , V CD , V CE and V CF is the waveforms of non-selection voltages to be applied to the scanning electrode during non-selecting periods other than the blanking period when the blanking voltage is applied.

In the scanning electrodes L, the selecting period during which a certain line of scanning electrode is selected has a duration equal to three slots (3t 0 ). As illustrated in FIG. 6 , in all of the voltages waveforms V CA to V CF , the first slot (0 to t 0 ) is 0 V. Namely, as the control signal CB of the scanning electrode drive circuit 31 , “0” is supplied in the first slot (0 to t 0 ), and “1” is supplied in the second and third slots (t 0 to 3t 0 ). In the second slot (t 0 to 2t 0 ), “0” is supplied as the control signal SK. In the third slot (2t 0 to 3t 0 ), “1” is supplied as the control signal SK.

In the segmented electrode drive circuit 32 , as the control signal SB, “0” is supplied in the first slots (0 to t 0 ), and “1” is supplied in the second and third slots (t 0 to 3t 0 ) Namely, the output of the segmented electrode drive circuit 32 to the segmented electrodes S has an electric potential of zero in the first slot, and has either a high impedance state or an electric potential of zero in the second and third slots depending on the contents of the data signal XI.

The following description will discuss the electric potential produced in the segmented electrode connected to the output terminal in high impedance state of the segmented electrode drive circuit 32 with reference to a RC equivalent circuit shown in FIGS. 7 and 8 . In order to simplify the explanation, the following explanation is made with reference to two lines of segmented electrodes S j and S k , and eight lines of scanning electrodes L 0 to L 7 capacitive-coupled to these segmented electrodes.

In the first slot, since the electric potential of all of the scanning electrodes L and the segmented electrodes S is zero, the electric charges of all of the pixels on the segmented electrodes S j and S k are zero.

In the second slot, “1” is supplied as the control signal SB to the segmented electrode drive circuit 32 . Consequently, the output from the output terminal of the segmented electrode drive circuit 32 to the segmented electrodes has either a high impedance state or an electric potential of zero depending on the data signal XI. In FIG. 7 , electric potentials of 0, 0, 0, V 0 /2, V 0 /2, V 0 /2, V 0 /2 and 0 are applied to the scanning electrodes L 0 to L 7 , respectively, in the second slot, the segmented electrode S j has a high impedance state, and the segmented electrode S k has an electric potential of zero.

In this case, since the output terminal connected to the segmented electrode S j has a high impedance state, electric charges are not input/output from the segmented electrode drive circuit 32 to the segmented electrode S j . Moreover, a liquid crystal is present at each intersection of the scanning electrodes L and the segmented electrodes S of the liquid crystal panel 1 , i.e., at each pixel, and forms a capacitive load. Therefore, the electric charges held by the pixels on the segmented electrode S j of high impedance state are not readily discharged, and are retained. Namely, the segmented electrode S j keeps a voltage just before the output terminal of the segmented electrode drive circuit 32 turns into the high impedance state.

More specifically, the electric potential produced in the segmented electrode S j of high impedance state in the second slot is given by

V Lav +Q total /C total

where V Lav is the average electric potential of all of the scanning electrodes capacitive-coupled to the segmented electrode S j , Q total is the total of the electric charges remaining on the pixels on the segmented electrode S j , and C total is the total capacity between the segmented electrode S j and all of the scanning electrodes capacitive-coupled to the segmented electrode S j .

In the segmented electrode S j , since V Lav is V 0 /4 and the electric charges injected to the segmented electrode S j in the first slot is zero, Q total is zero. Namely, an electric potential of V 0 /4 appears on the segmented electrode S j in the second slot.

In other words, such an electric potential that causes no electric charge to be output/input to the segmented electrode S j of high impedance state and the total of electric charges on all of the pixels on the segmented electrode S j to be zero, i.e., the average electric potential of all of the capacitive-coupled scanning electrodes appears on the segmented electrode S j .

In the following third slot, as illustrated in FIG. 8 , voltages of 2V 0 , −V 0 , −V 0 , −V 0 , 0, −V 0 /2, −V 0 /2, 0 are applied to the scanning electrodes L 0 to L 7 , respectively, and V Lav is −V 0 /4. Since the electric charges injected in the first slot is zero and no electric charge is input/output in the second slot because of the high impedance state of the segmented electrode S j , Q total is zero. Consequently, an electric potential of −V 0 /4 appears on the segmented electrode S j in the third slot.

The electric potential −V 0 /4 of the segmented electrode S j may also be obtained as follows.

Assuming that the electric charges on the pixels formed at the intersections of the segmented electrode S j and the scanning electrodes L 0 to L 7 are Q a , Q b , Q c , Q d , Q e , Q f , Q g , Q h , respectively, each of the pixels has a uniform capacity C, and the segmented electrode S j has an electric potential V X , the following equations are written:

Q a =C (2 V 0 −V X )  equation (1)

Q b =C (− V 0 −V X )  equation (2)

Q c =C (− V 0 −V X )  equation (3)

Q d =C (− V 0 −V X )  equation (4)

Q e =C (0 −V X )  equation (5)

Q f =C (− V 0 /2 −V X )  equation (6)

Q g =C (− V 0 /2 −V X )  equation (7)

Q h =C (0 −V X )  equation (8)

It is known from these equations that

Q b =Q c =Q d

Q e =Q h

Q f =Q g

Since the total, Q total , of the electric charges remaining on the pixels on the segmented electrode s j is zero, it is written that

Q a +Q b +Q c +Q d +Q e +Q f +Q g +Q h =0

Then,

Q a +3 Q b +2 Q e +2 Q f =0

By substituting equations (1), (2), (5) and (6) for this equation, it is written that

V x =−V 0 /4

The following equation is obtained from V x and equation (8).

Q h =C (0 +V 0 /4)= CV 0 /4

If Q h =Q 1 , as shown in FIG. 8 ,

Q a =9 Q 1

Q b =Q c =Q d =−3 Q 1

Q e =Q h =Q 1

Q f =Q g =−Q 1

Thus, by applying the voltage waveforms V CA , V CB , V CB , V CC , V CD , V CE , V CE and V CF shown in FIG. 6 to the scanning electrodes L 0 to L 7 , respectively, and by switching the control signals CB and SB between ON and OFF in the manner mentioned above, the electric potential of the segmented electrode S j which causes an output from the segmented electrode drive circuit 32 a to be in a high impedance state has the voltage waveform VSG shown in FIG. 6 . On the other hand, the electric potential of the segmented electrode S k which causes an output from the segmented electrode drive circuit 32 to have an electric potential of zero has the voltage waveform V SH .

Consequently, the voltage waveform V A-G or V A-H is applied to the pixels on the scanning electrode to which the selection voltage (V CA ) is applied, depending on the data signal XI. The voltage waveform V A-G has a pulse height of 0 V in the first slot, −V 0 /4 in the second slot, and 2V 0 +V 0 /4=5V 0 /4 in the third slot. The voltage waveform V A-G does not switch the state of pixel. On the other hand, the voltage waveform V A-H has a pulse height of 0 V in the first slot, 0 V in the second slot and 2V 0 in the third slot, and switches the state of pixel.

The electric potential of the segmented electrode S j was actually examined using an oscilloscope. As a result, the voltage waveform V SG appeared on CH 2 as shown in FIG. 9 . When the data signal XI was switched every six slots equivalent to two selecting periods, it was confirmed that the two voltage waveforms V SG and two voltage waveforms V SH alternately appeared on CH 2 as shown in FIG. 10 and a plurality of electric potentials were generated in the segmented electrode S j .

As described above, in this embodiment, it is possible to arrange the number of analog switches per segmented electrode to be one in the segmented electrode drive circuit 32 , thereby simplifying the structure of the segmented electrode drive circuit 32 . Therefore, when forming the segmented electrode drive circuit 32 as an IC, if the area of a silicon wafer and the number of output terminals per IC are fixed, the area of each analog switch can be increased and the output impedance can be lowered compared to the structure requiring two analog switches for each output terminal. On the other hand, if a lowering of the output impedance is not required, it is possible to reduce the area of the silicon wafer per IC on condition that the number of output terminals is fixed. It is therefore possible to produce a drive circuit of a passive-matrix type liquid crystal display apparatus at reduced costs.

Embodiment 2

The following description will discuss another embodiment of the present invention with reference to FIGS. 11 to 15 and 23 . The structures performing the same functions as in Embodiment 1 will be designated with the same numbers, and the explanation thereof will be omitted.

A liquid crystal panel in a ferroelectric liquid crystal display apparatus of this embodiment has the same structure as that of the liquid crystal panel 1 of Embodiment 1 except for the electrode structure.

FIG. 11 is a plan view showing the electrode structure of the liquid crystal panel of this embodiment. In this liquid crystal panel, one pixel is formed by three lines of scanning electrodes and one line of segmented electrode. In the description below, three pixels formed by three lines of scanning electrodes L iA , L iB and L iC (i=0, 1 . . . ) and one line of segmented electrode S j (j=0, 1 . . . ) are referred to as sub-pixels A ijA , A ijB and A ijC , respectively. The three sub-pixels A ijA , A ijB and A ijC form one pixel A ij . A scanning electrode drive circuit is connected to the scanning electrodes L through output terminals DL iA , DL iB and DL iC . A segmented electrode drive circuit is connected to the segmented electrodes S through an output terminal DS j .

The ferroelectric liquid crystal display apparatus of this embodiment achieves a multiple gray scale display by the following drive scheme.

In the scanning electrodes L, the three lines of scanning electrodes L iA , L iB and L iC forming one pixel are selected at a time. However, as to be described later, the waveforms of selection voltages to be applied to the three lines of scanning electrodes in a selecting period differ from each other as shown in FIG. 13 . In a scanning method employed by this drive scheme, first, three lines of scanning electrodes L 0A , L 0B and L 0C are simultaneously selected, and a non-selection voltage is applied to other scanning electrodes. Next, three lines of scanning electrodes L 1A , L 1B and L 1C are simultaneously selected, and a non-selection voltage is applied to other scanning electrodes.

In FIG. 12 , G 1 shows the relationship between the pulse height V S and pulse width τ of a pulse in the first slot required for switching 90 percent of the region of the pixel, and G 2 shows the relationship between the pulse height V S and pulse width τ of a pulse in the first slot required for switching 10 percent of the region of the pixel when pulses of two slots with equal width are successively applied to the pixel of the liquid crystal panel of this embodiment (i.e., when a voltage having a pulse height V S is applied in the first slot and a voltage having a pulse height (40−V S ) is applied in the second slot).

As is clear from FIG. 12 , for example, when the pulse width is 80 μs, in order to switch the pixel, it is necessary to apply a switching voltage waveform so that the pulse height V S in the first slot is, for example, a pulse height (V S =0.8 V) at point A in a region higher than a threshold value (G 1 ) for switching 90 percent of the region and that the pulse height in the second slot is 39.2 V.

On the other hand, when the pixel is not to be switched, it is necessary to apply a non-switching voltage waveform so that the pulse height V S in the first slot is, for example, a pulse height (V S =−3.2 V) at point B in a region lower than a threshold value (G 2 ) for switching 10 percent of the region and that the pulse height in the second slot is 43.2 V.

FIG. 13 is a waveform illustration of three kinds of selection voltages applied to the scanning electrodes L iA , L iB and L iC and a signal voltage applied to the segmented electrodes S, for achieving the above-mentioned switching waveform and non-switching waveform, and the resultant switching voltage waveform and non-switching voltage waveform.

V CA , V CB and V CC shown in FIG. 13 are selection voltages applied to the scanning electrodes L iA , L iB and L iC , respectively, in the selecting period. V SE , V SF , V SG and V SH shown in FIG. 13 are signal voltages applied to the segmented electrode S j in the selecting period.

In this case, V a to V f and V 1 to V 4 shown in FIG. 13 satisfy the following conditions at the same time.

V e −V 4 =V c −V 3 =V a −V 2 =0.8 V

V f +V 4 =V d +V 3 =V b +V 2 =39.2 V

V e −V 3 =V c −V 2 =V a −V 1 =−3.2 V

V f +V 3 =V d +V 2 =V b +V 1 =43.2 V

V 1 =V 2 +4 V=V 3 +8 V=V 4 +12 V

V a =V c +4 V=V e +8 V

V f =V d +4 V=V b +8 V

V e =V 4 +0.8 V

Although V f and V 1 can be determined arbitrarily, it is arranged in this case that V f =V 1 =25.6 V. Accordingly, V d =V 2 =21.6 V, V b =V 3 =17.6 V, V 4 =13.6 V. V e =14.4 V, V c =18.4 V, and V a =22.4 V.

By arranging the pulse height in the first slot to be aV 0 (−1<a<1, V 0 =40 V), the pulse height in the second slot to be (1−a)V 0 , and the pulse width in the first and second slots to be the same, it is possible to readily achieve a DC balance of liquid crystal molecules constituting a pixel.

In this case, when V SE is applied to the segmented electrode S j in the selecting period, all of the three sub-pixels A ijA , A ijB and A ijC are switched to one of the stable states as shown in FIG. 12 by the waveforms V A-E , V B-E and V C-E applied to A ijA , A ijB and A ijC , respectively. When V SF is applied to the segmented electrode S j , the sub-pixels A ijA and A ijB are switched to one of the stable states but A ijC is not switched by the waveforms V A-F , V B-F and V C-F . When V SG is applied to the segmented electrode S j , only the sub-pixel A ijA is switched to one of the stable states, and sub-pixels A ijB and A ijC are not switched. When V SH is applied to the segmented electrode S j , none of the sub-pixels A ijA , A ijB and A ijC are switched. It is thus possible to achieve displays in four levels of gray scale.

With the achievement of such driving, when ferroelectric liquid crystals having negative dielectric anisotropy are used, the memory pulse width of ferroelectric liquid crystal molecules varies depending on two successive pulses. Specifically, when the pulses are of the same polarity, E min becomes greater and τ min becomes smaller against the voltage in the second slot as the absolute value of the voltage in the first slot increases. On the other hand, when the pulses have the opposite polarities, E min becomes smaller and τ min becomes greater against the voltage in the second slot as the absolute value of the voltage in the first slot increases. In this embodiment, the polarity of the voltage in the second slot is determined on condition that it switches the liquid crystal molecules to one of the stable states.

The above-mentioned values of the voltages V a , V b , V c , V d , V e , V f , V 1 , V 2 , V 3 and V 4 are merely examples, and these voltages are arbitrarily determined within a range satisfying all of the following conditions.

V a >V c >V e >0

V a +V b =V c +V d =V e +V f

V a −V 3 =V c −V 4

V c −V 3 =V e −V 4

V a −V 2 =V c −V 3

  V c −V 2 =V e −V 3

V a −V 1 =V c −V 2

V c −V 1 =V e −V 2

V 4 <V 3 <V 2 <V 1

The waveforms applied to the pixels in the selecting period has been explained above. Next, the waveforms applied to the pixels in the non-selecting period will be discussed.

This embodiment is characterized by alternately applying voltages waveforms V CE and V CF shown in FIG. 14 to the scanning electrodes L that are not selected. In this characteristic, it is possible to reduce the variation in the root-mean-square value of the bias voltage and improve the contrast. The pulse heights V g and V h of the voltage waveforms V CE and V CF satisfy the condition

V g <( V max +V min )/2 <V h

where V max is a maximum of the pulse heights V 1 to V 4 of the signal voltages applied to the segmented electrodes S, and V min is a minimum thereof.

For example, when the pulse heights V 4 , V 3 , V 2 and V 1 of the voltage waveforms V SE , V SF , V SG and V SH are 2V 0 , 4V 0 , 6V 0 and 8V 0 , respectively, V max is 8V 0 and V min is 2V 0 . Therefore, for example, it is possible to make V g =3V 0 and V h =7V 0 .

In this case, when the voltage waveforms V SE and V SH are applied to the segmented electrode in the non-selecting period, the average root-mean-square value of the bias voltage is given by

((( V 0 ) 2 +(5 V 0 ) 2 )/2) ½ ≈3.6 V 0

When the voltage waveforms V SF and V SG are applied to the segmented electrode in the non-selecting period, the average root-mean-square value of the bias voltage is given by

((( V 0 ) 2 +(3 V 0 ) 2 )/2) ½ ≈2.2 V 0

The ratio of these average root-mean-square values is given by

3.6 V 0 /2.2 V 0 ≈1.6

In a drive scheme disclosed in Japanese Publication for Unexamined Patent Application (Tokukaihei) No. 8-50278 (1996), for example, a bipolar pulse (shown in FIG. 23 ) of pulse height V k

V k =( V 2 +V 3 )/2

is applied to the scanning electrodes L in the non-selecting period. In this case, V k =5V 0 , and the average root-mean-square value of the bias voltage is 3V 0 when the voltage waveforms V SE and V SH are applied to the segmented electrodes S. On the other hand, the average root-mean-square value of the bias voltage is V 0 when the voltage waveforms V SF and V SG are applied to the segmented electrodes S. The ratio of these average values is given by

3 V 0 /V 0 =3.0

Namely, it was found that the ferroelectric liquid crystal display apparatus of this embodiment achieves a smaller variation in the root-mean-square value of the bias voltage compared to a conventional structure. In general, as the difference between the pulse heights V g , V h and the average pulse height of the signal voltage applied to the segmented electrodes S is increased, the variation in the root-mean-square value of the bias voltage is reduced.

It has been explained with reference to FIG. 14 that two kinds of pulses V CE and V CF are alternately applied to the scanning electrodes L in the non-selecting period. However, it is also possible to use the voltage waveform V CE of two slots formed by two pulses of the same polarity and pulse height and the voltage waveform V CF of the same pulse height and the opposite polarity to the voltage waveform V CE as shown in FIG. 15 . In this case, the voltage waveforms V CE and V CF are alternately applied at an interval of n selecting period (n is an integer not smaller than 1). The pulse height V X of the voltage waveforms V CE and V CF switches to V g or V h every two selecting periods. As a result, the same effects as those mentioned above can be produced.

As described above, in this embodiment, displays in four levels of gray scale are achieved by forming one pixel from three lines of scanning electrodes and one line of segmented electrode, simultaneously applying scanning voltages of different selection voltage waveforms to the three lines of scanning electrodes, and applying any one of four kinds of signal voltages to the segmented electrode. Moreover, by adjusting the pulse height of the voltage waveform to be applied to the scanning electrode in the non-selecting period, the variation in the root-mean-square value of the bias voltage is reduced compared to the conventional structure. As a result, a ferroelectric liquid crystal display apparatus with gray scale display capabilities and high contrast is achieved.

Embodiment 3

The following description will discuss still another embodiment of the present invention with reference to FIGS. 2 , 3 , 16 to 18 .

A ferroelectric liquid crystal display apparatus of this embodiment is characterized by including the liquid crystal panel 1 shown in FIG. 2 and temperature measuring means, not shown, for measuring the temperature of the FLC 8 . This ferroelectric liquid crystal display apparatus is also characterized in compensating a change of the memory angle of the FLC 8 caused by a change in temperature by superimposing a DC voltage on a drive voltage to be applied to the scanning electrodes L, based on the temperature change from a predetermined reference temperature.

First, the relationship between the change in temperature and the memory angle of molecules of the FLC 8 will be explained. As discussed in Embodiment 1, the ferroelectric liquid crystal molecule 51 constituting the FLC 8 has two stable states, positions P 1 and P 2 , as shown in FIG. 3 ( a ). An angle formed by the molecule long axis of the liquid crystal molecule 51 in the position P 1 and a center axis 52 is called a memory angle θ m as shown in FIG. 3 ( a ). As illustrated in FIG. 16 , the memory angle θ m changes depending on the temperature of the FLC 8 . For example, it can be seen that the memory angle is around ±5° at 30° C., decreases with a rise in temperature, and becomes around ±3° at 45° C.

It was found that, after switching the liquid crystal molecule 51 to the first or second stable state by applying a switching voltage thereto, if a DC voltage is further applied, the liquid crystal molecule 51 shifts from the stable state, i.e., position P 1 or P 2 , according to the voltage applied.

Like Japanese Publication for Unexamined Patent Application (Tokukaihei) No. 7-120722 (1995), the liquid crystal molecule 51 is switched to the second stable state by aligning the polarization axis of the polarizing plate with the center axis 52 shown in FIG. 3 ( a ) and applying a positive switching voltage. In this condition, a voltage is further applied, and g 1 in FIG. 17 shows the amount of transmitted light against the voltage. Similarly, the liquid crystal molecule 51 is switched to the first stable state by applying a negative switching voltage. In this condition, a voltage is further applied, and g 2 in FIG. 17 shows the amount of transmitted light against the voltage. When the molecule long axis of the liquid crystal molecule 51 is aligned with the center axis 52 , i.e., the polarization axis of the polarizing plate, the amount of transmitted light is zero. The amount of transmitted light increases as the molecule long axis of the liquid crystal molecule 51 approaches a tilted axis 53 or 54 .

It can be seen from FIG. 17 that when a positive voltage is further applied to the ferroelectric liquid crystal molecule 51 which has been switched to the second memory state with the application of a positive switching voltage, the ferroelectric liquid crystal molecule 51 further moves from the position P 2 toward the tilted angle 54 . It can be also known that when a negative voltage is further applied to the ferroelectric liquid crystal molecule 51 which has been switched to the first memory state with the application of a negative switching voltage, the ferroelectric liquid crystal molecule 51 further moves from the position P 1 toward the tilted angle 53 .

With the use of such phenomena, it is possible to compensate a change of the memory angle θ m resulting from a change in temperature. More specifically, the drive voltage applied to the scanning electrodes L at a temperature T 0 has, for example, a waveform shown at the top in FIG. 18 . This waveform is the same as the waveform of the drive voltage of the scanning electrode according to the J/A drive scheme explained in Embodiment 1. Namely, the selecting period is formed by two slots (0 to 2t 0 ), and a strobe pulse with a pulse height of 2V 0 is applied in the second slot of the selecting period. In addition, a blanking pulse of the opposite polarity to the strobe pulse and a pulse height of V 0 is applied twice before the selecting period.

Furthermore, the polarization axis of the polarizing plate 10 is positioned according to the memory angle θ m0 of the liquid crystal molecule 51 at temperature T 0 . More specifically, the polarizing plate 10 is positioned so that the polarization axis is aligned with the molecule long axis when the liquid crystal molecule 51 is in one of the stable states at temperature T 0 .

When the temperature becomes higher than T 0 , the memory angle θ m of the liquid crystal molecule 51 becomes smaller than θ m0 . At this time, as shown by the middle waveform in FIG. 18 , a negative voltage having pulse height V m corresponding to the rise of temperature from T 0 is superimposed from the selecting period to the blanking period. In this case, the pulse heights of the strobe pulse and blanking pulse do not vary.

Additionally, a positive voltage having a pulse height V P for cancelling the DC component of the superimposed negative voltage is applied after the blanking pulse. Since the dielectric anisotropy of the ferroelectric liquid crystals used in this embodiment is negative, the positive voltage V P satisfy the condition

V P >2 V 0

and a blanking voltage −V 0 is applied just before the application of the positive voltage V P , the liquid crystal molecule 51 is not switched to the other stable state by the positive voltage V P .

By applying the negative voltage V m in such a manner, the change of the memory angle caused by a rise in temperature is compensated, and the long axis of the liquid crystal molecules in one of the stable states and the polarization axis of the polarizing plate 10 are kept in alignment.

On the other hand, when the temperature becomes lower than T 0 , as shown by the bottom waveform in FIG. 18 , a positive voltage having a pulse height V n corresponding to the lowering of temperature from T 0 is superimposed from the selecting period to the blanking period. In this case, the pulse heights of the strobe pulse and blanking pulse do not vary. In addition, a negative voltage having a pulse height V N for cancelling the DC component of the superimposed positive voltage is applied after the blanking pulse. Even when the negative voltage is provided to switch the liquid crystal molecule 51 to the other stable state, the display of pixel is not affected because the liquid crystal molecule 51 has been switched to the other stable state by the blanking pulse applied just before the application of the negative voltage V N .

Consequently, like the case of the temperature rise, the change of the memory angle caused by the lowering of temperature is compensated, and the long axis of the liquid crystal molecules in one of the stable states and the polarization axis of the polarizing plate 10 are kept in alignment.

In the above-mentioned explanation, for example, the molecule long axis of the liquid crystal molecule 51 in one of the stable states and the polarization axis of the polarizing plate 10 are aligned. However, needless to say, the molecule long axis and the polarization axis of the polarizing plate 11 may be aligned with each other.

As described above, in this embodiment, the change of the memory angle depending on a change in temperature can be compensated by a drive voltage applied to the scanning electrodes L. Consequently, it is possible to achieve a ferroelectric liquid crystal display apparatus capable of retaining good contrast even if the temperature of the FLC 8 varies due to a change in ambient temperature and heat generated by itself when driven.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims

1. A passive-matrix type liquid crystal display apparatus having a pixel formed by a liquid crystal lying at each intersection of scanning electrodes and segmented electrodes, characterized in that:said liquid crystal is a ferroelectric liquid crystal; and a DC voltage varying according to a measured change in temperature of said liquid crystal is superimposed over a drive voltage applied to said scanning electrodes, wherein a blanking voltage is applied to said scanning electrodes before a selecting period, and a voltage for cancelling a superimposed DC component is applied to said scanning electrodes after said blanking voltage and before said selecting period.

2. The passive-matrix type liquid crystal display apparatus according to claim 1,wherein said ferroelectric liquid crystal has negative dielectric anisotropy.