A base deck 102 mates with a top cover (not shown) to form an enclosed housing. A spindle motor 104 is mounted within the housing to controllably rotate media 106, preferably characterized as magnetic recording discs.
A controllably moveable actuator 108 moves an array of read/write transducers 110 adjacent tracks defined on the media surfaces through application of current to a voice coil motor (VCM) 112. A flex circuit assembly 114 provides electrical communication paths between the actuator 108 and device control electronics on an externally mounted printed circuit board (PCB) 116.
Remote users respectively access the fabric 130 via personal computers (PCs) 132, 134, 136. In this way, a selected user can access the storage space 122 to write or retrieve data as desired.
The devices 100 and the controllers 124, 126 are preferably incorporated into a multi-device array (MDA). The MDA preferably uses one or more selected RAID (redundant array of independent discs) configurations to store data across the devices 100. Although only one MDA and three remote users are illustrated in
Policy processors 156, 158 execute a real-time operating system (RTOS) for the controller 140 and communicate with the respective ISPs 142, 144 via PCI busses 160, 162. The policy processors 156, 158 can further execute customized logic to perform sophisticated processing tasks in conjunction with the ISPs 142, 144 for a given storage application. The ISPs 142, 144 and the policy processors 156, 158 access memory modules 164, 166 as required during operation.
A number of list managers, denoted generally at 170 are used for various data and memory management tasks during controller operation, such as cache table management, metadata maintenance, and buffer management. The list managers 170 preferably perform well-defined albeit simple operations on memory to accomplish tasks as directed by the FCCs 168. Each list manager preferably operates as a message processor for memory access by the FCCs, and preferably executes operations defined by received messages in accordance with a defined protocol.
The list managers 170 respectively communicate with and control a number of memory modules including an exchange memory block 172, a cache tables block 174, buffer memory block 176 and SRAM 178. The function controllers 168 and the list managers 170 respectively communicate via a cross-point switch (CPS) module 180. In this way, a selected function core of controllers 168 can establish a communication pathway through the CPS 180 to a corresponding list manager 170 to communicate a status, access a memory module, or invoke a desired ISP operation.
Similarly, a selected list manager 170 can communicate responses back to the function controllers 168 via the CPS 180. Although not shown, separate data bus connections are preferably established between respective elements of
A PCI interface (I/F) module 182 establishes and directs transactions between the policy processor 156 and the ISP 142. An E-BUS I/F module 184 facilitates communications over the E-BUS 146 between FCCs and list managers of the respective ISPs 142, 144. The policy processors 156, 158 can also initiate and receive communications with other parts of the system via the E-BUS 146 as desired.
The controller architecture of
Accordingly,
A source device 202 preferably communicates with first and second target devices 204, 206 via a common pathway 208, such as a multi-line data bus. The pathway in
The source device 202 is preferably configured to concurrently transfer a data, such as a data packet, to the first and second target devices 204, 206 over the pathway 208. Preferably, the data packet is concurrently received by respective FIFOs 216, 218 for subsequent movement to memory spaces 220, 222, which in the present example preferably represent different cache memory locations within the controller architecture.
In response to receipt of the transferred packet, the target devices 204, 206 each preferably transmit separate acknowledgement (ACK) signals to the source device to confirm successfully completion of the data transfer operation. The ACK signals can be supplied at the completion of the transfer or at convenient boundaries thereof.
In a first preferred embodiment, the concurrent transfer takes place in parallel as shown by
Although not required, it is contemplated that such synchronous transfers are particularly suitable when the target devices are nominally identical (e.g., buffer managers in nominally identical chip sets such as the ISPs 142, 144). However, transfers can take place to different types of devices so long as the transfer rate can be accommodated by the slower of the two target devices. Upon completion, each device 204, 206 supplies a separate acknowledgement (ACK1 and ACK 2) via separate communication paths 226, 228 as shown.
Alternatively,
All of the data can be written to the first device 204 prior to the writing of the data to the second device 206; alternatively, portions of the overall data packet can be alternately sent to the respective devices in turn. It will be noted that the sequential transfer may preferably involve duplicate DMA operations to each target device. The transfers may further take place at different rates, such as indicated by separate clock input lines 230, 232.
As before, the devices supply respective ACK1 and ACK2 signals back to the source device 202 at the conclusion of the data transfer to confirm successful receipt of the data. Additional acknowledgement signals can also be sent at appropriate times during the transfer as well. Other alternatives are also contemplated, including the transfer of a data packet some portions of which are transferred in parallel and other portions of which are transferred sequentially.
It will be noted that the foregoing alternative approaches advantageously mirror the data in multiple locations in an efficient manner while providing separate confirmation for each written data set. For example, as shown in
At step 252, parallel target devices, such as 204, 206 are first provided in communication with a source device such as 202 via a communication pathway. This pathway can include a physical chipset boundary such as shown in
At step 254, a concurrent data transfer is initiated from the source device to the target devices. For example, the source device may include a FIFO or other memory space that stores data received from the server 128 for ultimate storage to the devices 100. In such case, the data may be desirably mirrored within the controller architecture 140 during the processing of this data in preparation for subsequent writing of the data to the media 106.
The concurrent transfer can comprise a synchronously clocked transfer as shown by step 256, and/or a sequential transfer that takes place at different rates as shown by step 258.
At step 260, separate acknowledgement (ACK) signals are transmitted back to the source device to confirm receipt. While it is contemplated that the target devices will be configured to transmit the ACK signals automatically, it will be appreciated that the separate signals can be forwarded in response to a subsequent polling request initiated by the source device.
Further processing can take place as desired once the data are acknowledged as being successfully mirrored. For example, SGL, SBL and other metadata structures can be accurately maintained and updated in real time based on the confirmation supplied by the respective ACK signals.
The source device can generate the data as a result of an ongoing processing operation, such as an XOR operation to generate higher level RAID parity values (e.g., RAID-5, RAID-6, etc.). In this case, the data are preferably generated and passively mirrored to multiple target locations on-the-fly.
The foregoing embodiments have preferably characterized the data transferred by the source to the target devices as comprising array data; that is, data that is ultimately striped to the media 106 during a write operation, or data that has been recovered from the media 106 during a read operation. However, such is not necessarily required. Rather, the data can take any number of forms, including metadata structures (including SGLs or SBLs, etc.), commands, status information, or other inter-device communications.
While preferred embodiments presented herein have been directed to a multi-device array utilizing a plurality of disc drive storage devices, it will be appreciated that such is merely for purposes of illustration and is not limiting. Rather, the claimed invention can be utilized in any number of various environments to promote efficient data mirroring.
It is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this detailed description is illustrative only, and changes may be made in detail, especially in matters of structure and arrangements of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed. For example, the particular elements may vary depending on the particular application without departing from the spirit and scope of the present invention.