Passive switched-capacitor filters conforming to power constraint

Abstract

Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

Description

BACKGROUND

I. Field

The present disclosure relates generally to electronics, and more specifically to filters.

II. Background

Filters are commonly used to filter signals to pass desired signal components and to attenuate undesired signal components. Filters are widely used for various applications such as communication, computing, networking, consumer electronics, etc. For example, in a wireless communication device such as a cellular phone, filters may be used to filter a received signal to pass a desired signal on a specific frequency channel and to attenuate out-of-band undesired signals and noise. For many applications, filters that occupy small area and consume low power are highly desirable.

SUMMARY

Passive switched-capacitor (PSC) filters that may occupy smaller area and consume less power are described herein. In one design, a PSC filter may implement a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. The second-order IIR filter may not meet a power constraint whereas each complex first-order IIR section may meet the power constraint. The coefficients for the two complex first-order IIR sections may be determined based on the coefficients for the second-order IIR filter, as described below. Each complex first-order IIR section may be implemented with a PSC filter section comprising multiple capacitors and multiple switches.

In another design, a PSC filter may implement one or more complex filter sections (e.g., two complex first-order IIR sections) coupled in series. Each complex filter section includes first, second, and third sets of capacitors. The first set of capacitors (e.g., capacitors 1024a and 1034a in FIG. 10) receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. The second set of capacitors (e.g., capacitors 1024b and 1034b in FIG. 10) receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. The third set of capacitors (e.g., capacitors 1044 and 1054 in FIG. 10) receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. Each complex filter section further includes first, second, third and fourth sets of switches. The first set of switches couples the first set of capacitors to a first summing node. The second set of switches couples the second set of capacitors to a second summing node. The third set of switches couples the third set of capacitors to the first summing node. The fourth set of switches couples the third set of capacitors to the second summing node. Each capacitor stores a value from an associated summing node when selected for charging and shares electrical charge with other capacitors via the associated summing node when selected for charge sharing.

In yet another design, a PSC filter may implement a finite impulse response (FIR) section coupled to an IIR section, which may be for a complex first-order IIR filter. The FIR section receives and filters a complex input signal and provides a complex filtered signal. The IIR section receives and filters the complex filtered signal and provides a complex output signal. The FIR and IIR sections may be implemented with two PSC filter sections. Each PSC filter section may include a bank of complex filter sections that may be enabled in different clock cycles.

In yet another design, a PSC filter section includes first and second complex filter sections and may be used for the FIR or IIR section described above. The first complex filter section receives and filters a complex input signal and provide a complex output signal every M clock cycles, where M is greater than one. The second complex filter section receives and filters the complex input signal and provides the complex output signal every M clock cycles. The first and second complex filter sections may be enabled in different clock cycles. For example, with M=2, the first complex filter section may be enabled in even-numbered clock cycles, and the second complex filter section may be enabled in odd-numbered clock cycles.

Various aspects and features of the disclosure are described in further detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a second-order FIR filter.

FIG. 2 shows a PSC filter that implements the second-order FIR filter.

FIG. 3 shows a timing diagram for the PSC filter in FIG. 2.

FIG. 4 shows a block diagram of a second-order IIR filter.

FIG. 5 shows a PSC filter that implements the second-order IIR filter.

FIG. 6 shows a timing diagram for the PSC filter in FIG. 5.

FIG. 7 shows a process for designing a PSC filter with coefficient scaling.

FIG. 8 shows filtering with complex second-order IIR filters.

FIG. 9 shows a block diagram of a complex first-order IIR section.

FIG. 10 shows a PSC filter that implements the complex first-order IIR section.

FIG. 11 shows a timing diagram for the PSC filter in FIG. 10.

FIG. 12 shows a PSC filter that implements two complex first-order IIR sections.

FIG. 13 shows a process for designing a PSC filter with decomposition.

FIG. 14 shows a complex first-order IIR section implemented with a FIR filter bank and an IIR filter bank.

FIG. 15 shows a PSC filter that implements the IIR filter bank in FIG. 14.

FIG. 16 shows a plot of pole movement due to filter bank transformation.

FIG. 17 shows a process for designing a PSC filter with filter bank transformation.

FIG. 18 shows a plot of a function affecting power constraint.

FIG. 19 shows a process for designing an IIR filter to meet power constraint.

FIG. 20 shows a block diagram of a wireless communication device.

DETAILED DESCRIPTION

The PSC filters described herein may be used for various types of filters such as FIR filters, IIR filters, auto regressive moving average (ARMA) filters composed of FIR and IIR sections, etc. The PSC filters may also implement a filter of any order, e.g., first, second, third or higher order. Multiple PSC filter sections may be used to form more complex filters. For clarity, PSC filters for second-order FIR filter and for first-order and second-order IIR filters are described in detail below.

A PSC filter may be implemented with only capacitors and switches, without using active circuits. This may provide certain advantages described below. However, due to the passive nature of the PSC filter, not all filter transfer functions may be directly implementable with the PSC filter. The PSC filter can implement a filter transfer function that meets a power constraint. Various schemes to meet the power constraint are described below and are based on observation that the total electrical charges before and after each charge sharing operation in the PSC circuit should be keep constant. This implies that a FIR filter is implementable if its coefficients are scaled so that they sum to 1. For an IIR filter, several schemes for meeting the power constraint are described below and include coefficient scaling, complex filter section decomposition, filter bank transformation, and pole repositioning.

FIG. 1 shows a block diagram of a second-order FIR filter 100 that may be implemented with a PSC filter. FIR filter 100 includes two delay elements 112 and 114 coupled in series, with each delay element providing a delay of one clock cycle. Delay element 112 receives an input sample x(n) and provides a delayed sample x(n−1). Delay element 114 receives the delayed sample x(n−1) and provides a delayed sample x(n−2). FIR filter 100 includes two FIR taps 1 and 2 for second order. A multiplier 120 (which may be considered as being for FIR tap 0) is coupled to the input of delay element 112. A multiplier 122 for FIR tap 1 is coupled to the output of delay element 112. A multiplier 124 for FIR tap 2 is coupled to the output of delay element 114. Multipliers 120, 122 and 124 multiply their samples with filter coefficients b₀, b₁ and b₂, respectively. A summer 130 is coupled to the outputs of all three multipliers 120, 122 and 124. Summer 130 sums the outputs of multipliers 120, 122 and 124 and provides an output sample y(n).

The output sample y(n) from FIR filter 100 may be expressed as:y(n)=b₀·x(n)+b₁·x(n−1)+b₂·x(n−2).  Eq (1)

A transfer function H_FIR(z) for FIR filter 100 in the z-domain may be expressed as:H_FIR(z)=b₀+b₁·z⁻¹+b₂·z⁻²,  Eq (2)where z^−k denotes a delay of k clock cycles.

The filter coefficients may be defined to meet the following power constraint for FIR filter:|b₀|+|b₁|+|b₂|=1.  Eq (3)

If coefficients b₀, b₁ and b₂ do not meet the power constraint in equation (3), then the coefficients may be scaled as follows:

$\begin{array}{cc}{b}_0^{\prime }=K_{\mathrm{FIR}}·b_0,& \mathrm{Eq}\left(4a\right)\\ b_1^{\prime }=K_{\mathrm{FIR}}·b_1,\mathrm{and}& \mathrm{Eq}\left(4b\right)\\ b_2^{\prime }=K_{\mathrm{FIR}}·b_2,& \mathrm{Eq}\left(4c\right)\\ \mathrm{where}{K}_{\mathrm{FIR}}=\frac{1}{b_0+b_1+b_2}\mathrm{is}a\mathrm{scaling}\mathrm{factor}.& \mathrm{Eq}\left(4d\right)\end{array}$

The scaling in equation set (4) results in the scaled coefficients meeting the power constraint, as follows:|b₀′|+|b₁′|+|b₂′|=1.  Eq (5)

Any set of FIR filter coefficients may be scaled to meet the power constraint in equation (5). The power constraint may also be referred to as an absolute magnitude sum constraint. The FIR filter may be implemented with the scaled coefficients and may generate scaled output sample y′(n), which may be expressed as:y′(n)=b₀′·x(n)+b₁′·x(n−1)+b₂′·x(n−2)=K_FIR·y(n).  Eq (6)

In many cases, y′(n) may be used in place of y(n). However, in cases where signal level plays a non-trivial role (e.g., to avoid signal saturation), the K_FIR scaling factor may be increased or decreased. Active devices such as amplifiers may be used to increase K_FIR. A switching pattern may be adjusted to reduce K_FIR.

FIG. 2 shows a schematic diagram of a design of a PSC filter 200 that implements second-order FIR filter 100 in FIG. 1. PSC filter 200 includes an input section 220 and two tap sections 230 and 240 for FIR taps 1 and 2, respectively, of FIR filter 100. Within PSC filter 200, an input switch 212 has one end receiving an input signal V_in and the other end coupled to a summing node A. A reset switch 214 is coupled between the summing node and circuit ground. An output switch 216 has one end coupled to the summing node and the other end providing an output signal V_out. Switches 212, 214 and 216 may be implemented with metal oxide semiconductor (MOS) transistors or other types of transistors or switches.

Input section 220 includes an input capacitor 224 coupled between the summing node and circuit ground. Tap section 230 includes two switches 232a and 232b coupled in series with two capacitors 234a and 234b, respectively. Both series combinations of switch 232 and capacitor 234 are coupled between the summing node and circuit ground. Tap section 240 includes three switches 242a, 242b and 242c coupled in series with three capacitors 244a, 244b and 244c, respectively. All three series combinations of switch 242 and capacitor 244 are coupled between the summing node and circuit ground.

All capacitor(s) in each section have the same capacitance/size, which is determined by the corresponding filter coefficient. The capacitances of the capacitors in the three sections of PSC filter 200 may be given as:C₀₀=K·b₀′,  Eq (7a)C₁₀=C₁₁=K·b₁′, and  Eq (7b)C₂₀=C₂₁=C₂₂=K·b₂′,  Eq (7c)where C_ij is the capacitance of the j-th capacitor in the section for FIR tap i, and

K is a scaling constant.

As shown in equation set (7), the size of each capacitor C_ij is proportional to the corresponding scaled coefficient b_i′. K may be selected based on various factors such as switching settling time, capacitor size, power dissipation, noise, etc. A negative capacitor for a negative coefficient may be obtained by switching the polarity of the capacitor between a read phase and a charge sharing phase.

In each clock cycle, switch 212 is closed for a brief period of time to charge one capacitor in each section with the V_in signal. The capacitor selected for charging in each tap section is determined by switches 232 and 242, as described below. The total input capacitance observed by the V_in signal for the charge operation may be expressed as:C_in=C₀₀+C_1u+C_2v,  Eq (8)where u ε {0, 1} is an index of the capacitor selected for charging in tap section 230, and

v ε {0, 1, 2} is an index of the capacitor selected for charging in tap section 240.

Since the capacitors in each tap section have the same capacitance, the total input capacitance C_in is constant for each clock cycle.

In each clock cycle, an appropriate capacitor in each tap section is used to generate the V_out signal. For FIR tap L, the capacitor charged L clock cycles earlier and storing x(n−L) is selected for use via its associated switch. The two selected capacitors in tap sections 230 and 240 and input capacitor 224 are used in a charge sharing operation that implements the multiplications with filter coefficients b₀′ through b₂′ and the summing of the multiplier outputs in equation (6).

The charge sharing operation uses capacitor size to achieve multiplication with a filter coefficient and current summing to achieve summing of the multiplier outputs. For each capacitor within PSC filter 200, the voltage V_ij across that capacitor is determined by the V_in signal at the time the capacitor is charged, or V_ij=V_in. The electrical charge Q_ij stored by each capacitor is determined by the voltage V_ij across that capacitor and the capacitance C_ij of the capacitor, or Q_ij=V_ij·C_ij. In each clock cycle, one capacitor storing the proper sample x(n−i) from each tap section is selected, and the charges from all selected capacitors as well as input capacitor 224 are shared. The charge sharing for the FIR filter may be expressed as:

$\begin{array}{cc}{V}_{\mathrm{out}}=\frac{C_{00}·V_{00}+C_{1p}·V_{1p}+C_{2q}·V_{2q}}{C_{00}+C_{1p}+C_{2q}},& \mathrm{Eq}\left(9\right)\end{array}$ where p ε {0, 1} is an index of the capacitor storing x(n−1) in tap section 230, and

q ε {0, 1, 2} is an index of the capacitor storing x(n−2) in tap section 240.

Since the capacitors in each tap section have the same capacitance, the total output capacitance C_out observed by the V_out signal is constant for each clock cycle and is equal to the total input capacitance, or C_out=C_in.

Index p can cycle between 0 and 1, so that in each clock cycle one capacitor 234 in tap section 230 is charged, and the other capacitor 234 is used for charge sharing. Index q can cycle from 0 through 2, so that in each clock cycle one capacitor 244 in tap section 240 is charged, and another capacitor 244 is used for charge sharing. PSC filter 200 may be considered as having six states for the six different (p, q) combinations.

FIG. 3 shows a timing diagram of various control signals for PSC filter 200 in FIG. 2. A clock signal CLK is shown at the top of the timing diagram. Control signals for the switches within PSC filter 200 are shown below the clock signal.

In the design shown in FIG. 3, each clock cycle includes a read/charge phase, a compute/charge sharing phase, a write/output phase, and a reset/discharge phase. For the read phase from time T₀ to time T₁, the S_in control signal is asserted, switch 212 is closed, and input capacitor C₀₀ and one capacitor in each tap section are charged with the V_in signal. The S_ij control signal for each capacitor selected for charging is asserted during the read phase and de-asserted at time T₂. For the charge sharing phase starting at time T₃, the S_ij control signal for each capacitor selected for charge sharing is asserted, and the selected capacitors in sections 230 and 240 as well as capacitor C₀₀ perform charge sharing via the summing node. For the write phase from time T₄ to time T₅, the S_out control signal is asserted, switch 216 is closed, and the voltage at the summing node is provided as the V_out signal. For the reset phase from time T₆ to time T₇, the S_reset control signal is asserted, switch 214 is closed, and the capacitors used for charge sharing are reset/discharged. These capacitors may be charged with the V_in signal in the next clock cycle.

FIG. 4 shows a block diagram of a second-order IIR filter 400 that may be implemented with a PSC filter. Within IIR filter 400, a multiplier 420 receives and scales an input sample x(n) with a filter coefficient c₀. A summer 430 subtracts the output of a summer 432 from the output of multiplier 420 and provides an output sample y(n).

Two delay elements 412 and 414 are coupled in series, with each delay element providing a delay of one clock cycle. Delay element 412 receives the output sample y(n) and provides a delayed sample y(n−1). Delay element 414 receives delayed sample y(n−1) and provides a delayed sample y(n−2). IIR filter 400 includes two IIR taps 1 and 2 for second order. A multiplier 422 for IIR tap 1 is coupled to the output of delay element 412. A multiplier 424 for IIR tap 2 is coupled to the output of delay element 414. Multipliers 422 and 424 multiply their samples with filter coefficients c₁ and c₂, respectively, for the two IIR taps. Summer 432 sums the outputs of multipliers 422 and 424 and provides its output to summer 430.

The output sample y(n) from IIR filter 400 may be expressed as:y(n)=c₀·x(n)−c₁·y(n−1)−c₂·y(n−2).  Eq (10)

A transfer function H_IIR(z) for IIR filter 400 may be expressed as:

$\begin{array}{cc}{H}_{\mathrm{IIR}}\left(z\right)=\frac{c_0}{1+c_1·z^{-1}+c_2·z^{-2}}.& \mathrm{Eq}\left(11\right)\end{array}$

FIG. 5 shows a schematic diagram of a design of a PSC filter 500 that implements second-order IIR filter 400 in FIG. 4. PSC filter 500 includes an input section 520 and two tap sections 530 and 540 for IIR taps 1 and 2, respectively, of IIR filter 400. Within PSC filter 500, an input switch 512 has one end receiving an input signal V_in and the other end coupled to a summing node A. A reset switch 514 is coupled between the summing node and circuit ground. An output switch 516 has one end coupled to the summing node and the other end providing an output signal V_out.

Input section 520 includes a capacitor 524 coupled between the summing node and circuit ground. Tap section 530 includes a switch 532 coupled in series with a capacitor 534, the combination of which is coupled between the summing node and circuit ground. Tap section 540 includes two switches 542a and 542b coupled in series with two capacitors 544a and 544b, respectively. Both series combinations of switch 542 and capacitor 544 are coupled between the summing node and circuit ground. Capacitors 534 and 544 in tap sections 530 and 540 may be reset at the start of filtering operation.

All capacitor(s) in each section of PSC filter 500 have the same capacitance, which is determined by the corresponding filter coefficient. The capacitances of the capacitors in the three sections of PSC filter 500 may be given as:C₀₀=K·c₀,  Eq (12a)C₁₀=K·c₁, and  Eq (12b)C₂₀=C₂₁=K·c₂.  Eq (12c)

As shown in equation set (12), the size of each capacitor C_ij is proportional to the magnitude of the corresponding filter coefficient c_i. A negative capacitor for a negative coefficient may be obtained by switching the polarity of the capacitor between the read phase and the charge sharing phase.

In each clock cycle, switch 512 is closed for a brief period of time to charge capacitor 524 in section 520 with the V_in signal. The total input capacitance observed by the V_in signal is thus C_in=C₀₀, and no extra capacitors are needed for C_in.

In each clock cycle, an appropriate capacitor in each tap section is used to generate the V_out signal. For IIR tap L, the capacitor charged L clock cycles earlier and storing y(n−L) is selected for use via its associated switch. Two selected capacitors in tap sections 530 and 540 as well as input capacitor 524 are used in a charge sharing operation that implements the multiplications with filter coefficients c₀ through c₂ and the summing of the multiplier outputs in equation (10). The charge sharing for the IIR filter may be expressed as:

$\begin{array}{cc}{V}_{\mathrm{out}}=\frac{C_{00}·V_{00}+C_{10}·V_{10}+C_{2k}·V_{2k}}{C_{00}+C_{10}+C_{2k}},& \mathrm{Eq}\left(13\right)\end{array}$ where k ε {0, 1} is an index of the capacitor storing y(n−2) in tap section 540.

After completing the charge sharing, the voltage across capacitors C₀₀, C₁₀ and C_2k corresponds to y(n). Capacitors C₁₀ and C_2k may store y(n) for use in subsequent clock cycles. Capacitor C₀₀ may provide y(n) for the V_out signal. The total output capacitance observed by the V_out signal is C_out=C₀₀, and no extra capacitors are needed for C_out.

Index k can cycle between 0 and 1, so that each capacitor 544 in tap section 540 is used for charge sharing in alternating clock cycle. PSC filter 500 may be considered as having two states for the two possible values of k.

FIG. 6 shows a timing diagram of various control signals for PSC filter 500 in FIG. 5. The clock signal CLK is shown at the top of the timing diagram. Control signals for the switches within PSC filter 500 are shown below the clock signal.

In the design shown in FIG. 6, each clock cycle includes a read phase, a charge sharing phase, a write phase, and a reset phase. For the read phase from time T₀ to time T₁, the S_in control signal is asserted, switch 512 is closed, and input capacitor C₀₀ is charged with the V_in signal. For the charge sharing phase from time T₂ to time T₃, the S_ij control signal for each capacitor selected for charge sharing is asserted, and the selected capacitors as well as input capacitor C₀₀ perform charge sharing via the summing node. At the end of the charge sharing phase, the S_ij control signal for each selected capacitor is de-asserted at time T₃, which then causes that capacitor to store y(n). For the write phase from time T₄ to time T₅, the S_out control signal is asserted, switch 516 is closed, and capacitor C₀₀ provides y(n) to the V_out signal. For the reset phase from time T₆ to time T₇, the S_reset control signal is asserted, switch 514 is closed, and capacitor C₀₀ is reset.

The coefficients for the second-order IIR filter may be defined to meet the following power constraint for IIR filter:|c₀|+|c₁|+|c₂|=1.  Eq (14)If coefficients c₀, c₁ and c₂ do not meet the power constraint in equation (14), then several schemes may be used meet the power constraint.

In a first scheme for meeting the power constraint for IIR filter, if |c₁|+|c₂|<1, then a scaled coefficient c₀′ may be computed as follows:c₀′=1−|c₁|−|c₂|.  Eq (15)

The coefficients c₀′, c₁ and c₂ meet the power constraint for IIR filter, as follows:|c₀′|+|c₁|+|c₂|=1.  Eq (16)

The IIR filter may be implemented with coefficients c₀′, c₁ and c₂ and may generate output sample y′(n), which may be expressed as:y′(n)=c₀′·x(n)−c₁·y(n−1)−c₂·y(n−2).  Eq (17)

The transfer function with coefficients c₀′, c₁ and c₂ may be expressed as:

$\begin{array}{cc}{H}_{\mathrm{IIR}}^{\prime }\left(z\right)=\frac{c_0^{\prime }}{c_0}·H_{\mathrm{IIR}}\left(z\right)=\frac{1-c_1-c_2}{c_0}·H_{\mathrm{IIR}}\left(z\right).& \mathrm{Eq}\left(18\right)\end{array}$

FIG. 7 shows a process 700 for designing a PSC filter with coefficient scaling to meet the power constraint. Multiple coefficients for a filter transfer function may be obtained (block 712). At least one of the multiple coefficients may be scaled based on a power constraint for the PSC filter (block 714). The PSC filter may then be implemented based on the at least one scaled coefficient to obtain the filter transfer function (block 716).

In one design, the filter transfer function may be for a FIR filter, e.g., a second-order FIR filter having the power constraint shown in equation (3). In this design, a scaling factor K_FIR may be determined based on the magnitude of each of the multiple coefficients, e.g., as shown in equation (4d). Each of the multiple coefficients may then be scaled based on the scaling factor to obtain a corresponding scaled coefficient, e.g., as shown in equations (4a) through (4c).

In another design, the filter transfer function may be for an IIR filter, e.g., a second-order IIR filter having the power constraint shown in equation (14). In this design, one of the multiple coefficients may be replaced with a new coefficient determined based on magnitude of each remaining coefficient, e.g., as shown in equation (15).

In a second scheme for meeting the power constraint for IIR filter, if |c₁|+|c₂|≧1, then the second-order IIR filter may be decomposed into two first-order IIR sections. Lower-order IIR sections often (but not always) result in smaller coefficients, which may allow the power constraint to be met.

The decomposition of a second-order FIR section may be expressed as:

$\begin{array}{cc}\begin{array}{c}1+c_1·z^{-1}+c_2·z^{-2}=\left(1-p·z^{-1}\right)·\left(1-p^{*}·z^{-1}\right)\\ =\left(1-\left(p_{\mathrm{re}}+j{p}_{\mathrm{im}}\right)·z^{-1}\right)·\\ \left(1-\left(p_{\mathrm{re}}-j{p}_{\mathrm{im}}\right)·z^{-1}\right)\end{array}& \mathrm{Eq}\left(19\right)\end{array}$ where p=p_re+j p_im is a complex coefficient, c₁=−2p_re, c₂=p_re²+p_im², and “*” denotes a complex conjugate.

As shown in equation (19), the decomposition of a second-order FIR section typically produces two complex first-order FIR sections with conjugated coefficients p and p*.

The complex coefficient may be tested for the following power constraint condition:|p_re|+|p_im|<1.  Eq (20)

If the condition in equation (20) is satisfied, then the second-order IIR filter in equation (10) may be implemented with two concatenated complex first-order IIR sections, both of which meet the power constraint. A complex output sample y′(n) from the first complex first-order IIR section may be expressed as:y_re′(n)={tilde over (c)}₀·x_re(n)+p_re·y_re′(n−1)−p_im·y_im′(n−1), and  Eq (21a)y_im′(n)={tilde over (c)}₀·x_im(n)+p_re·y_im′(n−1)+p_im·y_re′(n−1),  Eq (21b)where x(n)=x_re(n)+j x_im(n) is a complex input sample,

y′(n)=y_re′(n)+j y_im′(n) is a complex output sample from the first section, and

{tilde over (c)}₀ is a scaled coefficient that may be given as:{tilde over (c)}₀=1−|p_re|−|p_im|.  Eq (22)

A complex output sample y″(n) from the second complex first-order IIR section may be expressed as:y_re″(n)={tilde over (c)}₀·y_re′(n)+p_re·y_re″(n−1)+p_im·y_im″(n−1), and  Eq (23a)y_im″(n)={tilde over (c)}₀·y_im′(n)+p_re·y_im″(n−1)−p_im·y_re″(n−1),  Eq (23b)where y″(n)=y_re″(n)+j y_im″(n) is a complex output sample from the second section.

As shown in equation sets (21) and (23), the first and second complex first-order IIR sections have the same coefficients. The only difference in the two complex first-order IIR sections is the sign of the samples scaled by p_im.

As an example, a second-order IIR filter may have coefficients c₀=1, c₁=−0.25 and c₂=0.75. Since |c₁|+|c₂|=1, the first scheme for scaling coefficients does not apply. Using the second scheme, second-order IIR filter may be decomposed into two complex first-order IIR sections with p_re=0.125, p_im=0.857, and {tilde over (c)}₀=0.018. Since |p_re|+|p_im|<1, the two complex first-order IIR sections meet the power constraint.

FIG. 8 shows filtering of complex input samples with complex second-order IIR filters 810 and 830. For IIR filter 810, real input samples x_re(n) may be filtered with a real second-order IIR filter 820a, e.g., as shown in equation (10), to obtain real output samples y_re(n). Imaginary input samples x_im(n) may be filtered with a real second-order IIR filter 820b to obtain imaginary output samples y_im(n). IIR filters 820a and 820b independently filter the real and imaginary parts of the complex input samples. IIR filters 820a and 820b are identical and have the same coefficients. However, IIR filters 820a and 820b may not meet the power constraint and thus may not be directly implementable.

For IIR filter 830, the complex input samples x_re(n) and x_im(n) may be filtered with a complex first-order IIR section 840a, e.g., as shown in equation set (21), to obtain complex filtered samples y_re′(n) and y_im′(n). The complex filtered samples may be further filtered with a complex first-order IIR section 840b, e.g., as shown in equation set (23), to obtain complex output samples y_re″(n) and y_im″(n).

IIR filter 810 composed of two real second-order IIR filters 820a and 820b for the real and imaginary parts is equivalent to IIR filter 830 composed of two complex first-order IIR sections 840a and 840b. The complex output samples y_re″(n) and y_im″(n) from IIR filter 830 are equivalent to the complex output samples y_re(n) and y_im(n) from IIR filter 810. However, complex first-order IIR sections 840a and 840b may be implementable whereas real second-order IIR filters 820a and 820b may not be implementable.

FIG. 9 shows a block diagram of complex first-order IIR section 840a, which includes an IIR section 910a for the real part and an IIR section 910b for the imaginary part. Within IIR section 910a, a multiplier 920a receives and scales a real input sample x_re(n) with filter coefficient {tilde over (c)}₀. A summer 930a sums the output of multiplier 920a with the output of a summer 932a and provides a real output sample y_re′(n). A delay element 912a receives the real output sample y_re′(n) and provides a real delayed sample y_re′(n−1). A multiplier 922a for IIR tap A is coupled to the output of delay element 912a. A multiplier 924a for IIR tap B is also coupled to the output of delay element 912a. Multipliers 922a and 924a multiply the real delayed sample y_re′(n−1) with filter coefficients p_re and p_im, respectively, for IIR taps A and B. Summer 932a subtracts the output of a multiplier 924b in IIR section 910b from the output of multiplier 922a in IIR section 910a and provides its output to summer 930a.

IIR section 910b includes all of the elements in IIR section 910a. The elements in IIR section 910b are coupled in the same way as the elements in IIR section 910a with the following differences. A multiplier 922b for IIR tap C and a multiplier 924b for IIR tap D multiply the imaginary delayed sample y_im′(n−1) from a delay element 912b with filter coefficients p_re and p_im, respectively. A summer 932b sums the output of multiplier 924a in IIR section 910a with the output of multiplier 922b in IIR section 910b and provides its output to a summer 930b.

Complex first-order IIR section 840b in FIG. 8 may be implemented in similar manner as complex first-order IIR section 840a in FIG. 8, with the difference being a swamp in the signs of the outputs of multipliers 924a and 924b.

FIG. 10 shows a schematic diagram of a design of a PSC filter 1000 that implements complex first-order IIR section 840a in FIGS. 8 and 9. PSC filter 1000 includes a path 1010a for the real part and a path 1010b for the imaginary part. Path 1010a includes an input section 1020a and a tap section 1030a for IIR tap A of IIR section 840a in FIG. 9. Path 1010b includes an input section 1020b and a tap section 1030b for IIR tap C in FIG. 9. Both paths 1010a and 1010b share a tap section 1040 for IIR taps B and D in FIG. 9.

Within path 1010a, an input switch 1012a has one end receiving a real input signal V_in,re and the other end coupled to a summing node A. A reset switch 1014a is coupled between summing node A and circuit ground. An output switch 1016a has one end coupled to summing node A and the other end providing a real output signal V_out,re. Switches 1012b, 1014b and 1016b in path 1010b are coupled in similar manner as switches 1012a, 1014a and 1016a, respectively, in path 1010a.

Input section 1020a includes a capacitor 1024a coupled between summing node A and circuit ground. Tap section 1030a includes a switch 1032a coupled in series with a capacitor 1034a, the combination of which is coupled between summing node A and circuit ground. Input section 1020b and tap section 1030b are coupled in similar manner between summing node B and circuit ground. Tap section 1040 includes two switches 1042a and 1052a having one end coupled to summing node A and the other end coupled to capacitors 1044 and 1054, respectively. Tap section 1040 further includes two switches 1042b and 1052b having one end coupled to summing node B and the other end coupled to capacitors 1044 and 1054, respectively. The other ends of capacitors 1044 and 1054 are coupled to circuit ground.

The capacitances of the capacitors in PSC filter 1000 may be given as:C₀₀=C₀₁=K·{tilde over (c)}₀,  Eq (24a)C₁₀=C₁₁=K·p_re, and  Eq (24b)C₂₀=C₂₁=K·p_im.  Eq (24c)

For the example above with p_re=0.125, p_im=0.857, and {tilde over (c)}₀=0.018, the capacitance ratios may be given as follows:

$\begin{array}{c}{C}_{00}\text{:}{C}_{10};C_{10}\text{:}{C}_{11};C_{20}\text{:}{C}_{21}={\tilde{c}}_0\text{:}{\tilde{c}}_0;p_{\mathrm{re}}\text{:}{p}_{\mathrm{re}};p_{\mathrm{im}}\text{:}{p}_{\mathrm{im}}\\ =0.018\text{:}0\mathrm{.018};0.125\text{:}0\mathrm{.125};\\ 0.857\text{:}0\mathrm{.857}\end{array}$

In each clock cycle, switches 1012a and 1012b are closed for a brief period of time to charge capacitor 1024a in section 1020a with the V_in,re signal and to charge capacitor 1024b in section 1020b with the V_in,im signal. In each clock cycle, capacitor 1024a in section 1020a, capacitor 1034a in section 1030b, and either capacitor 1044 or 1054 in section 1040 are used in a charge sharing operation that implements the multiplications with filter coefficients {tilde over (c)}₀, p_re and p_im and the summing of the multiplier outputs in equation (21a). In each clock cycle, capacitor 1024b in section 1020b, capacitor 1034b in section 1030b, and either capacitor 1054 or 1044 in section 1040 are used in a charge sharing operation that implements equation (21b). The charge sharing for the real and imaginary parts may be expressed as:

$\begin{array}{cc}{V}_{\mathrm{out},\mathrm{re}}=\frac{C_{00}·V_{00}+C_{10}·V_{10}+C_{2k}·V_{2k}}{C_{00}+C_{10}+C_{2k}},\mathrm{and}& \mathrm{Eq}\left(25a\right)\\ V_{\mathrm{out},\mathrm{im}}=\frac{C_{01}·V_{01}+C_{11}·V_{11}+C_{2\stackrel{\_}{k}}·V_{2\stackrel{\_}{k}}}{C_{01}+C_{11}+C_{2\stackrel{\_}{k}}},& \mathrm{Eq}\left(25b\right)\end{array}$ where k ε {0, 1} is an index of the capacitor storing y_im′(n−1) in tap section 1040, and

k is an index of the capacitor storing y_re′(n−1) in tap section 1040.

After completing the charge sharing, the voltage on summing node A corresponds to y_re′(n), and the voltage on summing node B corresponds to y_im′(n). Capacitor 1024a may provide y_re′(n) for the V_out,re signal, and capacitor 1024b may provide y_im′(n) for the V_out,im signal. Capacitors 1034a may store y_re′(n) and capacitor 1034b may store y_im′(n) for use in the next clock cycle. Capacitors 1044 and 1054 are used in an interleaved manner to store y_re′(n) and y_im′(n) in each clock cycle. In each even-numbered clock cycle, capacitor 1044 may be coupled to summing node A, perform charge sharing, and store the y_re′(n), while capacitor 1054 may be coupled to summing node B, perform charge sharing, and store the y_im′(n). In each odd-numbered clock cycle, capacitor 1044 may be coupled to summing node B, perform charge sharing, and store the y_im′(n), while capacitor 1054 may be coupled to summing node A, perform charge sharing, and store the y_re′(n). Capacitor 1044 may thus be coupled to summing nodes A and B in alternating clock cycles, and capacitor 1054 may be coupled to summing nodes B and A in alternating clock cycles. Capacitors 1044 and 1054 have the same size but are interleaved in time.

FIG. 6 shows a timing diagram that may be used for the various control signals for PSC filter 1000 in FIG. 10. For the read phase from time T₀ to time T₁, the S_in control signal is asserted, switches 1012a and 1012b are closed, capacitor C₀₀ is charged with the V_in,re signal, and capacitor C₀₁ is charged with the V_in,im signal. For the charge sharing phase from time T₂ to time T₃, the S₁₀ control signal and either the S₂₀ or S₂₂ control signal are asserted, and capacitor C₀₀, capacitor C₁₀ and either capacitor C₂₀ or C₂₂ perform charge sharing via summing node A. Simultaneously, the S₁₁ control signal and either the S₂₁ or S₂₃ control signal are asserted, and capacitor C₀₁, capacitor C₁₁ and either capacitor C₂₀ or C₂₂ perform charge sharing via summing node B. At the end of the charge sharing phase, the S_ij control signal for each selected capacitor is de-asserted at time T₃, which then causes that capacitor to store y_re′(n) or y_im′(n). For the write phase from time T₄ to time T₅, the S_out control signal is asserted, switches 1016a and 1016b are closed, capacitor C₀₀ provides y_re′(n) to the V_out,re signal, and capacitor C₀₁ provides y_im′(n) to the V_out,im signal. For the reset phase from time T₆ to time T₇, the S_reset control signal is asserted, switches 1014a and 1014b are closed, and capacitors C₀₀ and C₀₁ are reset.

FIG. 11 shows a timing diagram of a switching pattern for PSC filter 1000 in FIG. 10. The switching pattern includes two cycles 0 and 1 for the two possible values of k in equation set (25) and repeats every two clock cycles. Table 1 shows the two cycles 0 and 1 and, for each cycle, gives the capacitors used to generate the V_out,re and V_out,im signals.

TABLE 1
	Capacitors	Capacitors
Cycle k	used to generate Vout,re	used to generate Vout,im
0	C00, C10 and C20	C01, C11 and C21
1	C00, C10 and C21	C01, C11 and C20

For cycle 0, input capacitor C₀₀ is charged with the V_in,re signal and capacitor C₀₁ is charged with the V_in,im signal when the S_in control signal is asserted during the read phase. The S₁₀, S₁₁, S₂₀ and S₂₃ control signals are asserted during the charge sharing phase, capacitors C₀₀, C₁₀ and C₂₀ are used to generate the V_out,re signal, and capacitors C₀₁, C₁₁ and C₂₁ are used to generate the V_out,im signal. Capacitors C₁₀ and C₂₀ store the V_out,re signal and capacitors C₁₁ and C₂₁ store the V_out,im signal at the end of the charge sharing phase.

For cycle 1, input capacitor C₀₀ is charged with the V_in,re signal and capacitor C₀₁ is charged with the V_in,im signal during the read phase. The S₁₀, S₁₁, S₂₁ and S₂₂ control signals are asserted during the charge sharing phase, capacitors C₀₀, C₁₀ and C₂₁ are used to generate the V_out,re signal, and capacitors C₀₁, C₁₁ and C₂₀ are used to generate the V_out,im signal. Capacitors C₁₀ and C₂₁ store the V_out,re signal and capacitors C₁₁ and C₂₀ store the V_out,im signal at the end of the charge sharing phase.

For PSC filter 1000, capacitors C₀₀ and C₀₁ are charged with the V_in,re and V_in,im signals in each clock cycle and are also used for charge sharing in the same clock cycle. Capacitors C₁₀ and C₁₁ are used for charge sharing in each clock cycle and store y_re′(n) and y_im′(n) for use in the next clock cycle. For tap section 1040, index k toggles between 0 and 1, capacitors C₂₀ and C₂₁ are used for charge sharing at nodes A and B in one clock cycle, at nodes B and A in the following clock cycle, etc.

Table 2 summarizes the action performed by each capacitor in PSC filter 1000 in each clock cycle.

	TABLE 2
	Clock Cycle
	n	n + 1	n + 2	. . .
Capacitor C00	store xre(n)	store xre(n + 1)	store xre(n + 2)	. . .
	xre(n)→ yre(n)	xre(n + 1)→ yre(n + 1)	xre(n + 2)→ yre(n + 2)
Capacitor C01	store xim(n)	store xim(n + 1)	store xim(n + 2)	. . .
	xim(n)→ yim(n)	xim(n + 1)→ yim(n + 1)	xim(n + 2)→ yim(n + 2)
Capacitor C10	yre(n − 1)→ yre(n)	yre(n)→ yre(n + 1)	yre(n + 1)→ yre(n + 2)	. . .
	store yre(n)	store yre(n + 1)	store yre(n + 2)
Capacitor C11	yim(n − 1)→ yim(n)	yim(n)→ yim(n + 1)	yim(n + 1)→ yim(n + 2)	. . .
	store yim(n)	store yim(n + 1)	store yim(n + 2)
Capacitor C20	yim(n − 1)→ yre(n)	yre(n)→ yim(n + 1)	yim(n + 1)→ yre(n + 2)	. . .
	store yre(n)	store yim(n + 1)	store yre(n + 2)
Capacitor C21	yre(n − 1)→ yim(n)	yim(n)→ yre(n + 1)	yre(n + 1)→ yim(n + 2)	. . .
	store yim(n)	store yre(n + 1)	store yim(n + 2)

FIG. 12 shows a schematic diagram of a design of a PSC filter 1200 that implements complex first-order IIR sections 840a and 840b in FIG. 8. PSC filter 1200 includes a first PSC filter section 1210a that implements complex first-order IIR section 840a and a second PSC filter section 1210b that implements complex first-order IIR section 840b. Each PSC filter section 1210 includes all elements in PSC filter 1000 in FIG. 10. The capacitors in tap section 1040 within PSC filter section 1210a are selected in different order than the capacitors in tap section 1040 within PSC filter section 1210b due to the difference between equation sets (21) and (23).

FIG. 13 shows a process 1300 for designing a PSC filter with decomposition. A filter transfer function may be decomposed into multiple complex first-order filter sections, e.g., as shown in equation (19) (block 1312). In one design of block 1312, the filter transfer function is for a second-order IIR filter and may be decomposed into two complex first-order IIR sections. Complex coefficients (e.g., p and p*) for the two complex first-order IIR sections may be determined based on coefficients (e.g., c₁ and c₂) for the second-order IIR filter. An input coefficient (e.g., {tilde over (c)}₀) for the two complex first-order IIR sections may be determined based on the magnitude of the real and imaginary parts (e.g., p_re and p_im) of the complex coefficients, e.g., as shown in equation (22). The multiple complex first-order filter sections may be implemented with multiple PSC filter sections to obtain the filter transfer function (block 1314).

The two complex first-order IIR sections obtained by decomposing a second-order IIR filter may not meet the power constraint. The complex pole obtained from the decomposition may be expressed as:p=p_re+j p_in=r·e^jθ,  Eq (26)where r is the magnitude of the pole and θ is the phase of the pole.

The sum of the magnitude of the real and imaginary parts of the pole may be expressed as:|p_re|+|p_im|=r·(|cos θ|+|sin θ|).  Eq (27)

A necessary and sufficient condition for stability of an IIR filter is r<1. The power constraint may be met with |p_re|+|p_im|<1. The term (|cos θ|+|sin θ|) may be greater than one depending on the value of θ. Thus, it is possible to have |p_re|+|p_im|≧1 even with r<1, in which case the IIR filter is stable but not directly implementable.

In a third scheme for meeting the power constraint for IIR filter, which may be used when the complex first-order IIR sections do not meet the power constraint, a complex first-order IIR section may be implemented with an interleaved filter bank. From equation set (21), the complex filtered samples from complex first-order IIR section 840a may be expressed as:

$\begin{array}{cc}\begin{array}{c}{y}^{\prime }\left(n\right)={\tilde{c}}_0·x\left(n\right)+p·y^{\prime }\left(n-1\right)\\ ={\tilde{c}}_0·x\left(n\right)+p·{\tilde{c}}_0·x\left(n-1\right)+p^2·y^{\prime }\left(n-2\right).\end{array}& \mathrm{Eq}\left(28\right)\end{array}$

Two consecutive filtered samples from complex first-order IIR section 840a may be expressed as:y′(n)={tilde over (c)}₀·x(n)+p·{tilde over (c)}₀·x(n−1)+p²·y′(n−2), and  Eq (29a)y′(n+1)={tilde over (c)}₀·x(n+1)+p·{tilde over (c)}₀·x(n)+p²·y′(n−1).  Eq (29b)

Equation set (29) may be partitioned into an IIR part and a FIR part. The IIR part may also be referred to as a recursive part or an autoregressive part. The FIR part may also be referred to as a non-recursive part. The IIR part may be expressed as:y′(n)={hacek over (c)}₀·{hacek over (x)}(n)+p²·y′(n−2), and  Eq (30a)y′(n+1)={hacek over (c)}₀·{hacek over (x)}(n+1)+p²·y′(n−1),  Eq (30b)where {hacek over (c)}₀=1−|real(p²)|−|imag(p²)| and {hacek over (x)}(n) is the output of the FIR part.

The FIR part may be expressed as:{hacek over (x)}(n)={hacek over (c)}₀⁻¹·{tilde over (c)}₀·x(n)+{hacek over (c)}₀⁻¹·{tilde over (c)}₀·p·x(n−1), and  Eq (31a){hacek over (x)}(n+1)={hacek over (c)}₀⁻¹·{tilde over (c)}₀·x(n+1)+{hacek over (c)}₀⁻¹·{tilde over (c)}₀·p·x(n).  Eq (31b)

FIG. 14 shows a block diagram of a complex first-order IIR section 1400 implemented with a FIR filter bank 1410 and an IIR filter bank 1420. FIR filter bank 1410 may filter the complex input samples x_re(n) and x_im(n) as shown in equation set (31) and provide complex filtered samples {hacek over (x)}_re(n) and {hacek over (x)}_im(n). IIR filter bank 1420 may filter the complex filtered samples {hacek over (x)}_re(n) and {hacek over (x)}_im(n) as shown in equation set (30) and provide complex output samples y_re′(n) and y_im′(n). FIG. 14 shows a design with IIR filter bank 1420 being placed after FIR filter bank 1410. In another design, FIR filter bank 1410 may be placed after IIR filter bank 1420. The order of FIR filter bank 1410 and IIR filter bank 1420 may be selected based on noise and other considerations.

FIG. 15 shows a schematic diagram of a design of a PSC filter 1500 that implements IIR filter bank 1420 in FIG. 14. PSC filter 1500 includes a first IIR section 1510a and a second IIR section 1510b. Each IIR section 1510 includes all elements of PSC filter 1000 in FIG. 10.

A real input signal V_in,re is provided to both a switch 1512a in IIR section 1510a and a switch 1512c in IIR section 1510b. An imaginary input signal V_in,im is provided to both a switch 1512b in IIR section 1510a and a switch 1512d in IIR section 1510b. A switch 1516a in IIR section 1510a and a switch 1516c in IIR section 1510b are coupled together and provide a real output signal V_out,re. A switch 1516b in IIR section 1510a and a switch 1516d in IIR section 1510b are coupled together and provide an imaginary output signal V_out,im. The other elements within IIR sections 1510a and 1510b are coupled as described above for FIG. 10.

IIR section 1510a operates in each even-numbered clock cycle, filters the V_in,re and V_in,im signals, and provides the V_out,re and V_out,im signals. IIR section 1510a is disabled during each odd-numbered clock cycle. Conversely, IIR section 1510b operates in each odd-numbered clock cycle, filters the V_in,re and V_in,im signals, and provides the V_out,re and V_out,im signals. IIR section 1510b is disabled during each even-numbered clock cycle. IIR sections 1510a and 1510b thus operate in an interleaved manner, with IIR section 1510a operating in one clock cycle, then IIR section 1510b operating in the next clock cycle, then IIR section 1510a operating in the following clock cycle, etc. IIR section 1510a operates on {hacek over (x)}(n) and provides y′(n), as shown in equation (30a). IIR section 1510b operates on {hacek over (x)}(n+1) and provides y′(n+1), as shown in equation (30b).

In one design, a PSC filter for FIR filter bank 1410 in FIG. 14 (which may be a FIR filter) may be implemented in similar manner as PSC filter 1000 in FIG. 10. However, the switches for the PSC filter for FIR filter bank 1410 are operated to implement a FIR filter instead of an IIR filter. In another design, two FIR filter banks may be merged from two first-order complex IIR filters. The merged second-order FIR filter has real coefficients and may be implemented as a normal second-order PSC FIR filter.

Equation sets (30) and (31) show filter bank transformation for a case in which IIR filter bank 1420 includes two IIR sections. In general, the filter bank transformation may be performed for any value of m or M=2^m to obtain a complex pole at p^2m=p^M. The IIR part may be expressed as:y′(n+i)={hacek over (c)}₀·{hacek over (x)}(n+i)+p^M·y′(n−M+i), for i=0, . . . , M−1,  Eq (32)where {hacek over (c)}₀=1−|real(p^M)|−|imag(p^M)|.  Eq (33)

A filter bank may thus include M IIR sections. Each IIR section may be implemented as shown in FIG. 15, may operate at 1/M of the clock rate, and may be enabled every M clock cycles. The M IIR sections may be sequentially enabled in M clock cycles, one IIR section in each clock cycle.

FIG. 16 shows a plot 1610 of pole movement due to filter bank transformation with different values of M. An IIR filter is stable if its pole has a magnitude of r<1 and is located within a unit circle 1612. The pole of the IIR filter meets the power constraint in equation (20) if it is located within a diamond box 1614. The filter bank transformation changes the pole from p to p^M. Plot 1610 shows the pole location for an example IIR filter with c₀=1, c₁=−1.5 and c₂=0.6875. In this example, the pole p obtained from decomposition is located outside diamond box 1614 and thus does not meet the power constraint. The filter bank transformation with M=2 results in the pole p² being located within diamond box 1614 and thus meets the power constraint. The filter bank transformation with M=4 and 8 results in the poles p⁴ and p⁸ being located closer to the origin. As shown by this example, the pole generally moves toward the origin for larger values of M. In general, a larger distance from the pole to the unit circle may result in smaller insertion loss, which is desirable.

The pole due to filter bank transformation with M=2 may be expressed as:p²=r²·e^j20≡{hacek over (p)}={hacek over (p)}_re+j {hacek over (p)}_im.  Eq (34)

The power constraint for the IIR part may then be expressed as:|{hacek over (p)}_re|+|{hacek over (p)}_im|=r²·(|cos 2θ|+|sin 2θ|)≦1.  Eq (35)

Since r<1 for a stable IIR filter, r²<r and it may be more possible to meet the power constraint. As an example, a complex first-order IIR section with pole of p=0.625+j 0.625 does not meet the power constraint. However, a filter bank with pole of p²=j 0.78 meets the power constraint.

Equation (35) is for a 2-way interleaved filter bank with M=2. In general, the power constraint for an M-way interleaved filter bank may be expressed as:|{hacek over (p)}_re|+|{hacek over (p)}_im|=r^M·(|cos M·θ|+|sin M·θ|)≦1.  Eq (36)

In theory, the power constraint can always be satisfied if M is sufficiently large. However, a larger M also corresponds to greater complexity for the IIR part.

FIG. 17 shows a process 1700 for designing a PSC filter with filter bank transformation. A filter transfer function may be decomposed into a FIR part and an IIR part (block 1712). In one design, the filter transfer function is for a complex first-order IIR filter and may be decomposed into the FIR part and the IIR part. A complex coefficient (e.g., p^M) for the IIR part may be determined based on a complex coefficient (e.g., p) for the complex first-order IIR filter. The IIR part may be partitioned into multiple (M) IIR sections, with each IIR section operating at 1/M clock rate, and the M IIR sections being sequentially enabled in M clock cycles (block 1714). In one design, the IIR part may be partitioned into first and second IIR sections, with the first IIR section being enabled in even-numbered clock cycles, and the second IIR section being enabled in odd-numbered clock cycles. The FIR and IIR parts may be implemented with PSC filter sections to obtain the filter transfer function (block 1716).

In a fourth scheme for meeting the power constraint for IIR filter, pole repositioning may be performed, and a pole may be moved to a more suitable location in order to meet the power constraint. The second part of the right hand side of equation (22) may be expressed as:ƒ(θ)=(|cos θ|+|sin θ|).  Eq (37)

FIG. 18 shows a plot 1810 of function ƒ(θ) in equation (37). Function ƒ(θ) has a minimum value of 1.0 for θ=i·π/2, where i is an integer. In order to meet the power constraint |p_re|+|p_im|<1, it is better to minimize f(θ), which means making either θ or M·θ close to i·π/2. It may be desirable to have θ≈π/2, so that the poles are on the imaginary axis. If the interleaved filter bank with M=2 is used, then it may be desirable to have θ≈π/4 or θ≈3π/4. This may be achieved by a multi-rate filter design.

For the fourth scheme, the pole location may be varied in a systematic or pseudo-random manner. The pole at each new location may be evaluated to determine whether (i) a desired filter response can be obtained with the new pole location and (ii) the power constraint is met with the new pole location.

FIG. 19 shows a process 1900 for designing a second-order IIR filter to meet power constraint. The second-order IIR filter may be designed to meet applicable system requirements. The coefficients c₀, c₁ and c₂ of the second-order IIR filter may be obtained (block 1912). A determination is made whether the coefficients can be scaled, e.g., whether |c₁|+|c₂|<1 (block 1914). If the answer is ‘Yes’ for block 1914, then coefficient scaling may be performed to obtain coefficient c₀′ as shown in equation (15) (block 1924). Otherwise, the second-order IIR filter may be decomposed into complex first-order IIR sections (block 1916). A determination is made whether the pole of the first-order IIR sections meet the power constraint, e.g., whether |p_re|+|p_im|<1 (block 1918). If the answer is ‘Yes’ for block 1918, then coefficient scaling may be performed to obtain coefficient {tilde over (c)}₀ as shown in equation (22) (block 1924).

Otherwise, each complex first-order IIR section may be implemented with a filter bank starting with m=1 (block 1920). A determination is made whether the pole for the filter bank meets the power constraint, e.g., whether |{hacek over (p)}_re|+|{hacek over (p)}_im|<1 (block 1922). If the answer is ‘Yes’ for block 1922, then coefficient scaling may be performed to obtain coefficient {hacek over (c)}₀ as shown in equation (33) (block 1924). Otherwise, a determination is made whether m is equal to a maximum value (block 1926). If the answer is ‘No’, then m may be incremented (block 1928), and the process may then return to block 1920. Otherwise, pole repositioning may be performed in order to meet the power constraint (block 1930).

For clarity, much of the description above is for second-order FIR filter and first-order and second-order IIR filters. The PSC filters described herein may be used for FIR filters and IIR filters of any order.

The PSC filters described herein may provide certain advantages. First, the PSC filters do not utilize amplifiers within the PSC filters, which may reduce size and power consumption. Amplifiers may be used for input/output buffering. Second, the PSC filters may be able to provide an accurate frequency response, which is determined by capacitor ratios that can be more accurately achieved in an integrated circuit (IC). Third, the PSC filters may have high adaptability since it uses an array of capacitors that may be configured during operation, e.g., to obtain different filter responses.

The PSC filters described herein may be used for various applications such as wireless communication, computing, networking, consumer electronics, etc. The PSC filters may also be used for various devices such as wireless communication devices, cellular phones, broadcast receivers, personal digital assistants (PDAs), handheld devices, wireless modems, laptop computers, cordless phones, Bluetooth devices, wireless local loop (WLL) stations, consumer electronics devices, etc. For clarity, the use of the PSC filters in a wireless communication device, which may be a cellular phone or some other device, is described below. The PSC filters may be used to pass a desired signal, to attenuate jammers and out-of-band noise and interference, and/or to perform other functions in the wireless device.

FIG. 20 shows a block diagram of a design of a wireless communication device 2000 in which the PSC filter described herein may be implemented. Wireless device 2000 includes a receiver 2020 and a transmitter 2040 that support bi-directional communication. In general, wireless device 2000 may include any number of receivers and any number of transmitters for any number of communication systems and frequency bands.

In the receive path, an antenna 2012 may receive radio frequency (RF) modulated signals transmitted by base stations and provide a received RF signal, which may be routed through an RF unit 2014 and provided to receiver 2020. RF unit 2014 may include an RF switch and/or a duplexer that can multiplex RF signals for the transmit and receive paths. Within receiver 2020, a low noise transconductance amplifier (LNTA) 2022 may amplify the received RF signal (which may be a voltage signal) and provide an amplified RF signal (which may be a current signal). A passive sampler 2024 may sample the amplified RF signal, perform frequency downconversion via a sampling operation, and provide analog samples. An analog sample is an analog value for a discrete time instant. A filter/decimator 2026 may filter the analog samples, perform decimation, and provide filtered samples at a lower sample rate. Filter/decimator 2026 may be implemented with the PSC filters described herein.

The filtered samples from filter/decimator 2026 may be amplified by a variable gain amplifier (VGA) 2028, filtered by a filter 2030, further amplified by an amplifier (AMP) 2032, further filtered by a filter 2034, and digitized by an analog-to-digital converter (ADC) 2036 to obtain digital samples. Filter 2030 and/or 2034 may be implemented with the PSC filters described herein. VGA 2028 and/or amplifier 2032 may be implemented with switched-capacitor amplifiers that can amplify the analog samples from filters 2026 and 2030. A digital processor 2050 may process the digital samples to obtain decoded data and signaling. A control signal generator 2038 may generate a sampling clock for passive sampler 2024 and control signals for filters 2026, 2030 and 2034.

In the transmit path, transmitter 2040 may process output samples from digital processor 2050 and provide an output RF signal, which may be routed through RF unit 2014 and transmitted via antenna 2012. For simplicity, details of transmitter 2040 are not shown in FIG. 20.

Digital processor 2050 may include various processing units for data transmission and reception as well as other functions. For example, digital processor 2050 may include a digital signal processor (DSP), a reduced instruction set computer (RISC) processor, a central processing unit (CPU), etc. A controller/processor 2060 may control the operation at wireless device 2000. A memory 2062 may store program codes and data for wireless device 2000. Data processor 2050, controller/processor 2060, and/or memory 2062 may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs.

FIG. 20 shows a specific design of receiver 2020. In general, the conditioning of the signals within receiver 2020 may be performed by one or more stages of mixer, amplifier, filter, etc. These circuit blocks may be arranged differently from the configuration shown in FIG. 20. Furthermore, other circuit blocks not shown in FIG. 20 may also be used to condition the signals in the receiver. Some circuit blocks in FIG. 20 may also be omitted. All or a portion of receiver 2020 may be implemented on one or more RF ICs (RFICs), mixed-signal ICs, etc.

The received RF signal from antenna 2012 may contain both a desired signal and jammers. A jammer is a large amplitude undesired signal close in frequency to a desired signal. The jammers may be attenuated prior to ADC 2036 in order to avoid saturation of the ADC. Filters 2026, 2030 and/or 2034 may attenuate the jammers and other out-of-band noise and interference and may each be implemented with any of the PSC filters described herein.

The PSC filters described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronics device, etc. The PSC filters may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

An apparatus implementing the PSC filters described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.

In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computers. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: a first filter section comprising:a first set of capacitors operative to receive a real input signal and an imaginary delayed signal, to store and share electrical charges, and to provide a real filtered signal, wherein the first set of capacitors comprises: a first capacitor operative to receive and store the real input signal, to share electrical charge, and to provide the real filtered signal in each clock cycle, anda second capacitor operative to share electrical charge and to store the real filtered signal in each clock cycle;a second set of capacitors operative to receive an imaginary input signal and a real delayed signal, to store and share electrical charges, and to provide an imaginary filtered signal; anda third set of capacitors operative to receive the real and imaginary filtered signals, to store and share electrical charges, and to provide the real and imaginary delayed signals.

2. The apparatus of claim 1, wherein the second set of capacitors comprises a third capacitor operative to receive and store the imaginary input signal, to share electrical charge, and to provide the imaginary filtered signal in each clock cycle, anda fourth capacitor operative to share electrical charge and to store the imaginary filtered signal in each clock cycle.

3. The apparatus of claim 2, wherein the third set of capacitors comprises a fifth capacitor operative to share electrical charge in each clock cycle, to store the real filtered signal in each even-numbered clock cycle, and to store the imaginary filtered signal in each odd-numbered clock cycle, anda sixth capacitor operative to share electrical charge in each clock cycle, to store the imaginary filtered signal in each even-numbered clock cycle, and to store the real filtered signal in each odd-numbered clock cycle.

4. The apparatus of claim 1, wherein each capacitor in the first, second and third sets is operative to store a value from an associated summing node when selected for charging and to share electrical charge with other capacitors via the associated summing node when selected for charge sharing.

5. The apparatus of claim 1, wherein the first filter section further comprises a first switch operative to couple a capacitor in the first set to a first summing node;a second switch operative to couple a capacitor in the second set to a second summing node;a first set of switches operative to couple the third set of capacitors to the first summing node; anda second set of switches operative to couple the third set of capacitors to the second summing node.

6. The apparatus of claim 5, wherein each switch is operative to couple an associated capacitor to an associated summing node when enabled and to decouple the associated capacitor from the associated summing node when disabled.

7. The apparatus of claim 5, wherein the first filter section further comprises a first input switch operative to couple the real input signal to the first summing node when the first input switch is enabled;a first output switch operative to couple the first summing node to the real filtered signal when the first output switch is enabled; anda first reset switch operative to couple the first summing node to circuit ground and to reset a capacitor coupled directly to the first summing code when the first reset switch is enabled.

8. The apparatus of claim 7, wherein the first filter section further comprises a second input switch operative to couple the imaginary input signal to the second summing node when the second input switch is enabled;a second output switch operative to couple the second summing node to the imaginary filtered signal when the second output switch is enabled; anda second reset switch operative to couple the second summing node to circuit ground and to reset a capacitor coupled directly to the second summing code when the second reset switch is enabled.

9. The apparatus of claim 1, further comprising: a second filter section coupled to the first filter section and comprisinga fourth set of capacitors operative to receive the real filtered signal and an imaginary delayed output signal, to store and share electrical charges, and to provide a real output signal;a fifth set of capacitors operative to receive the imaginary filtered signal and a real delayed output signal, to store and share electrical charges, and to provide an imaginary output signal; anda sixth set of capacitors operative to receive the real and imaginary output signals, to store and share electrical charges, and to provide the real and imaginary delayed output signals.

10. The apparatus of claim 9, wherein the first and second filter sections each implement a complex first-order infinite impulse response (IIR) section and collectively implement a complex second-order IIR filter.

11. The apparatus of claim 1, wherein the apparatus is an integrated circuit.

12. A wireless device comprising: at least one passive switched-capacitor (PSC) filter, each PSC filter comprising at least one filter section operative to receive and filter a complex input signal and provide a complex filtered signal for the PSC filter, wherein a filter section for each PSC filter comprises:a first set of capacitors operative to receive a real input signal and an imaginary delayed signal, to store and share electrical charges, and to provide a real filtered signal, wherein the first set of capacitors comprises: a first capacitor operative to receive and store the real input signal, to share electrical charge, and to provide the real filtered signal in each clock cycle, anda second capacitor operative to share electrical charge and to store the real filtered signal in each clock cycle,a second set of capacitors operative to receive an imaginary input signal and a real delayed signal, to store and share electrical charges, and to provide an imaginary filtered signal, anda third set of capacitors operative to receive the real and imaginary filtered signals, to store and share electrical charges, and to provide the real and imaginary delayed signals; anda signal generator operative to generate control signals for the at least one PSC filter.

13. The wireless device of claim 12, wherein each PSC filter is operative to receive analog input samples for the complex input signal and to provide analog output samples for the complex filtered signal, and wherein the wireless device further comprises an analog-to-digital converter (ADC) operative to digitize the complex filtered signal from a last PSC filter and provide digital samples.

14. The wireless device of claim 12, wherein each PSC filter comprises two complex first-order infinite impulse response (IIR) filter sections.

15. The wireless device of claim 12, wherein each PSC filter comprises a finite impulse response (FIR) filter section and an infinite impulse response (IIR) filter section.

16. A method comprising: receiving a real input signal and an imaginary delayed signal by a first set of capacitors in a first filter section, wherein the first set of capacitors is operative to store and share electrical charges, and to provide a real filtered signal, wherein the first set of capacitors comprises: a first capacitor operative to receive and store the real input signal, to share electrical charge, and to provide the real filtered signal in each clock cycle, anda second capacitor operative to share electrical charge and to store the real filtered signal in each clock cycle;receiving an imaginary input signal and a real delayed signal by a second set of capacitors, wherein the second set of capacitors is operative to store and share electrical charges, and to provide an imaginary filtered signal; andreceiving the real and imaginary filtered signals by a third set of capacitors, wherein the third set of capacitors is operative to store and share electrical charges, and to provide the real and imaginary delayed signals.

17. The method of claim 16, wherein the second set of capacitors comprises a third capacitor operative to receive and store the imaginary input signal, to share electrical charge, and to provide the imaginary filtered signal in each clock cycle, anda fourth capacitor operative to share electrical charge and to store the imaginary filtered signal in each clock cycle.

18. The method of claim 17, wherein the third set of capacitors comprises a fifth capacitor operative to share electrical charge in each clock cycle, to store the real filtered signal in each even-numbered clock cycle, and to store the imaginary filtered signal in each odd-numbered clock cycle, anda sixth capacitor operative to share electrical charge in each clock cycle, to store the imaginary filtered signal in each even-numbered clock cycle, and to store the real filtered signal in each odd-numbered clock cycle.

19. The method of claim 16, wherein each capacitor in the first, second and third sets is operative to store a value from an associated summing node when selected for charging and to share electrical charge with other capacitors via the associated summing node when selected for charge sharing.

20. The method of claim 16, wherein the first filter section further comprises a first switch operative to couple a capacitor in the first set to a first summing node;a second switch operative to couple a capacitor in the second set to a second summing node;a first set of switches operative to couple the third set of capacitors to the first summing node; anda second set of switches operative to couple the third set of capacitors to the second summing node.

21. The method of claim 20, wherein each switch is operative to couple an associated capacitor to an associated summing node when enabled and to decouple the associated capacitor from the associated summing node when disabled.

22. The method of claim 20, wherein the first filter section further comprises a first input switch operative to couple the real input signal to the first summing node when the first input switch is enabled;a first output switch operative to couple the first summing node to the real filtered signal when the first output switch is enabled; anda first reset switch operative to couple the first summing node to circuit ground and to reset a capacitor coupled directly to the first summing code when the first reset switch is enabled.

23. The method of claim 22, wherein the first filter section further comprises a second input switch operative to couple the imaginary input signal to the second summing node when the second input switch is enabled;a second output switch operative to couple the second summing node to the imaginary filtered signal when the second output switch is enabled; anda second reset switch operative to couple the second summing node to circuit ground and to reset a capacitor coupled directly to the second summing code when the second reset switch is enabled.

24. The method of claim 16, further comprising: receiving the real filtered signal and an imaginary delayed output signal by a fourth set of capacitors in a second filter section coupled to the first filter section, wherein the fourth set of capacitors is operative to store and share electrical charges, and to provide a real output signal;receiving the imaginary filtered signal and a real delayed output signal by a fifth set of capacitors, wherein the fifth set of capacitors is operative to store and share electrical charges, and to provide an imaginary output signal; andreceiving the real and imaginary output signals by a sixth set of capacitors, wherein the sixth set of capacitors is operative to store and share electrical charges, and to provide the real and imaginary delayed output signals.

25. The method of claim 24, wherein the first and second filter sections each implement a complex first-order infinite impulse response (IIR) section and collectively implement a complex second-order IIR filter.

26. An apparatus comprising: means for receiving a real input signal and an imaginary delayed signal, wherein the means for receiving a real input signal and an imaginary delayed signal is operative to store and share electrical charges, and to provide a real filtered signal, wherein the means for receiving a real input signal and an imaginary delayed signal comprises: a first capacitor operative to receive and store the real input signal, to share electrical charge, and to provide the real filtered signal in each clock cycle, anda second capacitor operative to share electrical charge and to store the real filtered signal in each clock cycle;means for receiving an imaginary input signal and a real delayed signal, wherein the means for receiving an imaginary input signal and a real delayed signal is operative to store and share electrical charges, and to provide an imaginary filtered signal; andmeans for receiving the real and imaginary filtered signals, wherein the means for receiving the real and imaginary filtered signals is operative to store and share electrical charges, and to provide the real and imaginary delayed signals.

27. The apparatus of claim 26, wherein the means for receiving an imaginary input signal and a real delayed signal comprises a third capacitor operative to receive and store the imaginary input signal, to share electrical charge, and to provide the imaginary filtered signal in each clock cycle, anda fourth capacitor operative to share electrical charge and to store the imaginary filtered signal in each clock cycle.

28. The apparatus of claim 27, wherein the means for receiving the real and imaginary filtered signals comprises a fifth capacitor operative to share electrical charge in each clock cycle, to store the real filtered signal in each even-numbered clock cycle, and to store the imaginary filtered signal in each odd-numbered clock cycle, anda sixth capacitor operative to share electrical charge in each clock cycle, to store the imaginary filtered signal in each even-numbered clock cycle, and to store the real filtered signal in each odd-numbered clock cycle.

29. The apparatus of claim 26, wherein each capacitor is operative to store a value from an associated summing node when selected for charging and to share electrical charge with other capacitors via the associated summing node when selected for charge sharing.

30. The apparatus of claim 26, further comprising: means for coupling a capacitor in the means for receiving a real input signal and an imaginary delayed signal to a first summing node;means for coupling a capacitor in the means for receiving an imaginary input signal and a real delayed signal to a second summing node;means for coupling the means for receiving the real and imaginary filtered signals to the first summing node; andmeans for coupling the means for receiving the real and imaginary filtered signals to the second summing node.