Patent Application
20100225419
I. Field
The present disclosure relates generally to electronics, and more specifically to filters.
II. Background
Filters are commonly used to filter signals to pass desired signal components and to attenuate undesired signal components. Filters are widely used for various applications such as communication, computing, networking, consumer electronics, etc. For example, in a wireless communication device such as a cellular phone, filters may be used to filter a received signal to pass a desired signal on a specific frequency channel and to attenuate out-of-band signals and noise. For many applications, filters that occupy small area and consume low power are highly desirable.
Passive switched-capacitor (PSC) filters that may occupy smaller area and consume less power are described herein. In one design, a PSC filter includes (i) a plurality of capacitors that can store and share electrical charge and (ii) a plurality of switches that can couple the plurality of capacitors to a summing node. Each switch couples an associated capacitor to the summing node when enabled and decouples the associated capacitor from the summing node when disabled. Each capacitor stores a voltage value from the summing node when selected for charging and shares electrical charge with other capacitors via the summing node when selected for charge sharing.
The PSC filter may further include an input switch, a reset switch, an output switch, and an input capacitor. The input switch couples an input signal to the summing node when enabled. The output switch couples the summing node to an output signal when enabled. The reset switch shorts the summing node to circuit ground and resets/discharges the capacitors coupled to the summing code when enabled. The input capacitor stores the input signal, shares electrical charge, and provides the output signal in each clock cycle.
In one design, a PSC filter implements a finite impulse response (FIR) filter and includes multiple sections for multiple FIR taps. Each section includes (i) multiple capacitors of equal size determined based on a filter coefficient for an associated FIR tap and (ii) multiple switches that can couple the multiple capacitors to the summing node. The section for FIR tap L, where L=1, 2, . . . , includes L+1 capacitors to store L+1 samples of the input signal for L+1 most recent clock cycles. The L+1 capacitors may be sequentially selected for charging with the input signal, one capacitor in each clock cycle. The capacitor selected for charging in a given clock cycle is selected for charge sharing L clock cycles later, and is then charged in the following clock cycle. In each clock cycle, the input capacitor and one capacitor in each section are charged with the input signal during a first/read phase, and another capacitor in each section is selected for charge sharing during a second phase. The selected capacitor in each section and the input capacitor provide a sample (e.g., a voltage value) for the output signal during a third/write phase, and these capacitors are reset during a fourth/reset phase.
In another design, a PSC filter implements an infinite impulse response (IIR) filter and includes multiple sections for multiple IIR taps. Each section includes (i) at least one capacitor of equal size determined based on a filter coefficient for an associated IIR tap and (ii) at least one switch that can couple the at least one capacitor to the summing node. The section for IIR tap L, where L=1, 2, . . . , includes L capacitors to store L samples of the output signal for L most recent clock cycles. The L capacitors may be sequentially selected for charging with the output signal, one capacitor in each clock cycle. The capacitor selected for charging in a given clock cycle is selected for charge sharing L clock cycles later. In each clock cycle, the input capacitor is charged with the input signal during the first phase, and one capacitor in each section is selected for charge sharing with the input capacitor during the second phase. After the charge sharing is complete, all capacitors involved in the charge sharing have the same sample or voltage value, and each selected capacitor stores its sample. The input capacitor provides its sample to the output signal during the third phase and is reset during the fourth phase.
In yet another design, a PSC filter implements an auto regressive moving average (ARMA) filter composed of a FIR section and an IIR section. The FIR section includes at least one first section for at least one FIR tap. The IIR section includes at least one second section for at least one IIR tap. A first section for FIR tap L includes L+1 capacitors of equal size and used to store L+1 samples of the input signal for L+1 most recent clock cycles. A second section for IIR tap L includes L capacitors of equal size and used to store L samples of the output signal for L most recent clock cycles. In each clock cycle, one capacitor in each first section and one capacitor in each second section are selected for charge sharing to generate a sample for the output signal.
Various aspects and features of the disclosure are described in further detail below.
The PSC filters described herein may be used for various types of filters such as FIR filters, IIR filters, ARMA filters, etc. The PSC filters may also implement filters of any order, e.g., first, second, third or higher order. Multiple PSC filter sections may be used to form more complex filters. For clarity, PSC filters for a second-order FIR filter and a second-order IIR filter are described in detail below.
The output sample y(n) from FIR filter 100 may be expressed as:
y(n)=b0·x(n)+b1·x(n−1)+b2·x(n−2). Eq (1)
A transfer function H(z) for FIR filter 100 in the z-domain may be expressed as:
H(z)=b0+b1·z+b2·z2, Eq (2)
where z−k denotes a delay of k clock cycles.
The filter coefficients may be defined to meet the following condition:
|b0|+|b1|+|b2|=1. Eq (3)
The condition in equation (3) ensures that a PSC filter for FIR filter 100 can meet a power constraint. Any set of FIR filter coefficients may be scaled to achieve the condition in equation (3).
Input section 220 includes an input capacitor 224 coupled between the summing node and circuit ground. Tap section 230 includes two switches 232a and 232b coupled in series with two capacitors 234a and 234b, respectively. Both series combinations of switch 232 and capacitor 234 are coupled between the summing node and circuit ground. Tap section 240 includes three switches 242a, 242b and 242c coupled in series with three capacitors 244a, 244b and 244c, respectively. All three series combinations of switch 242 and capacitor 244 are coupled between the summing node and circuit ground.
All capacitors in each section have the same capacitance/size, which is determined by the corresponding filter coefficient. The capacitances of the capacitors in the three sections of PSC filter 200 may be given as:
C
00
=K·b
0, Eq (4)
C
10
=C
11
=K·b
1, and Eq (5)
C
20
=C
21
=C
22
=K·b
2, Eq (6)
where Cij is the capacitance of the j-th capacitor in the section for FIR tap i, and
K is a scaling constant.
As shown in equations (4) through (6), the size of each capacitor Cij is proportional to the corresponding filter coefficient bi. K may be selected based on various factors such as switching settling time, capacitor size, power dissipation, noise, etc. K may be set to a sufficiently small value so that the settling time can be much larger (e.g. 7 times larger) than the RC constant in order to keep the residue error negligible. Also, capacitor size and power dissipation may be reduced with a small value of K. However, thermal noise and/or fabrication technology may limit the minimum value of K. A negative capacitor for a negative coefficient may be obtained by switching the polarity of the capacitor between a read phase and a charge sharing phase.
In general, the number of capacitors to use for each FIR tap is determined by the delay for that FIR tap. L+1 capacitors of the same size may be used for FIR tap L, where L=1, 2, . . . . Indices L and i are used interchangeably herein. In each clock cycle, one capacitor may be charged with the input signal to store x(n), and another capacitor that was charged L clock cycles earlier and storing x(n−L) may be used to generate y(n) for the output signal. The L+1 capacitors may be charged in a sequential/circular order, one capacitor in each clock cycle, and may store samples x(n) through x(n−L) in any given clock cycle n.
In each clock cycle, switch 212 is closed for a brief period of time to charge one capacitor in each section with the Vin signal. The capacitor selected for charging in each tap section is determined by switches 232 and 242, as described below. The total input capacitance observed by the Vin signal for the charge operation may be expressed as:
C
in
=C
00
+C
1u
+C
2v, Eq (7)
where u ∈ {0, 1} is an index of the capacitor selected for charging in tap section 230, and
v ∈ {0, 1, 2} is an index of the capacitor selected for charging in tap section 240.
Since the capacitors in each tap section have the same capacitance, the total input capacitance Cin is constant for each clock cycle. The constant Cin may be desirable for a constant signal insertion loss, which may occur when the signal is provided from a capacitive source to Cin. Furthermore, no extra capacitors are needed for Cin, which utilizes the capacitors selected for charging in the three sections.
In each clock cycle, an appropriate capacitor in each tap section is used to generate the Vout signal. For FIR tap L, the capacitor charged L clock cycles earlier and storing x(n−L) is selected for use via its associated switch. The two selected capacitors in tap sections 230 and 240 and input capacitor 224 are used in a charge sharing operation that implements the multiplications with filter coefficients b0 through b2 and the summing of the multiplier outputs in equation (1).
The charge sharing operation uses capacitor size to achieve multiplication with a filter coefficient and current summing to achieve summing of the multiplier outputs. For each capacitor within PSC filter 200, the voltage Vij across that capacitor is determined by the Vin signal at the time the capacitor is charged, or Vij=Vin. The electrical charge Qij stored by each capacitor is determined by the voltage Vij across that capacitor and the capacitance Cij of the capacitor, or Qij=Vij·Cij. In each clock cycle, one capacitor storing the proper sample x(n−L) from each tap section is selected, and the charges from all selected capacitors and input capacitor 224 are shared. The charge sharing for the FIR filter may be expressed as:
where p ∈ {0, 1} is an index of the capacitor storing x(n−1) in tap section 230, and
q ∈ {0, 1, 2} is an index of the capacitor storing x(n−2) in tap section 240.
Since the capacitors in each tap section have the same capacitance, the total output capacitance Cout observed by the Vout signal is constant for each clock cycle and is equal to the total input capacitance, or Cout=Cin. The constant Cout may be desirable for a constant signal insertion loss, which occurs when the signal is provided from Cout to a capacitive load. Furthermore, no extra capacitors are needed for Cout, which utilizes the capacitors used for charge sharing in the three sections.
Index p can cycle between 0 and 1, so that in each clock cycle one capacitor 234 in tap section 230 is charged, and the other capacitor 234 is used for charge sharing. Index q can cycle from 0 through 2, so that in each clock cycle one capacitor 244 in tap section 240 is charged, and another capacitor 244 is used for charge sharing. PSC filter 200 may be considered as having six states for the six different (p, q) combinations.
In the design shown in
As shown in
For PSC filter 200, the capacitors in each tap section are selected for charging in a sequential manner, one capacitor in each clock cycle. For input section 220, capacitor C00 is selected for charging in each clock cycle. For tap section 230, index u is cycled from 0 through 1, capacitor C10 is selected for charging in one clock cycle, then capacitor C11 is selected for charging in the next clock cycle, then capacitor C10 is selected for charging in the following clock cycle, etc. For tap section 240, index v is cycled from 0 through 2, capacitor C20 is selected for charging in one clock cycle, then capacitor C21 is selected for charging in the next clock cycle, then capacitor C22 is selected for charging in the following clock cycle, then capacitor C20 is selected for charging in the next clock cycle, etc.
In general, for FIR tap L, the capacitor charged in clock cycle n is selected for charge sharing in clock cycle n+L to achieve a delay of L clock cycles. For input section 220 with L=0, capacitor C00 is used for charge sharing in the same clock cycle that it is charged. For tap section 230 with L=1, the capacitor charged in clock cycle n is selected for charge sharing in clock cycle n+1. For tap section 240 with L=2, the capacitor charged in clock cycle n is selected for charge sharing in clock cycle n+2.
The capacitors used for charge sharing in a given clock cycle are reset at the end of that clock cycle and then charged in the next clock cycle, so that u(n+1)=p(n) and v(n+1)=q(n). There is thus no time gap between the time when a sample is discarded from any given capacitor and the time when that capacitor is reused for a new sample. This results in each capacitor being utilized in each clock cycle, and hence no waste of capacitors.
Table 2 summarizes the action performed by each capacitor in PSC filter 200 in each clock cycle. In Table 2, “store” x(n) means that a capacitor is being charged with a new value from the Vin signal in clock cycle n, “hold” x(n) means that the capacitor is holding the stored value in clock cycle n, and x(n)→y(n+L) means that the capacitor is providing the stored value obtained in clock cycle n for charge sharing in clock cycle n+L.
As shown in Table 2, in each clock cycle, one capacitor in each tap section stores the Vin signal, and a different capacitor in each tap section provides its stored value for charge sharing to generate the Vout signal. Capacitor C00 stores the Vin signal during the read phase of each clock cycle and provides the stored value during the charge sharing phase of the same clock cycle. For FIR tap 1, a delay of one clock cycle is obtained by charging a capacitor in clock cycle n and using that capacitor for charge sharing in clock cycle n+1. For FIR tap 2, a delay of two clock cycles is obtained by charging a capacitor in clock cycle n and using that capacitor for charge sharing in clock cycle n+2. In each clock cycle n, a stored value x(n) from capacitor C00 in input section 220, a stored value x(n−1) from one capacitor in tap section 230, and a stored value x(n−2) from one capacitor in tap section 240 are used to obtain the Vout signal.
Referring back to
An input capacitor and the enabled capacitor in each section may be charged with an input signal during a first/read phase of the clock cycle (block 514). Another capacitor in each of the multiple sections may be selected for charge sharing (block 516). Charges on the input capacitor and the selected capacitor in each section may be shared during a second/charge sharing phase of the clock cycle (block 518). A voltage value on the input capacitor and the selected capacitor in each section may be provided as an output signal during a third/write phase of the clock cycle (block 520). The input capacitor and the selected capacitor in each section may be reset/discharged during a fourth/reset phase of the clock cycle (block 522).
Two delay elements 610b and 610c are coupled in series, with each delay element 610 providing a delay of one clock cycle. Delay element 610b receives the output sample y(n) and provides a delayed sample y(n−1). Delay element 610c receives delayed sample y(n−1) and provides a delayed sample y(n−2). IIR filter 600 includes two IIR taps 1 and 2 for second order. A multiplier 620b for IIR tap 1 is coupled to the output of delay element 610b. A multiplier 620c for IIR tap 2 is coupled to the output of delay element 610c. Multipliers 620b and 620c multiply their samples with filter coefficients c1 and c2, respectively, for the two IIR taps. Summer 630b sums the outputs of multipliers 620b and 620c and provides its output to summer 630a.
The output sample y(n) from IIR filter 600 may be expressed as:
y(n)=c0·x(n)−c1·y(n−1)−c2·y(n−2). Eq (9)
A transfer function H(z) for IIR filter 600 may be expressed as:
The filter coefficients may be defined to meet the following condition:
|c
0
|+|c
1
|+|c
2|=1. Eq (11)
The condition in equation (11) ensures that a PSC filter for IIR filter 600 can meet a power constraint. Filter coefficients c1 and c2 may be selected to obtain a desired frequency response for IIR filter 600. If |c1+|c2|<1, then c0 may be defined as c0=1−|c1|−|c2|. If |c1|+|c2|>1, then other techniques may be used to implement the IIR filter.
Input section 720 includes a capacitor 724 coupled between the summing node and circuit ground. Tap section 730 includes a switch 732 coupled in series with a capacitor 734, the combination of which is coupled between the summing node and circuit ground. Tap section 740 includes two switches 742a and 742b coupled in series with two capacitors 744a and 744b, respectively. Both series combinations of switch 742 and capacitor 744 are coupled between the summing node and circuit ground. Capacitor 734 in tap section 730 and capacitors 744a and 744b in tap section 740 may be reset at the start of filtering operation.
All capacitors in each section of PSC filter 700 have the same capacitance, which is determined by the filter coefficients. The capacitances of the capacitors in the three sections of PSC filter 700 may be given as:
C
00
′=K·c
0, Eq (12)
C
10
′=K c
1, and Eq (13)
C
20
′=C
21
′=K·c
2. Eq (14)
As shown in equations (12) through (14), the size of each capacitor Cij′ is proportional to the magnitude of the corresponding filter coefficient ci. A negative capacitor for a negative coefficient may be obtained by switching the polarity of the capacitor between the read phase and the charge sharing phase.
In general, the number of capacitors to use for each IIR tap is determined by the delay for that IIR tap. L capacitors of the same size may be used for IIR tap L, where L=1, 2, . . . . In each clock cycle, one capacitor that was charged L clock cycles earlier and storing y(n−L) may be used to generate y(n) for the output signal, and this capacitor may store y(n) for use to generate y(n+L). The L capacitors may be charged in a sequential order, one capacitor in each clock cycle, and may store samples y(n) through y(n−L+1) in any given clock cycle n.
In each clock cycle, switch 712 is closed for a brief period of time to charge capacitor 724 in section 720 with the Vin signal. The total input capacitance observed by the Vin signal is thus Cin=C00′, and no extra capacitors are needed for Cin.
In each clock cycle, an appropriate capacitor in each tap section is used to generate the Vout signal. For IIR tap L, the capacitor charged L clock cycles earlier and storing y(n−L) is selected for charge sharing via its associated switch. Two selected capacitors in tap sections 730 and 740 and input capacitor 724 are used in a charge sharing operation that implements the multiplications with filter coefficients c0 through c2 and the summing of the multiplier outputs in equation (9). The charge sharing for the IIR filter may be expressed as:
where m ∈ {0, 1} is an index of the capacitor storing y(n−2) in tap section 740.
After completing the charge sharing, the voltage across capacitors C00′, C10′ and C2m′ corresponds to y(n). Capacitors C10′ and C2m′ may store y(n) for use in subsequent clock cycles. Capacitor C00′ may provide y(n) for the Vout signal. The total output capacitance observed by the Vout signal is Cout=C00′, and no extra capacitors are needed for Cout.
Index m can cycle between 0 and 1, so that each capacitor 744 in tap section 740 is used for charge sharing in alternate clock cycle. PSC filter 700 may be considered as having two states for the two possible values of m.
In the design shown in
For cycle 0, only input capacitor C00′ is charged with the Vin signal. The S10′ and S20′ control signals are asserted during the charge sharing phase, and capacitors C00′, C10′ and C20′ are used to generate the Vout signal. Capacitors C10′ and C20′ store the Vout signal at the end of the charge sharing phase. For cycle 1, only capacitor C00′ is charged with the Vin signal. The S10′ and S21′ control signals are asserted during the charge sharing phase, and capacitors C00′, C10′ and C21′ are used to generate the Vout signal. Capacitors C10′ and C21′ store the Vout signal at the end of the charge sharing phase.
For PSC filter 700, capacitor C00′ in section 720 is charged with the Vin signal in each clock cycle and is also used for charge sharing in the same clock cycle. For tap section 730, capacitor C10′ is used for charge sharing in each clock cycle and stores y(n) for use in the next clock cycle. For tap section 740, index m toggles between 0 and 1, capacitor C20′ is selected for charge sharing in one clock cycle, then capacitor C21′ is selected for charge sharing in the following clock cycle, etc.
In general, for IIR tap L, the capacitor used for charge sharing in clock cycle n stores y(n) after completing the charge sharing. This capacitor is selected for charge sharing again in clock cycle n+L to achieve a delay of L clock cycles. For tap section 730 with L=1, capacitor C10′ is used for charge sharing in clock cycle n, stores y(n) after completing the charge sharing, and is used for charge sharing again in clock cycle n+1 to provide y(n) in the computation of y(n+1). For tap section 740 with L=2, one capacitor is used for charge sharing in clock cycle n, stores y(n) after completing the charge sharing, and is used for charge sharing again in clock cycle n+2 to provide y(n) in the computation of y(n+2). For each tap section, the capacitors used for charge sharing in a given clock cycle is used to store y(n) after completing the charge sharing. There is thus no time gap between the time when a sample is discarded from any given capacitor and the time when that capacitor is reused for a new sample. This results in each capacitor being utilized in each clock cycle, and hence no waste of capacitors.
Table 4 summarizes the action performed by each capacitor in PSC filter 700 in each clock cycle.
As shown in Table 4, in each clock cycle, only input capacitor C00′ stores the Vin signal. In each clock cycle, one capacitor in each section provides the stored value for charge sharing to generate the Vout signal. For IIR tap 1, a delay of one clock cycle is obtained by storing y(n) in capacitor C10′ in clock cycle n and using this capacitor for charge sharing in clock cycle n+1. For IIR tap 2, a delay of two clock cycles is obtained by storing y(n) in a capacitor in clock cycle n and using that capacitor for charge sharing in clock cycle n+2. In each clock cycle n, a stored value x(n) from capacitor C00′, a stored value y(n−1) from capacitor C10′ in tap section 730, and a stored value y(n−2) from one capacitor in tap section 740 are used to obtain the Vout signal.
Referring back to
Charges on the input capacitor and the selected capacitor in each section may be shared during a second/charge sharing phase of the clock cycle to obtain a voltage value (block 1016). The voltage value on the selected capacitor in each section may be stored at end of the second phase (block 1018). The voltage value on the input capacitor may be provided as an output signal during a third/write phase of the clock cycle (block 1020). The input capacitor may be reset/discharged during a fourth/reset phase of the clock cycle (block 1022).
Decimator 1120 may also be a summing decimator and may sum N input samples and provide one output sample. The summing decimator is equivalent to an N-tap FIR filter followed by a non-summing decimator. The summing decimator can provide lowpass filtering, with the filter response being dependent on the N weights for the N input samples being summed for each output sample. In general, any set of weights may be applied to the N input samples being summed. However, a non-weighted sum with equal weights for all N input samples may be adequate for most applications and may result in simpler implementation of the summing decimator. In any case, the lowpass filtering provided by the summing decimator may simplify filtering requirement of preceding FIR or IIR filter 1110.
As an example, it may be desirable to implement an 8-tap FIR filter with tap coefficients of [1 3 5 7 7 5 3 1] followed by a non-summing decimator with a decimation factor of 4. This combination of FIR filter and non-summing decimator may be implemented with a 5-tap FIR filter with tap coefficients of [1 2 2 2 1] followed by a summing decimator with a decimation factor of 4 and equal weights of [1 1 1 1]. The summing decimator may thus reduce the complexity and size of the preceding FIR filter. For example, the 8-tap FIR filter and non-summing decimator may be implemented with 144 unit capacitors whereas the 5-tap FIR filter and summing decimator may be implemented with 48 unit capacitors.
To simplify implementation, decimator 1120 may be merged with preceding FIR or IIR filter 1110. The merged design may reduce insertion loss over a separate design in which FIR or IIR filter 1110 and decimator 1120 are implemented with separate PSC stages. In particular, the separate design would have (i) insertion loss between the preceding FIR/IIR filter 1110 and decimator 1120 and (ii) insertion loss between decimator 1120 and a succeeding stage (not shown in
Input section 1220 includes four switches 1222a to 1222d coupled in series with four capacitors 1224a to 1224d, respectively. The four series combinations of switch 1222 and capacitor 1224 are coupled between a summing node A and circuit ground. Tap section 1230 includes five switches 1232a to 1232e coupled in series with five capacitors 1234a to 1234e, respectively. The five series combinations of switch 1232 and capacitor 1234 are coupled between the summing node and circuit ground. Tap section 1240 includes six switches 1242a to 1242f coupled in series with six capacitors 1244a to 1244f, respectively. The six series combinations of switch 1242 and capacitor 1244 are coupled between the summing node and circuit ground. All capacitors in each section may have the same capacitance/size, which may be determined by the corresponding filter coefficient as described above.
In general, for decimation by N, input section 1220 may include N capacitors 1224, tap section 1230 may include N+1 capacitors 1234, and tap section 1240 may include N+2 capacitors 1244. Each section with decimation by N may thus include N−1 more capacitors than the corresponding section without decimation. Output switch 1216 may be enabled once every N clock cycles for decimation by N (instead of once every clock cycle without decimation). In every N-th clock cycle, N samples within each tap section (instead of one sample per tap section without decimation) may be selected and combined to obtain an output sample.
Each clock cycle may be partitioned into four phases 0, 1, 2 and 3, as shown in
The design in
Input section 1320 includes four switches 1322a to 1322d coupled to four capacitor 1324a to 1324d, respectively. The four series combinations of switch 1322 and capacitor 1324 are coupled between a summing node A and circuit ground. Tap section 1330 includes a switch 1332 coupled in series with a capacitor 1334, the combination of which is coupled between the summing node and circuit ground. Tap section 1340 includes two switches 1342a and 1342b coupled in series with two capacitors 1344a and 1344b, respectively. Both series combinations of switch 1342 and capacitor 1344 are coupled between the summing node and circuit ground. Capacitor 1334 in tap section 1330 and capacitors 1344a and 1344b in tap section 1340 may be reset at the start of filtering operation. All capacitors in each section of PSC filter 1300 may have the same capacitance, which may be determined by the filter coefficients as described above.
In general, for decimation by N, input section 1320 may include N capacitors 1324. Each tap section with decimation by N may include the same number of capacitors as the corresponding tap section without decimation. Output switch 1316 may be enabled once every N clock cycles for decimation by N (instead of once every clock cycle without decimation). In every N-th clock cycle, N samples from input section 1320 may be combined to obtain an output sample.
Each clock cycle may be partitioned into four phases 0, 1, 2 and 3, as shown in
A FIR section and an IIR section may be combined into an ARMA filter, which may have certain advantages. For example, the ARMA filter may be able to synthesize a more complex filter response and may have lower insertion loss.
The output sample y(n) from ARMA filter 1400 may be expressed as:
y(n)=b0·x(n)+b1·x(n−1)+b2·x(n−2)−c1·y(n−1)−c2·y(n−2) Eq (16)
A transfer function H(z) for ARMA filter 1400 may be expressed as:
The filter coefficients may be defined to meet the following condition:
|b
0
|+|b
1
|+|b
2
|+|c
1
|+|c
2|=1. Eq (18)
The condition in equation (18) ensures that a PSC filter for ARMA filter 1400 can meet a power constraint. Filter coefficients b0, b1 and b2 may be selected to obtain a desired frequency response for FIR section 1402. Filter coefficients c1 and c2 may be selected to obtain a desired frequency response for IIR section 1404.
Input section 1520 includes a capacitor 1524 coupled between the summing node and circuit ground. Tap section 1530 includes two switches 1532a and 1532b coupled in series with two capacitors 1534a and 1534b, respectively, between the summing node and circuit ground. Tap section 1540 includes three switches 1542a, 1542b and 1542c coupled in series with three capacitors 1544a, 1544b and 1544c, respectively, between the summing node and circuit ground. Tap section 1550 includes a switch 1552 and a capacitor 1554 coupled in series and between the summing node and circuit ground. Tap section 1560 includes two switches 1562a and 1562b coupled in series with two capacitors 1564a and 1564b, respectively, between the summing node and circuit ground.
All capacitors in each tap section have the same capacitance, which is determined by the filter coefficient for the corresponding FIR or IIR tap. The capacitances of the capacitors in sections 1520, 1530 and 1540 may be given as shown in equations (4), (5) and (6), respectively. The capacitances of the capacitors in tap sections 1550 and 1560 may be given as shown in equations (13) and (14), respectively.
The sizes of the capacitors in the FIR and IIR sections of the ARMA filter may be selected to meet the power constraint. If (|c1|+|c2|)<1, then |b0|+|b1|+|b2| may be scaled down to be equal to 1−(|c1|+|c2|). If (|c1|+|c2|)≧1, then other techniques may be applied to resolve the power constraint, similar to the IIR case.
The Sin, Sout, Sreset and Sij control signals for FIR section 1402 for the six cycles 0 through 5 are as shown in
A more complex filter may be implemented by cascading multiple FIR sections, multiple IIR sections, multiple ARMA sections, or any combination thereof. In general, each filter section may have any order and any filter response.
In one design, filter 1700 is a lowpass filter having a bandwidth of 0.25·fsamp, where fsamp is the sampling rate or clock rate. Filter 1700 also provides 20 dB of attenuation from 0.2645·fsamp to 0.5·fsamp. The overall transfer function H(z) of filter 1700 may be expressed as:
where H1(z)=1+1.25z−1+z−2, Eq (20)
H
2(z)=1/(1−0.375z1+0.375z−2), Eq (21)
H
3(z)=1+0.25z−1+z−2, and Eq (22)
H
4(z)=1/(1+0.875z−2). Eq (23)
As shown in equation (19), the overall transfer function H(z) is composed of two second-order FIR sections with transfer functions H1(z) and H3(z) and two second-order IIR sections with transfer functions H2(z) and H4(z).
The capacitors for FIR section 1720 with H1(z) may be computed as shown in equations (4) to (6) and given as:
C00;C10:C11;C20:C21:C22=1;1.25:1.25;1:1:1=4;5:5;4:4:4. Eq (24)
The capacitors for FIR section 1722 with H3(z) may be given as:
C00;C10:C11;C20:C21:C22=1;0.25:0.25;1:1:1=4;1:1;4:4:4. Eq (25)
The capacitors for IIR section 1730 with H2(z) may be given as:
C00;C10;C20:C21=0.25;0.375;0.375:0.375=2;3;3:3. Eq (26)
The capacitors for IIR section 1732 with H4(z) may be given as:
C00;C10;C20:C21=0.125;0;0.875:0.875=1;0;7:7. Eq (27)
Capacitor C00 for each IIR section is selected based on the power constraint shown in equation (11).
Equations (24) through (27) give the capacitor sizes for the four filter sections if each filter section is implemented separately, e.g., as shown in
The PSC filters described herein may provide certain advantages. First, the PSC filters do not utilize an amplifier within the filter, which may reduce size and power consumption. Amplifiers may be used for input/output buffering. Second, the PSC filters may be able to provide an accurate frequency response, which is determined by capacitance ratios that can be more accurately achieved in an integrated circuit (IC). Third, the PSC filters may have high adaptability since it uses an array of capacitors that may be configured during operation, e.g., to obtain different filter responses.
The PSC filters described herein may be used for various applications such as wireless communication, computing, networking, consumer electronics, etc. The PSC filters may also be used for various devices such as wireless communication devices, cellular phones, broadcast receivers, personal digital assistants (PDAs), handheld devices, wireless modems, laptop computers, cordless phones, Bluetooth devices, consumer electronics devices, etc. For clarity, the use of the PSC filters in a wireless communication device, which may be a cellular phone or some other device, is described below. The PSC filters may be used to pass a desired signal, to attenuate jammers and out-of-band noise and interference, and/or to perform other functions in the wireless device.
On the receive path, an antenna 2012 may receive radio frequency (RF) modulated signals transmitted by base stations and provide a received RF signal, which may be routed through an RF unit 2014 and provided to receiver 2020. RF unit 2014 may include an RF switch and/or a duplexer that can multiplex RF signals for the transmit and receive paths. Within receiver 2020, a low noise transconductance amplifier (LNTA) 2022 may amplify the received RF signal (which may be a voltage signal) and provide an amplified RF signal (which may be a current signal). A passive sampler 2024 may sample the amplified RF signal, perform frequency downconversion via a sampling operation, and provide analog samples. An analog sample is an analog value for a discrete time instant. A filter/decimator 2026 may filter the analog samples, perform decimation, and provide filtered samples at a lower sample rate. Filter/ decimator 2026 may be implemented with any of the PSC filters described herein.
The filtered samples from filter/decimator 2026 may be amplified by a variable gain amplifier (VGA) 2028, filtered by a filter 2030, further amplified by an amplifier (AMP) 2032, further filtered by a filter 2034, and digitized by an analog-to-digital converter (ADC) 2036 to obtain digital samples. Filter 2030 and/or 2034 may be implemented with any of the PSC filters described herein. VGA 2028 and/or amplifier 2032 may be implemented with switched-capacitor amplifiers that can amplify the analog samples from filters 2026 and 2030. A digital processor 2050 may process the digital samples to obtain decoded data and signaling. A control signal generator 2038 may generate a sampling clock for passive sampler 2024 and control signals for filters 2026, 2030 and 2034. The control signals may be as shown in
On the transmit path, transmitter 2040 may process output samples from digital processor 2050 and provide an output RF signal, which may be routed through RF unit 2014 and transmitted via antenna 2012. For simplicity, details of transmitter 2040 are not shown in
Digital processor 2050 may include various processing units for data transmission and reception as well as other functions. For example, digital processor 2050 may include a digital signal processor (DSP), a reduced instruction set computer (RISC) processor, a central processing unit (CPU), etc. A controller/processor 2060 may control the operation at wireless device 2000. A memory 2062 may store program codes and data for wireless device 2000. Data processor 2050, controller/processor 2060, and/or memory 2062 may be implemented on one or more application specific integrated circuits (ASICS) and/or other ICs.
The received RF signal from antenna 2012 may contain both a desired signal and jammers. A jammer is a large amplitude undesired signal that is close in frequency to a desired signal. The jammers may be attenuated prior to ADC 2036 to avoid saturation of the ADC. Filters 2026, 2030 and/or 2034 may attenuate the jammers and other out-of-band noise and interference and may each be implemented with any of the PSC filters described herein.
The PSC filters described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronics device, etc. The PSC filters may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.
An apparatus implementing any of the PSC filters described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.
In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
