Fields of the invention include signal reception and receivers. The invention concerns a passive and tunable load modulation network for high-efficiency power amplifiers (PAs). The invention is applicable to high-efficiency power amplifiers used in wireless transceivers, including those used in 5G wireless networks. Additional applications include RF (radio frequency), microwave, and millimeter transmitters where load impedance controls the output power and efficiency delivered by a transistor.
Emerging 5G wireless networks achieve high data rates through the use of orthogonal frequency division multiplexing (OFDM) waveforms, which have high peak-to-average power ratios and require high PA efficiency at up to 10 dB back-off from the peak transmit power [1]. Load modulation improves backoff efficiency of PAs by exploiting the relationship between load impedance, efficiency, and output power. Often load modulation is accomplished by leveraging the interaction between two PAs as in Doherty and outphasing architectures [2-5]. However, these designs require multiple amplifiers and often utilize precise phase and amplitude control on the inputs, making them difficult to implement at millimeter-wave (mm-wave) frequencies. Sensitive combining networks between the two paths add additional challenges.
Alternatively, dynamic load modulation (DLM) uses switches to change the output tuning elements of the power amplifier to optimize efficiency for the desired output power [6]. Ideally, the DLM network would change the load impedance for according to an optimum value for peak power and another optimum value for a back-off power level. A heuristic for this is to consider the loadline of the transistor as directly determining the output power of the transistor. If the power is to be reduced, the current of the transistor would be reduce while the voltage swing is maintained to maximize the power efficiency of the transistor. Therefore, the loadline resistance must be increased at the backoff power level to improve efficiency. However, most approaches require a large bank of switched capacitors or varactors to change the load capacitance and therefore cannot access large areas of the Smith chart without significant loss [7], [8], [11], [13]. Scaling the DLM to mm-wave bands is also difficult due to the large parasitic capacitance and resistance associated with the switch or varactor components. Additionally, large banks of switches are generally only feasible in highly-scaled CMOS (complementary metal oxide semiconductor) processes, placing limits on the power handling for the network at the output of the PA.
A preferred embodiment provides a passive, tunable on-chip load modulation network for a high-efficiency power amplifier and includes a ring transmission line. An output is connected to a first point on the ring transmission line. A first switched input is connected to a second point on the ring transmission line, the second point being located on the ring transmission line to provide a first impedance transformation. A second switched input is connected to a third point on the ring transmission line, the third point being located to provide a second impedance transformation that is unique from the first impedance transformation.
A preferred embodiment is a passive, tunable on-chip load modulation network for a high-efficiency power amplifier. The network includes a ring transmission line. An output is connected to a first point on the ring transmission line. A plurality of switched inputs is connected to a plurality of points on the ring transmission line. Each of the plurality of points provides a unique impedance based upon a distance from the first point in one direction around the ring transmission line compared to a distance from the first point in the other direction around the ring transmission line.
A preferred embodiment is a passive, tunable on-chip load modulation network for a high-efficiency power amplifier. The network includes a ring transmission line. An output is connected to a first point on the ring transmission line. A first switched input is connected to a second point on the ring transmission line, the second point being located a symmetrical distance to the first point in both directions around the ring transmission line. A second switched input is connected to a third point on the ring transmission line, the third point being located an asymmetrical distance to the first point in one direction around the ring transmission line compared to the other direction around the ring transmission line. The network can include a third switched input connected to a fourth point on the ring transmission line, the fourth point being located an asymmetrical distance to the first point in one direction around the ring transmission line compared to the other direction around the ring transmission line. Additional switched input points can be added. The balance to consider is a trade-off between the number of selectable impedances and switching insertion losses associated with each additional switched input.
Preferred embodiments provide the best of both outphasing and DLM. An example experimental passive outphasing load modulator (POLM) from 28 GHz was fabricated in a 40 nm GaN process that allows the load impedance to be tuned between 20 and 80 ohms with minimal imaginary load variation. The network switches across a transmission line ring where only one switch is required for each state, enabling low loss and allows for practical device layout at high frequency. The GaN process also allows for high linearity and power handling to provide minimal distortion in transmitting. Another example suitable material system for embodiments of the invention is a CMOS silicon on insulator material system.
Preferred embodiments provide a passive tunable matching network including a tunable ring transmission line that provides selectable real impedance transformations to optimize the loadline match of the PA for output power and/or efficiency. High-power switches can be used to enable post-PA power handling and linearity. An example prototype provides selectable impedances of 15, 50, or 80Ω in three switching states that had switch insertion losses between 1.7 and 3.3 dB and P1dB exceeding 33 dBm at a center frequency of 28 GHz. The example network was wideband, providing a bandwidth exceeding 2.5 GHz.
A preferred POLM network 102 is schematically represented in
and is plotted in
Preferred transmission line rings may be realized as transmission lines or lumped-element based transmission lines according to the electromagnetic implementation that offers the lower loss. Lumped elements (capacitors/inductors) are provided in the thickest metals possible in the integrated circuit process for high quality factor and lowest loss. Additionally, switches can be constructed from the transistors in such way that the transistor gate is presented with an impedance to minimize losses in the switches.
Because the maximum real input impedance is bounded by Z02/(4ZL)), it is desirable for Z0 to be as large as possible to allow for a large input impedance variation. In order to increase the possible range of Zin, artificial transmission lines are used, where the shunt capacitance is distributed, but a stripline coil is used to increase inductance per unit length. By doing this, Z0 can be raised to 100Ω to produce a suitable impedance tuning range and each loop of the artificial transmission line produces a phase shift of 15 degrees at 28 GHz.
Switches Q2 and Q3 are 300 um wide devices for states 2 and 3 while Q1 is a 600 um device for state 1 since the input impedance seen when Q1 is on is significantly lower. To eliminate feed through and improve the isolation of each switch, resonating inductors L1, L2 and L3 are added to their respective switches. Adding the devices to the loop adds significant capacitive loading at each location and inductors L4, L5, and L6 are used to combat this. The values of the inductors are given in Table 1 above. While these inductors prevent undesired loading of the loop, they also limit the bandwidth of the network, especially in state 3 which would normally have the widest bandwidth but is also most sensitive to shunt parasitics.
A combination of switch losses and parasitics on the input lines could cause the impedance at the input to drift above the simulated values of 12, 26, and 48Ω each of the loop inputs. Adding L8 allows the input parasitic of Q3 to be minimized while the combination of C1 and C2 cancels the inductance associated with the length of the input network to create a close to ideal simulated impedance of 15Ω. As a result, additional impedance separation is created between the three states, and utilizing C2 and L7 moves the impedance seen for states 2 and 3 to 45 and 75Ω respectively.
In sum, the capacitances and inductances provide switch tuning to limit performance degradation associated with loading of the ring. L1, L2 and L3 resonate Cds (drain-source capacitance of the transistor). This essentially is the capacitance between the input and output of the switch). L4, L5 and L6 resonate shunt Cout of each device. L7, L8, C1 and C2 help with input matching. Q1 and Q2 are 300 μm devices. Q3 is 600 μm device to account for lower impedance seen at that port of the ring.
Experimental Results
The S-parameters were measured using a 67-GHz vector network analyzer and the input and output pads were de-embedded using on-chip SOLT calibration elements. The probing setup is shown in
The mismatch between the simulated and measured parameters is a result of modeling errors leading to the resonant networks being tuned closer to 29-GHz while the loop network is tuned to 28-GHz. This shift in the center frequency can be seen in the log-scale measurements shown in
The measured ratio of the lowest to highest real impedance presented by the network corresponds to a back-off power of 7.7 dB. In the worst case of state 3 the losses correspond to a theoretical back-off efficiency of 37% compared to just 22% for an ideal class B—a comparison that is plotted in
For a post-PA network, the linearity in each state is important. To measure linearity, a Norsat block up-converter with a saturated power of 44 dBm was used to drive the test-bench. The input power was measured with a 20 dB coupler and Keysight N1913A power meter while the output was measured on a 67 GHz network analyzer. To account for calibration mismatch between source and receiver, the data was smoothed and the loss was normalized to match the low power S-parameters measured previously in a 50Ω environment. After de-embedding cable and probe losses, the insertion loss versus the input power to the network is presented in
The experiments demonstrated improved efficiency of power amplifiers at 28 GHz designed in a 40 nm GaN process. The present switched ring structure allows the impedance to be tuned between 15 and 80Ω and exhibits a maximum loss of 3.3 dB which is sufficient to offset back-off efficiency degradation in traditional amplifiers. Power handling of the network is greater than two watts due to the high breakdown voltage of the GaN devices.
The passive network 102 can be described as a pair of transmission lines with characteristic impedance Z1 and Z2, and a differential phase length relative to the total phase around the loop. Specifically, the differential phase is 2Δ=θ1θ2 and the loop phase is 2Σ=θ1+θ2 where θ2 is the differential phase.
Under the condition that the characteristic impedance of the two arcs are Z1=Z2=Z0, the input impedance is:
the resulting input impedance is plotted in
In
A technology-specific POLM implementation would fix the total loop phase (Σ) but would allow the differential phase to be varied (Δ). In theory, this would require a switch network to tap different locations around the loop.
To understand the viability of POLM applied to a millimeter-wave PA, we consider two candidate circuit technologies: 45-nm CMOS SOI and 150-nm GaN HEMTs. For the CMOS SOI, we consider a 4-stack FET PA approach at 28 GHz to achieve the peak output power of 24.5 dBm. In
A 150-nm GaN HEMT technology targets an output power of 31.5 dBm using a single common source transistor in
Since the POLM can be external to the chip and realized as a separate component between the PA and the antenna, we consider the implementation of the POLM on a GaN substrate to determine the losses of the ring at 28 GHz. A test structure is illustrated in
The schematic of a 0.15 um GaN, 28 GHz PA is shown in
These experiments showed passive outphasing load modulation for reconfiguration of a millimeter-wave PA to achieve high average efficiency and tunable matching impedance. We present symmetric and asymmetric load networks and discussed the application to CMOS SOI and GaN device technologies. The prototype GaN POLM showed matching impedance variation from 3 to 12 Ohms with insertion loss from 0.15 to 0.4 dB. The complete PA design with the POLM integrated showed a PAE of 24% at 30 dBm of output power.
While specific embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.
Various features of the invention are set forth in the appended claims.
The application claims priority under 35 U.S.C. § 119 and all applicable statutes and treaties from prior U.S. provisional application Ser. No. 63/335,268, which was filed Apr. 27, 2022.
Number | Date | Country | |
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63335268 | Apr 2022 | US |