Claims
- 1. Circuitry comprising:
- a) a plurality of transistors coupled to a load for sharing current in the load, wherein each transistor includes a control electrode for adjusting a conductive state of the transistor and first and second additional electrodes for carrying a load current;
- b) control means for coupling a common control signal to the control electrode of each of said plurality of transistors; and
- c) biasing circuitry coupled to said plurality of transistors for applying a biasing voltage to the plurality of transistors to distribute load current among the plurality of transistors;
- d) said biasing circuitry comprising i) a series combination of a diode and a resistor coupled between one additional electrode of said first and second additional electrodes of each transistor and a reference voltage connection and ii) variable resistance means coupled between said one additional electrode of each transistor and the reference voltage connection to provide a current path to the reference voltage connection in parallel to the series combination of the diode and the resistor.
- 2. The circuitry of claim 1 wherein the plurality of transistors comprise field effect transistors.
- 3. The circuitry of claim 1 wherein the variable resistance means comprises at least one center tapped variable resistor for each two transistors and wherein the center tap is connected tot he reference voltage connection and each variable resistor is coupled between said one additional electrode of each of said two transistors.
- 4. The circuitry of claim 1 wherein the reference voltage connection is a ground connection.
- 5. Circuitry comprising:
- a) a plurality of transistors coupled to a load for sharing current in the load, wherein each transistor includes a control electrode for adjusting a conductive state of the transistor and first and second additional electrodes for carrying a load current;
- b) control means for coupling a common control signal to the control electrode of each of said plurality of transistors; and
- c) biasing circuitry coupled to said plurality of transistors for applying a biasing voltage tot he plurality of transistors to distribute load current among the plurality of transistors;
- d) said biasing circuitry comprising i) a series combination of a variable resistance passive element and a constant resistance element coupled between one additional electrode of said first and second additional electrodes of each transistor and a reference voltage connection to provide a first current path and ii) an adjustable resistance means coupled to said one additional electrode of each of the plurality of transistors and tot he reference voltage connection to provide a second current path to the reference voltage connection as current varies in the variable resistance passive element.
- 6. The circuitry of claim 5 wherein the plurality of transistors comprise field effect transistors.
- 7. The circuitry of claim 5 wherein the adjustable resistance means comprises at least one center tapped adjustable resistor for each two transistors and wherein the center tap is connected to the reference voltage connection and each adjustable resistor is coupled between said one additional electrode of said two transistors.
- 8. The circuitry of claim 5 wherein the reference voltage connection is a ground connection.
Government Interests
The invention described herein was made in the performance of work under NASA Contract No. NAS3-25266, and is subject to the provisions of Section 305 of the National Aeronautics and Space Act of 1958, as amended (42 U.S.C. .sctn.2457).
US Referenced Citations (5)
Non-Patent Literature Citations (3)
Entry |
Delaney, "Electronics for the Physicist", 1969, pp. 1-47. |
James Forsythe Techniques for Controlling Dynamic Current Balance in Parallel Power MOSFET Configurations, Proceedings of Powercon 8 G-3, pp. 1-11, Power Concepts, Inc., 1981. |
Technical Info Center Power MOSFET Transistor Data, Motorola, Inc., 1988, pp. 2-7-2 through 2-7-23 and Misc. |