Claims
- 1. A pattern write control circuit comprising:
- memory means, having a plurality of memory planes, for storing color element data, each memory plane storing different color element data respectively to display color dots;
- each memory plane including a plurality of memory elements and a plurality of words each having a group of dots in the same location of each memory element, each of said memory elements including one corresponding bit location in each one of said words, respectively, each of said memory elements including address data receiving means for receiving address data designating one of said bit locations within said memory element, and write-in data receiving means for receiving one-bit data to be written in said one of said bit locations;
- address data supply means for supplying said address data to all of said memory planes, said address data being received on all of said address data receiving means corresponding to all memory elements of each memory plane so that all said one bit locations of said memory elements designated by said address data collectively form one of said words of each plane;
- bit mask writing control means for selecting a selected number of bit locations within each of said one words designated by said address data;
- said bit mask writing control means including bit mask data memory means for storing bit mask data which specifies said selected number of bit locations in each of said one words, and means for supplying a write permission signal to said memory elements selected by the bit mask data; and
- color element data supply means for simultaneously supplying different color element data to the corresponding memory planes respectively, each said color element data being received on the write-in data receiving means of all memory elements of the memory plane corresponding thereto.
- 2. A circuit according to claim 1, wherein said color element data supply means comprises register means for storing the different color element data to be supplied simultaneously to said memory planes respectively, to thereby write the pattern data into the memory planes.
- 3. A circuit according to claim 1, wherein said means for supplying the write permission signal includes gate means for supplying said write permission signal to selected memory elements of the planes in synchronism with a writing access signal supplied from an external device.
- 4. A circuit according to claim 1, wherein said color data supplying means includes a color data register, in which two bit color data pairs, each corresponding to one memory plane and each designating whether a color element is displayed, are stored before the address data are supplied to the memory planes, and one bit of the color data pair is supplied to write-in data receiving means of the memory plane corresponding thereto at intervals of a one bit location, the other bit being supplied to write in receiving means on the remaining bit locations to thereby write tiling dot pattern data into said memory planes.
- 5. A pattern write control circuit comprising:
- memory means, having a plurality of memory planes, for storing different color element data, each memory plane storing different color element data respectively to display color data;
- each of said memory planes including address data receiving means for receiving address data designating a word location of the memory plane, and write-in data receiving means for receiving data to be written in said word location;
- address data supply means for supplying common address data to all of said memory planes, said common address data being received on said address data receiving means of each memory plane; and
- color element data supply means for selectivity supplying different word data to respective write-in data receiving means of said memory planes, bits of said word data assigned to each said memory plane designating at least states where (a) a particular color element is displayed, or (b) that an adjacent color element is not displayed.
- 6. A circuit according to claim 5, wherein said color data supplying means includes a color data register, in which two bit color data pairs, each corresponding to one of the memory planes and each designating whether the color element is to be displayed, are stored before the address data are supplied to the memory planes, one bit of the color pair being supplied to write-in data receiving means of a corresponding memory plane at intervals of a one bit location, the other bit being supplied to write-in data receiving means of a corresponding remaining bit locations, to thereby write a tiling dot pattern data into said memory planes.
- 7. A circuit according to claim 6, further comprising bit mask writing control means for selecting at least one bit location in a word of each memory plane designated by the address data supplied by said address data supply means.
- 8. A circuit according to claim 7, wherein each memory plane includes a plurality of memory elements corresponding to different bit locations in a word of the memory plane, each memory plane having a write-in data receiving means for receiving one-bit data to be written in the location designated by the address data, one of each 2-bit color element data being stored in said color element data register and supplied to said write-in data receiving means of memory elements corresponding to alternate bit locations, the other bit of 2-bit color element data being supplied to write-in data receiving means of the remaining memory elements.
- 9. A circuit according to claim 8, wherein said bit mask writing control means comprises bit mask data memory means for storing bit mask data which selects the bit locations in the word of the memory planes designated by the address data supplied to the memory planes, and means for supplying a writing permission signal to the memory elements which correspond to the bit locations selected by the bit mask data stored in the bit mask data memory.
- 10. A circuit according to claim 9, wherein said means for supplying a writing permission signal includes gate means for supplying a writing permission signal to said memory elements in response to the bit mask data stored in said bit mask data memory means, in synchronism with a writing access signal supplied from an external device.
- 11. A circuit according to claim 7, wherein said color data supplying means comprises a color element data register for storing a 2-bit color data pair corresponding to each of said memory planes and selectively designating whether that a color element corresponding to the memory plane is one of displayed, and not displayed.
- 12. A pattern write control circuit comprising:
- memory means, including a plurality of memory planes for storing color elements data, each said memory plane storing different color element data respectively, to display color dots,
- each of said memory planes including address data receiving means for receiving address data designating a word location of the memory plane and write-in data receiving means for receiving data to be written in the word location;
- address data supply means for supplying common address data to all of said memory planes, said common address data being received on the address data receiving means of each memory plane;
- color element data supply means for simultaneously supplying different color element data to the write-in data receiving means of said memory planes respectively;
- plane selecting means for holding plane selecting data corresponding to each of said memory planes and for selecting one of said memory planes in which pattern data is to be written, in accordance with said plane selecting data; and
- bit mask writing control means for selecting at least one bit location in said word designated by said address data supplied to said address data supply means.
- 13. A circuit according to claim 12, wherein said plane selecting means comprises a plane selection data register for storing the plane selecting data before the address data is supplied to the address data receiving means of said memory planes to write pattern data into said selected memory planes, and means for supplying plane selection signals to the memory planes specified by the plane selecting data stored in the plane selection data register when corresponding color element data is written in the selected memory planes.
- 14. A circuit according to claim 13, wherein said means for supplying the plane selection signal includes gate means for supplying a writing access signal from an external device, as a plane selection signal, to the memory plane specified by the color element data stored in said plane selection data register.
- 15. A circuit according to claim 12, wherein each memory plane includes a plurality of memory elements corresponding to different bit locations in a word of the memory plane respectively, each of which has address data receiving means for receiving address data designating one location of the memory element and write-in data receiving means for receiving one bit data to be written in the location, and said bit mask writing control means comprises bit mask memory means for storing bit mask data which selects bit locations in a word in a location designated by the address data supplied to a plurality of the memory planes, and means supplying write permission signals to the memory elements which correspond to those bit locations in the word having been specified by the bit mask data stored in the bit mask data memory means.
- 16. A circuit according to claim 15, wherein said means for supplying a write permission signal includes gate means for supplying a write permission signal to said memory elements selected by the bit mask data stored in said bit mask data memory means, synchronism with a writing access signal supplied from an external device.
Priority Claims (3)
Number |
Date |
Country |
Kind |
57-225201 |
Dec 1982 |
JPX |
|
57-225202 |
Dec 1982 |
JPX |
|
58-15941 |
Feb 1983 |
JPX |
|
Parent Case Info
This is a continuation of application Ser. No. 563,442, filed Dec. 20, 1983, which was abandoned upon filing hereof.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4016544 |
Morita et al. |
Apr 1977 |
|
4475161 |
Stock |
Oct 1984 |
|
4491836 |
Collmeyer et al. |
Jan 1985 |
|
Foreign Referenced Citations (2)
Number |
Date |
Country |
0105724 |
Sep 1983 |
EPX |
56-63965 |
Apr 1983 |
JPX |
Continuations (1)
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Number |
Date |
Country |
Parent |
563442 |
Dec 1983 |
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