The technology of the disclosure relates generally to audio buses and particularly to SOUNDWIRE NEXT audio buses, and more particularly to clock management through payload manipulation for simple devices associated with audio buses.
Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, enabling enhanced user experiences.
The mobile communication devices commonly include at least one microphone and multiple speakers, although many devices may include multiple microphones as well. The microphone(s) and the speakers used in the mobile communication devices typically have analog interfaces which require a dedicated two-wire connection between each pair of devices. Since a mobile communication device is capable of supporting multiple audio devices, a microprocessor or other control device in the mobile communication device may communicate audio data to multiple audio devices over a common communication bus simultaneously.
In this regard, the MIPI® Alliance initially developed the Serial Low-power Inter-chip Media Bus (SLIMbus℠ or SLIMBUS) to handle audio signals within a mobile communication device. The first release was published in October 2005 with v1.01 released on Dec. 3, 2008, and v2.0 released August 2015. In response to industry feedback, MIPI has also developed SoundWire℠ (SOUNDWIRE), a communication protocol for a processor in the mobile communication device (the “master”) to control distribution of digital audio streams between one or more audio devices (the “slave(s)”) via one or more SOUNDWIRE slave data ports. Version 1.1 was released Jun. 27, 2016 and v1.2 released April 2019. The original SOUNDWIRE was limited to relatively short distances (e.g., <50 cm) that might exist within the mobile communication device. In an effort to accommodate greater distances (e.g., such as when a headset is used), MIPI released a revised protocol, originally referred to as SOUNDWIRE-XL. SOUNDWIRE-XL has been renamed SOUNDWIRE NEXT. A new version of the SOUNDWIRE NEXT specification is expected in October 2018, but as of this writing has not been published.
SOUNDWIRE NEXT has proven exceptionally popular and has been adapted for use within the mobile communication device and not just for distances greater than 50 cm. This popularity has caused more devices (e.g., codecs, speakers, and microphones) to be coupled to the bus. Concurrently, system clocks within the mobile terminal have accelerated, and the speed of the SOUNDWIRE NEXT bus has also increased. As of this writing, in some instances, the SOUNDWIRE NEXT bus may operate at speeds approaching 100 megahertz (MHz).
Many devices, including those that may be attached to a SOUNDWIRE NEXT bus, have a clock recovery circuit that includes a phase-locked loop (PLL) to assist in the stabilization of the recovered clock signal. The higher the frequency of the bus clock, the larger and more expensive the PLL is likely to be. In many instances, commercial pressures dictate that microphones and speakers within mobile terminals or within basic headsets are relatively inexpensive. Thus, the pressure to provide high speeds on the SOUNDWIRE NEXT bus competes with the pressures to keep the PLLs relatively simple. This tension illustrates a need for an alternate approach to clock management on SOUNDWIRE NEXT buses.
Aspects disclosed in the detailed description include systems and methods for payload transport on audio buses for simple pulse division multiplexed (PDM) devices. In an exemplary aspect, simple PDM devices have a phase-locked loop (PLL) that operates at a frequency corresponding to an audio rate on an associated audio bus. Additional parameters are defined relative to a starting synchronization event. The parameters inform a simple PDM device from which bit slots to extract data or into which bit slots to write data. In a further exemplary aspect, a low-cost delay-locked loop (DLL) is used to assist the simple PDM device in calculating the designated bit slots. By limiting the PLL to a relatively low frequency, cost and space are reduced. Further, a lower frequency clock may provide power savings.
In this regard in one aspect, a method of reading data from an audio bus is disclosed. The method includes using a DLL circuit on an input signal. The method also includes selecting, with a multiplexer, at least one of a plurality of outputs from the DLL circuit to form at least one selecting signal. The method also includes processing the at least one selecting signal to form a control signal. The method also includes operating on a slot in an audio signal on the audio bus based on the control signal.
In another aspect, an audio device is disclosed. The audio device includes a bus interface configured to couple to an audio bus operating at a bus frequency. The audio device also includes a clock configured to operate at an audio rate slower than the bus frequency. The audio device also includes a transceiver coupled to the bus interface configured to send and receive data on the audio bus. The audio device also includes a circuit including a DLL and a multiplexer. The circuit is configured to use the DLL on an input signal from the audio bus. The circuit is also configured to select with the multiplexer, at least one of a plurality of outputs from the DLL to form at least one selecting signal. The circuit is also configured to process the at least one selecting signal to form a control signal. The circuit is also configured to operate on a slot in an audio signal on the audio bus based on the control signal.
In another aspect, a method for controlling payloads in an audio bus is disclosed. The method includes defining a synchronization event (sync event) corresponding to an audio rate. The method also includes defining a sample window interval corresponding to a number of sync events. The method also includes defining an offset relative to an initial sync event. The method also includes inserting data or receiving data at a device at the offset once per sample window interval.
In another aspect, an audio device is disclosed. The audio device includes a bus interface configured to couple to an audio bus operating at a bus frequency. The audio device also includes a clock configured to operate at an audio rate slower than the bus frequency. The audio device also includes a transceiver coupled to the bus interface configured to send and receive data on the audio bus. The audio device also includes a control system. The control system is configured to insert data or receive data at a predefined offset from a sample window interval start using the clock.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include systems and methods for payload transport on audio buses for simple pulse division multiplexed (PDM) devices. In an exemplary aspect, simple PDM devices have a phase-locked loop (PLL) that operates at a frequency corresponding to an audio rate on an associated audio bus. Additional parameters are defined relative to a starting synchronization event. The parameters inform a simple PDM device from which bit slots to extract data or into which bit slots to write data. In a further exemplary aspect, a low-cost delay-locked loop (DLL) is used to assist the simple PDM device in calculating the designated bit slots. By limiting the PLL to a relatively low frequency, cost and space are reduced. Further, a lower frequency clock may provide power savings
Exemplary aspects of the present disclosure are well-suited for use in SOUNDWIRE NEXT audio systems. However, to provide context for a SOUNDWIRE NEXT audio system, a variety of audio systems are discussed. In this regard, a SOUNDWIRE audio system is discussed with reference to
In this regard,
As better illustrated in
Similarly, a slave device 106 is illustrated in
In an exemplary aspect, ports on the slave devices 106(1) and 106(2) may act as audio sources in that an audio signal or stream originates therefrom. Likewise, ports on the slave devices 106(3) and 106(4) may act as audio sinks in that audio signals are sent thereto. It should be appreciated that it is possible that the slave devices 106(1)-106(4) may be multi-port devices and thus, could be audio sources and audio sinks. Ports on the master device 104, relative to the slave devices 106(1) and 106(2) may be audio sinks, but may be audio sources relative to the slave devices 106(3) and 106(4). In this regard, the master device 104 may have one or more data ports. That is, a particular port within the master device 104 may be functioning as an audio source or audio sink depending on the nature of the link for the port. It should be appreciated that terms such as audio source and audio sink are frequently used in the industry and refer to, in the case of an audio source, a device from which an audio stream originates. Likewise, an audio sink refers to a device to which an audio stream is sent.
While the audio system 100 of
With continued reference to
Note further, SOUNDWIRE NEXT currently supports a multi-drop arrangement and would look similar to the SOUNDWIRE audio system 100 of
SOUNDWIRE NEXT defines a conceptual row in a signal stream. This signal stream 500 is illustrated in
Exemplary aspects of the present disclosure allow the slave devices (and potentially a master) to have a low-frequency PLL that operates at the basic audio clock frequency yet still ascertains appropriate bit slots from which to receive or into which to transmit data. Initially, a few new parameters are defined which are exchanged during initialization of the bus. While particular names are given to these parameters, these names are matters of convenience, and the parameters may be renamed without departing from the present disclosure. These parameters include a sample window interval (sometimes referred to as S herein); a number of samples in a sample window interval (sometimes referred to as N herein); a row offset number (sometimes referred to as R herein); a sample width (sometimes referred to as W herein); a number of channels in a data port (sometimes referred to as C herein); and a horizontal start of window (sometimes referred to as ST herein). Optionally, a port type and a horizontal stop parameter may also be defined.
The sample window interval indicates how many rows are in a given sample. Relative to SOUNDWIRE NEXT, the sample window interval replaces the sample interval. The number of samples in a sample window interval is just that—the number of samples. This value enables groups of multiple samples in an interval. The row offset number indicates within the total number of rows (S) which row has a valid sample. The sample width indicates the number of bits per data sample. The number of channels is just that—the number of channels for the data port. The horizontal start of window indicates how many columns into the row the sample starts relative to the row start. The port type indicates if there are multiple channels inside a row or just one channel per row. The horizontal stop indicates which column is the last of the sample relative to a row beginning.
To assist in understanding the parameters just introduced,
In contrast, the signal flow 650 has S=1; N=2; R=0; W=2; C=1; and ST=12. The signal flow 650 assumes a row rate of 2.4 MHz with 32 columns in a row (equivalent to a bus rate of 76.8 MHz) and a single channel (C=1). In this case, the audio rate is 4.8 MHz, which causes the selection of S and N to change to make sure that the throughput remains at the desired levels. Four rows make up the sample window interval 654 (S=4). The sample is in each of the rows 656(1)-656(4) (assuming the first row is designated as 0; R=0). The sample is two bits 658(1)-658(2) (W=2), but N is two, so there are two samples side by side. The sample is offset from the beginning of the row by twelve columns 660 (ST=12). The next sample appears in the same spot in the next sample window interval 662. The slave device 106 may omit the PLL 119, or if the slave device 106 has a PLL 119, the PLL 119 only has to be capable of matching the audio rate of 2.4 MHz (with a simple doubler) or 4.8 MHz and not the bus rate of 76.8 MHz.
It should be appreciated that the signal flows 600 and 650 are provided as examples and show the flexibility and versatility of the present disclosure. Changing the value of S effectively changes the frequency, while changing the value of C, N, or W changes how much data is being sent. Changing the values of R and ST allows data to be positioned as desired within the sample interval window.
To be able to find the appropriate bit slots or columns into which to place transmitted data or from which to extract received data, exemplary aspects of the present disclosure add a DLL circuit 700, illustrated in
Each delay element within the DLL circuit 700 includes a respective output tap 704(1)-704(M). The output taps 704(1)-704(M) are provided to a multiplexer (MUX) 706 that selects an appropriate column pulse based on inputs ST and W received through an offset input and a sample width input. The output 707 of the multiplexer 706 is provided to a number of AND gates 708(1)-708(P), where P is equal to the highest expected W. The AND gates 708(1)-708(P) also receive inputs from respective flip-flops 710(1)-710(P). The AND gates 708(1)-708(P) also receive inputs from a row select counter circuit 712 that indicates which row is to be selected based on input R. The flip-flops 710(1)-710(P) receive input from an analog-to-digital sampling circuit 714 and a sample window counter circuit 716 which operates based on S and N. The output of the AND gates 708(1)-708(P) is provided to an OR gate 718 which in turn provides an output to a second OR gate 720. The second OR gate 720 also receives an input based on any possible additional channels (which would have their own set of AND gates and the like). The second OR gate 720 indicates to the interface 110 from which bit slots to extract data or into which bit slots to place data. Note that the interface 110 may not know the precise bit slot, but has an offset relative to the sync event of the appropriate row and uses the data at that spot in the row.
Note that aspects of the present disclosure can be used for multi-channel aggregation by one device (typically a master) as well. Thus, a master, for example, may receive multiple individual channel streams, each one coming from a single device, but together forming a multi-channel stream. An example of such is illustrated in
In contrast,
A process 1000 according to an exemplary aspect of the present disclosure is illustrated with reference to
The master device 104 then defines the offset (block 1008), which may include a row offset (R) (block 1008A) as well as a start of row offset (ST). Width may likewise be set to indicate a channel width as well as C to define the number of channels. The master devices 104 and slave devices 106 then insert data and retrieve data in the sample window interval based on the offset (block 1010).
An exemplary process 1050 associated with use of the DLL circuit 700 is provided with reference to
The systems and methods for payload transport on audio buses for simple PDM devices according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.
Exemplary aspects of the present disclosure are well suited for use with a SOUNDWIRE NEXT bus. There are a variety of locations in a computing device at which a SOUNDWIRE NEXT bus may be placed. In this regard,
With continued reference to
With continued reference to
With continued reference to
Similarly,
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The devices described herein may be employed in any circuit, hardware component, IC, or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present application claims priority to U.S. Provisional Patent Application Ser. No. 62/745,527 filed on Oct. 15, 2018 and entitled “PAYLOAD TRANSPORT ON AUDIO BUSES FOR SIMPLE PULSE DIVISION MULTIPLEXED (PDM) DEVICES,” the contents of which is incorporated herein by reference in its entirety.
Number | Date | Country | |
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62745527 | Oct 2018 | US |