Patent Application
20130070551
The invention relates to prevention of access to electronically stored data. More particularly, the invention is relates to protection of high-level devices such as FPGA, ASIC and microcontroller microchips or systems boards containing said microchips.
Logic circuits, microprocessor cores, memory controllers, accelerators, etc., are an assembly of combinatorial logic functions and flip-flops (registers). An FPGA, ASIC or microcontroller can be configured to implement a very large interconnected array of such circuits and connect itself to the outside world. A fundamental issue is to protect the proprietary information contained within this interconnected array (bit map states). When a user successfully authenticates the cryptosystem or authentication key the encryption is unlocked and passed to a cryptographic filter. However, if the allocated memory subsection/program within a programmable chip can be accessed, there creates an unauthorized ability to extract the cryptographic keys and to decrypt and analyze the information using a variety of tools and procedures. Access to the key allows an attacker to disable security on the microchip, modify low-level silicon features, access unencrypted configuration bitstream or even permanently damage the device. If an attacker can take control of a high-level device, the attacker can then erase or even physically destroy the device by uploading a malicious bitstream that will cause a high current to pass through the device and burn it out. The attacker can alternatively extract the proprietary data from the device and make some changes to the firmware. The attacker can also enable a clone or reprogram the design, possibly introducing a Trojan so as to carry out more sophisticated attacks at a later date.
A primary issue is that a cryptosystem (secure key) code is accessible when system power is on, retained or backed up for long periods when the system power is shut down. Thus it is desirable to prevent any unauthorized ability to extract the cryptographic keys as to decrypt and analyze the information during such operations using a variety of tools and procedures. An ongoing goal of industry and defense is to integrate some form of attack detection mechanism, that, if triggered, will then cause erasure (‘wipe’) of critical data as to prevent access.
Some prior art devices provide a solution by implementing a scheme for data erasure of the key microchip e.g., ASIC or FPGA, memory code information by storing all of the sensitive data onto a separate independent memory from the encryption data engine, either in volatile or non-volatile format. Such prior art devices then utilize a trigger from an anti-tamper detection system that is physically separate from both the encryption data and either the separate key data device itself or the encryption data engine processor.
Recent revelations of vulnerability of static ROM based encryption data has lead some to store the critical data sets within volatile memory. Most forms of modern random access memory (RAM) are volatile storage, including dynamic random access memory (DRAM) and static random access memory (SRAM). Volatile RAM loses its data quickly when power is removed. For example, DRAM volatile memory refresh rate requires power availability every 8-64 msec, depending upon refresh scheme employed and DRAM architecture. However, in DRAM memory cells capacitors will often retain their values for significantly longer, particularly at low temperatures. This indicates that it will be preferable to store the critical key data in SRAM.
Although it is possible to erase the secure key code, or other, information upon detection of a tamper event with the use of either volatile or non-volatile memory, it can be problematic. When resetting the individual bits to a logic ‘0’, individual memory bits will nevertheless retain some level of charge from their previous state (‘0’ or ‘1’) even upon power discontinuation. This opens up an array of reverse-engineering techniques, including i/o mapping, layer-by-layer removal, non-contact imaging etc. that can now be applied as to extract the previously stored key information.
Accordingly, there is a need for a device that can effectively erase critical data from FPGAs, ASICs and microcontrollers in the event of unauthorized access.
In at least one embodiment, the invention includes a percolation tamper protection circuit comprising a percolation gate, first and second terminals and a volatile memory. The percolation gate includes a pressure conduction composite that has a conductivity that varies proportional to pressure and the percolation gate has a first short circuit state and a second open circuit state. First and second terminals are connected to the percolation gate, where the first terminal is configured for connection to a power supply. A volatile memory is connected to the second terminal whereby current is choked from said volatile memory when said percolation gate switches states thereby erasing data stored in said volatile memory.
In at least one embodiment the invention includes a percolation tamper protection circuit which includes a percolation gate comprising a pressure conduction composite that generates a stress induced output voltage responsive to pressure. First and second terminals are connected to the percolation gate, where the first terminal is configured for connection to a power supply. A volatile memory containing data to be protected is connected to the second terminal. A means for determining whether the stress induced output voltage is indicative of a tamper event is provided that chokes current flow from the power supply to the volatile memory when it is determined that the stress induced output voltage is indicative of a tamper event thereby causing erasure of data stored in said volatile memory.
In at least one embodiment, the invention includes an integrated circuit employing a percolation tamper protection device. The integrated circuit has a housing enclosing a die and a percolation tamper protection device. The die includes a volatile memory. The percolation tamper protection device is connected to the volatile memory and includes a percolation gate that has a conductivity that varies proportional to pressure and first and second terminals connected to the percolation gate. A packing lid is mounted to the housing. The packing lid includes a plurality of pressure amplifiers that compress the percolation gate creating a preload that biases the percolation gate into a near short circuit state.
In at least one embodiment, the invention includes an integrated circuit employing a percolation tamper protection device. The integrated circuit has a housing enclosing a die and the percolation tamper protection device. The die includes a volatile memory. The percolation tamper protection device is connected to the volatile memory and includes a percolation gate that is biased in a conductive state and that has a conductivity that varies proportional to pressure
a illustrates a percolation tamper device in accordance with the invention.
b shows an interdigitated electrode in accordance with the invention.
A conduction path 114 supplies current from power supply 110 to volatile memory 112. Percolation gate 111 alters conduction path 114 in response to physical stress. As with gate voltage of a transistor device, provided the physical stress on percolation gate 111 is above the percolation threshold, percolation gate 111 allows for conduction and dc voltage is supplied to the volatile memory 112 from source 110. As stress is reduced on percolation gate 111 the conduction path will constrict until a point at which insufficient voltage is supplied to support the volatile memory 112 thereby causing the bit states of volatile memory 112 to revert to their null state. While not intending to be bound by theory, it is believed that due to the high Q nature of percolation materials, a very small change in stress around the percolation threshold will cause free flow of electrons through percolation gate 111 to be constricted.
In accordance with an embodiment of the invention, as illustrated in
An exemplary interdigitated trace pair 327 comprising closely spaced first and second interdigitated trace terminals 328a and 328b is depicted in
In keeping with the invention, to ensure that percolation tamper protection device 120 is in its normal conduction region, passive amplifiers 170 are interposed between packaging lid 165 and percolation tamper protection device 120 and percolation tamper protection device 120 is disposed contiguous to and stacked on top of die 130. The number and physical dimensions of such pressure amplifiers 170 control the loading magnitude on the percolation gate 111. For ceramic packaged devices, packaging lid 165 may be provided with two or more pressure amplifiers 170 spaced from each other.
The voltage source 110 may be internal or external to package 160. Suitable internal cavity exemplary voltage sources include long-duration micro sources such as a betavoltaic or superhydrophobic nanostructured batteries. Voltage source 110 is selected as to be capable of producing sufficient power to sustain volatile memory 112 in this normal conduction mode.
Any physical attack on the IC chip; for example, if the device is pried off its circuit board for detailed analysis, or the device is undergoing milling as part of a device reconstruction reverse engineering effort, or the packaging lid 165 is simply tampered with as to inspect the chip will all cause reduction in stress loading on the percolation tamper protection device 120. This stress reduction will cause a very large drop in gate conduction resulting in a loss of support level voltage at volatile memory region 131b, thereby causing the bit data stored in volatile memory region 131b to revert to their null state. Repeated strain loss during a tamper event will cause the voltage across volatile region 131b to similarly go from high to low to high in a continuing repetitive fashion as to cause repeated erasure of the bit states therein.
If an attacker seeks to remove the power source 110 at any point in an attack, the voltage across volatile region 131b is zero and the data bits stored therein will instantly revert to their null state. If the attacker seeks to void such a result and make static the bit states in a zero voltage supply condition by drastically reducing the surrounding temperature of the IC 160, then due to the temperature dependence of percolation materials, the percolation gate 111 supply will have dropped below its percolation threshold much earlier in this process and will no longer allow for conduction from source to drain causing the data bits in volatile memory to revert to their null state.
As used above “substantially,” “generally,” “relatively” and other words of degree are relative modifiers intended to indicate permissible variation from the characteristic so modified. It is not intended to be limited to the absolute value or characteristic which it modifies but rather possessing more of the physical or functional characteristic than its opposite, and preferably, approaching or approximating such a physical or functional characteristic.
Although the present invention has been described in terms of particular embodiments, it is not limited to those embodiments. Alternative embodiments, examples, and modifications which would still be encompassed by the invention may be made by those skilled in the art, particularly in light of the foregoing teachings.
Those skilled in the art will appreciate that various adaptations and modifications of the embodiments described above can be configured without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.
This application claims priority to U.S. patent application Ser. No. 61/535,577 filed on Sep. 16, 2011, which is incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61535577 | Sep 2011 | US |
