Patent Application
20160139649
Embodiments of the present invention relate to memory architectures. Specifically, embodiments of the present invention relate to performance-adjustable memory modules (e.g. DRAMs) configured for power consumption optimization.
Current mobile systems suffer from power leakage and consumption of semiconductor circuits. Moreover, current low-power circuits are based on conventional design schemes. However, mobile multi-core processor (MCP) implementations require a fundamentally different design approach for cores and on-chip memories. Still yet, current memory approaches are based on standard-based fixed speed having a fixed power supply. In some implementations, a sleep mode may be present. However, the sleep mode may take an extensive period of time for the memory to transition between sleep and wake modes.
Typically, existing memory configurations rely on standards-based fixed speed (e.g., fixed response latency and data rate). Moreover, current power supply levels are typically fixed by a standard as well. As such, varying levels of performance and/or power consumption are difficult to achieve/optimize. In such instances, it may take extended periods of time to switch between memory modes (e.g., from a sleep mode to an active mode).
In general, embodiments of the present invention provide a performance-adjustable memory module configured for power consumption optimization. In a typical embodiment, the memory module (e.g., a DRAM-type memory module) comprises a set of memory segments coupled to a set of power supplies. A controller (e.g., an external controller) will supply control information via a set of control registers that is used to vary levels of power provided by the set of power supplies to the set of memory segments. The varying levels of power allow for the performance levels of the set of memory segment to be varied, and thus provide a more optimized memory system.
A first aspect of the present invention provides a performance-adjustable memory module, comprising: a set of memory segments; and a set of power supplies coupled to the set of memory segments, the set of memory segments being configured to operate at varying levels of performance levels based on varying levels of power provided via the set of power supplies.
A second aspect of the present invention provides a performance-adjustable memory system, comprising: a plurality of memory segments; a plurality of power supplies coupled to the plurality of memory segments, the plurality of memory segments being configured to operate at varying levels of performance levels based on varying levels of power provided via the plurality of power supplies; and a controller configured to vary the levels of power levels provided by the plurality of power supplies to the plurality of memory segments.
A third aspect of the present invention provides a method for varying levels of performance in a memory module, comprising: providing control information to the memory module from a controller; utilizing the control information to provide varying levels of power provided from a set of power supplies that are coupled to a set of memory segments in the memory module; and varying levels of performance of the set of power segments based on the varying levels of power provided by the set of power supplies.
These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.
Illustrative embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term “set” is intended to mean a quantity of at least one. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various buffers, cores, grades and/or memories, these buffers, cores, grades, and/or memories should not be limited by these terms. These terms are only used to distinguish one buffer, core, grade, or memory from another buffer, core, grade, or memory. Thus, a first buffer, core, grade, or memory discussed below could be termed a second buffer, core, grade, or memory without departing from the teachings of the present inventive concept.
Embodiments are described herein with reference to cross-sectional or perspective illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an edge or corner region illustrated as having sharp edges may have somewhat rounded or curved features. Likewise, elements illustrated as circular or spherical may be oval in shape or may have certain straight or flattened portions. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region or element of a device and are not intended to limit the scope of the disclosed embodiments.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As indicated above, embodiments of the present invention provide a performance-adjustable memory module configured for power consumption optimization. In a typical embodiment, the memory module (e.g., a DRAM-type memory module) comprises a set of memory segments coupled to a set of power supplies. A controller (e.g., an external controller) will supply control information via a set of control registers that is used to vary levels of power provided by the set of power supplies to the set of memory segments. The varying levels of power allow for the performance levels of the set of memory segment to be varied, and thus provide a more optimized memory system. It is understood that these concepts could be extended and/or implemented at any level of memory architecture hierarchy. For example, similar concepts could be applied at a system and/or card level.
At least some of the teachings described herein utilize concepts of Direct Memory Access (DMA) and/or dynamic random access memory (DRAM). In general, DMA is a feature of modern computers and microprocessors that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit. Many hardware systems use DMA including disk drive controllers, graphics cards, network cards, and sound cards. DMA is also used for intra-chip data transfer in multi-core processors, especially in multiprocessor system-on-chips, where its processing element is equipped with a local memory (often called scratchpad memory) and DMA is used for transferring data between the local memory and the main memory. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without a DMA channel. Similarly, a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time and allowing computation and data transfer concurrency.
Without DMA, using programmed input/output (PIO) mode for communication with peripheral devices, or load/store instructions in the case of multi-core chips, the CPU is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU would initiate the transfer, do other operations while the transfer is in progress, and receive an interrupt from the DMA controller once the operation has been done. This is especially useful in real-time computing applications where not stalling behind concurrent operations is critical.
Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.
The main memory (the “RAM”) in personal computers is dynamic RAM (DRAM). It is the RAM in laptop and workstation computers as well as some of the RAM of video game consoles. The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities. Unlike flash memory, DRAM is volatile memory (cf. non-volatile memory), since it loses its data quickly when power is removed. The transistors and capacitors used are extremely small. Billions can fit on a single memory chip.
DRAM is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and transistor per data bit. The figure to the right shows a simple example with a 4 by 4 cell matrix. Modern DRAM matrices are many thousands of cells in height and width. The long horizontal lines connecting each row are known as word-lines. Each column of cells is composed of two bit-lines, each connected to every other storage cell in the column (the illustration to the right does not include this important detail). They are generally known as the + and − bit-lines. A sense amplifier is essentially a pair of cross-connected inverters between the bit-lines. A first inverter is connected with input from the + bit-line and output to the − bit-line. A second inverter's input is from the − bit-line with output to the + bit-line. This configuration results in positive feedback which stabilizes after one bit-line is fully at its highest voltage and the other bit-line is at the lowest possible voltage.
In any event, under the embodiments of the present invention, memory may be powered up along multiple levels of power/power supply. Memory response time and data rate is adjusted with the power supply changes. As will be shown below, a single memory module may have multiple memory segments in the memory. Each memory segment or a group of segments may be coupled to an independent power supply. The memory segments adjust response time/latency and date rate with adjustments in power provided by power supplies. Along these lines, memory segments may be differentially manufactured with a design intention such that each memory segment may be mapped to different speed modes. Specifically, low-power memory segments may be utilized for lower-performance operations (e.g., sleep) while high-power memory segments may be used for high-performance operations. To optimize power consumption and or performance within the memory module, memory segment(s) may be deactivated by the controller. In other embodiments, addressing space may be flexibly adjusted to support ultra low-power operation with one or more of the memory segments. Still yet, internal DMA functionality may enable real-time mode switching
Referring now to
As described above, controller 16 utilizes control information to vary the levels of power provided by power supply 14.
In general, each memory segment or group of memory segments may have their own latency and data rate response. Along these lines, memory segment access may be individually controlled by using individual address space configurations. Referring to
In another embodiment shown in
This section will set forth various illustrative examples of different modes and adjustability of performance that the above-described teachings may provide. It is understood that the examples shown and described in conjunction with
Referring to
Referring to
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Referring to
In any of the embodiments described herein, an internal DMA unit may be provided to expedite block-to-block, or segment-to-segment data transfer. As indicated above, DMA enables rapid transitions between high-performance and low-power mode. An example of such a configuration is shown in
In implementation, the various modules described herein might be implemented as discrete modules, or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading this description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality.
While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.
