Claims
- 1. An improved inverted gate thin film transistor, the improvement comprising:
- a multilayer gate formed on an insulating substrate, said multilayer gate including a first refractory metal layer formed on said substrate, an aluminum layer formed on said first layer and a second refractory metal layer formed on said aluminum layer;
- said second refractory metal layer patterned to form said gate; and
- said aluminum layer anodized adjacent said gate to prevent step coverage problems in succeeding layers.
- 2. The improvement as defined in claim 1 including said first and second refractory metal layers formed from tantalum.
- 3. The improvement as defined in claim 1 including said aluminum layer formed from an aluminum alloy.
- 4. The improvement as defined in claim 1 including a dielectric layer formed on said second refractory metal layer.
- 5. The improvement as defined in claim 4 including said second refractory metal layer having an anodized surface.
- 6. An improved matrix, the improvement comprising:
- a multilayer line formed on an insulating substrate, said multilayer line including a first refractory metal layer formed on said substrate, an aluminum layer formed on said first layer and a second refractory metal layer formed on said aluminum layer;
- said second refractory metal layer patterned to form said line; and
- said aluminum layer anodized adjacent said line to prevent step coverage problems in succeeding layers.
- 7. The improvement as defined in claim 6 including said first and second refractory metal layers formed from tantalum.
- 8. The improvement as defined in claim 6 including said aluminum layer formed from an aluminum alloy.
- 9. The improvement as defined in claim 6 including a dielectric layer formed on said second refractory metal layer.
- 10. The improvement as defined in claim 9 including said second refractory metal layer having an anodized surface.
- 11. The improvement as defined in claim 6 including forming an active matrix display, including a plurality of non-linear control elements, each coupling a pixel to said line.
- 12. The improvement as defined in claim 11 including said control element being an inverted gate thin film transistor, with said line forming said gate.
- 13. The improvement as defined in claim 12 including a storage capacitor coupled between each said pixel and an adjacent row line.
- 14. The improvement as defined in claim 13 including said storage capacitor formed as a portion of said adjacent row or column line.
- 15. The improvement as defined in claim 14 including said storage capacitor formed from a portion of said adjacent row line, and said row line formed with said gate as a multilayer row line.
- 16. The improvement as defined in claim 12 including a dielectric layer formed over said second refractory layer and a metal oxide capacitor contact formed on said dielectric layer.
- 17. The improvement as defined in claim 16 including a metal oxide capacitor contact formed on said dielectric layer.
Parent Case Info
This application is a continuation of Application No. 08/618,597, Mar. 27, 1996, that issued as U.S. Pat. No. 5,731,216.
US Referenced Citations (4)
Continuations (1)
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Number |
Date |
Country |
Parent |
618597 |
Mar 1996 |
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