Performing a signal analysis based on digital samples in conjunction with analog samples

Abstract

Testing a device under test—DUT—includes providing a test signal from the DUT to a test probe, taking from the test signal being present at the test probe analog samples at a first sampling rate, taking from the test signal being present at the test probe digital samples at a second sampling rate, providing a control signal indicative of sampling times of the analog samples, and performing an analysis of the digital samples in conjunction with the control signal.

Description

BRIEF DESCRIPTION OF DRAWINGS

Other objects and many of the attendant advantages of the disclosed embodiments will be readily appreciated and become better understood by reference to the following more detailed description in connection with the accompanied drawings. Features that are substantially or functionally equal or similar will be referred to by the same reference signs.

FIG. 1 shows a block diagram of an embodiment of a device for testing a DUT with a sampling oscilloscope and A BERT by using a common test head according to the disclosed embodiments;

FIG. 2 shows a block diagram of an exemplary test head according to the disclosed embodiments; and

FIG. 3 shows exemplary circuitry of the test head according to the disclosed embodiments.

DETAILED DESCRIPTION

FIG. 1 shows a DUT 10, for example a high-speed digital communication system or device, a digital sampling oscilloscope 12 for digitally measuring and analyzing the course or waveform of a signal 20 of the DUT, a BERT (analyzer) 14 for determining the bit error rate of the signal 20, and a test head 16 for capturing data from a test signal 20. The test head 16 comprises a probe 28 which is electrically connectable to a test point, a pin or a wire line representing an output of the DUT 10 for capturing physical information of the signal 20.

The test head 16 takes analog samples of the signal 20 at a first sampling rate. For example the first sampling rate may be 10000 times lower than the second sampling rate. The test head 16 transmits an analog sampling signal 18 comprising a sequence of the analog samples 18 to the sampling oscilloscope 12 for further processing. The test head 16 further takes digital samples, at a second sampling rate e.g. similar to the bit rate of the test signal 20, and transmits a digital sampling signal 22 comprising a sequence of the digital samples to the BERT 14.

For taking the digital samples, a clock recovery might be performed from the received test signal 20. Alternatively, a separate clock signal (not shown) might be used for sampling. Due to the high second sampling rate, the digital sampling requires a high bandwidth. For the digital sampling as performed within a BERT, the sensitivity should be sufficiently high, since the high-speed signal 20 is sampled with at high sampling rates. However, due to the fact that the magnitude of the sampling pulses of the analog sampling is in the same range compared to the signal to be measured, the digital sampling is influenced by the analog sampling. Such influence might lead to a wrong digital comparison result that might lead to wrong BER results.

In order to avoid bit error ratio analysis errors in the BERT 14 caused by such interference due to the analog sampling, a first control signal 24 is transmitted from the sampling oscilloscope 12 to the BERT 14. In this case, the BERT 14 itself controls the processing of the digital samples 22 provided by the test head 16 using the first control signal 24. This alternative might be preferable, if the test head is part of the sampling oscilloscope 12.

Alternatively, a corresponding second control signal 26 is generated by the test head 16 and transmitted from the test head 16 to the BERT 14. In order to further control the provision of digital samples form the test head 16 to the BERT 14, a third control signal 25 might be provided from the sampling oscilloscope 12 to the test head 16.

Alternatively, the test head 16 provides a composed signal to the BERT 14, comprising the digital samples and control information of the control signal.

The control signals 24 or 26 are indicative of sampling times of the analog samples. Thereto, the control signals might be digital signal, e.g. having a lower bit rate compared to the digital sampling signal 22. The control signal might show a logical 1 when an analog sampling is activated and a logical 0 otherwise, or vice versa. A logical “1” of the control signal activates a switching process within the BERT 14; in other words, the control signal control a switching of the processing of the digital samples in the BERT 14.

The switching of the processing in the BERT 14 results in ignoring the digital samples in the BERT 14 or replacing the digital samples by predefined sampling values. When ignoring or replacing the digital samples, the BERT 14 replaces either entire words such as 128 bits or several consecutive bits of the received stream of bits representing the digital samples taken by the test head 16.

FIG. 2 shows the embodiment of a test head 16 in more detail. The test head 16 comprises an analog sampling circuitry 30, which is a diode sampling circuitry clocked at an analog sampling rate which is relatively low in the range of several kHz, and a digital sampling circuitry 32, which comprises a comparator for comparing the captured signal 20 with a threshold at the digital sampling rate. Furthermore, the test head 16 comprises a control circuit 34. The unit 34 serves for providing the control signal to be provided in conjunction with the digital samples 22 to the BERT 14 as will be explained in the following.

The control circuit 34 receives a control signal 24 from the sampling oscilloscope 12 when an analog sample is taken, or when a sampling pulse should be generated in the analog sampling circuitry 30 in order to take an analog sample 18. Alternatively, the control circuit 34 may also receive a control signal directly from the analog sampling circuitry 30 when an analog sample 18 is taken. Upon receipt of a control signal either from the sampling oscilloscope 12 or the analog sampling circuitry 30, the control circuit 34 generates and transmits a control signal 26 to the BERT 14 in order to control the processing of the digital samples 22 in the BERT 12. The control signal 26 causes the BERT 14 to switch the processing of the digital samples 22, as described above.

FIG. 3 shows details of exemplary sampling circuitries 30 and 32 which are connected at their inputs. The analog sampling circuitry 30 comprises a diode sampling circuitry. The diode sampling circuitry comprises two PN diodes D1 and D2 connected in series. The diode D1 is supplied at its positive connection with a current from a controlled current source I1. The diode D2 is supplied at its negative connection with a current from a controlled current source I2. The current sources I1 and I2 are controlled by the control circuit 34. The control unit 34 controls the current sources I1 and I2 such that for taking a sample the current sources I1 and I2 are switched such that a current may flow over the diodes D1 and D2. The intensity of the flowing current depends on the voltage at the connection of the two diodes D1 and D2. The voltage at the connection point is influenced by the signal from the DUT. The flowing current charges or discharges the capacitances C1 and C2. Therefore, the charges on the capacitances C1 and C2 represent the analog sample of the signal from the DUT taken at the time when the current sources I1 and I2 are switched on by the control unit 34. The charges on the capacitances C1 and C2 are converted by Analog to Digital (A/D) converters into digital values which are transmitted to the sampling oscilloscope as digital signals 18 for further processing.

The control circuit 34 receives the control signal 24 from the sampling oscilloscope as mentioned above. This control signal 24 is provided for generating the switching signals for the current sources I1 and I2. When the current sources I1 and I2 are switched on, a current spike occurs on the input of the digital and the analog sampling circuitry 30 and 32, respectively. Because the magnitude of the current spikes are in the range of the amplitude of the signal to be measured, this current spike significantly influences the digital sampling by the digital sampling circuitry 32, and, thus, may cause erroneous digital samples. In order to avoid a processing of these erroneous digital samples in the BERT, the control unit 34 generates the control signal 26 already mentioned above. This control signal 26 may be for example a digital signal which is activated when a analog sample is taken, i.e. the switching signals for the current sources I1 and I2 are generated. The control signal 26 is processed in the BERT and used for switching the processing of the digital samples 22 received by the BERT from the digital sampling circuitry 32.

The digital sampling circuitry 32 comprises a comparator 36. The signal from the DUT is guided to an input of the comparator 36 with an input impedance of 50 ohms matching the impedance of a typical connection line to the DUT and, therefore, avoiding reflections on the connection line which could influence the sampling. The other input of the comparator 36 is connected to a voltage source THRES generating a threshold voltage with which the input voltage from the DUT is compared. At its output, the comparator 36 generates a comparison signal of the two input voltages. This comparison signal is input to a Flip-flop 38 which is clocked with the data rate of the signal from the DUT. In order to generate the clock for the Flip-Flop 38, a clock recovery circuit 40 is provided which receives the signal from the DUT and generates a clock from this signal. The digital samples 22 of the signal from the DUT at the output of the Flip-Flop 38 are then transmitted to the BERT for further processing.

The disclosed embodiments allow for efficiently performing data analyses based on analog and digital samples by using a common test head for capturing the samples from the test signal. Furthermore, the embodiments allow for the performance of parallel measurements of the test signal, thereby mitigating the problem of electrical coupling effects between the digital sampling circuitry and the analog sampling circuitry on a logical level. This allows further integrating both the digital sampling circuitry and the analog sampling circuitry

Claims

1. A method for testing a device under test—DUT—comprising: providing a test signal from the DUT to a test probe,taking analog samples from the test signal being present at the test probe at a first sampling rate,taking digital samples from the test signal being present at the test probe at a second sampling rate,providing a control signal indicative of sampling times of the analog samples, andperforming an analysis of the digital samples in conjunction with the control signal.

2. The method of claim 1, wherein the control signal comprises an indication of selected samples of the digital samples having a certain time relation with respect to the analog samples, and wherein performing the analysis of the digital samples is carried out such that the selected samples does not have any effect to an analysis result.

3. The method of claim 2, wherein the selected samples of the digital samples are determined having same sampling times or sampling times falling within certain time windows around sampling times of the analog samples.

4. The method of claim 1, wherein the test result comprises a bit error ratio value indicative of a ratio of erroneous of samples of the digital samples except the selected samples to an overall number of evaluated samples.

5. The method of claim 1, the selected samples are one of: ignored, masked or replacing by predefined samples.

6. The method of claim 1, wherein the analog samples are converted into multi-bit values by performing an analog-to-digital conversion.

7. The method of claim 6, wherein the analog samples are provided to a first data analyzer for performing a waveform analysis, and wherein the digital samples and the control signal are provided to a second data analyzer for performing a bit error ratio analysis.

8. The method of claim 6, wherein the second data analyzer performs a process switching in response to the control signal comprising one of: ignoring selected samples, masking selected samples, or replacing selected samples with a predefined sample values.

9. The method of claim 1, wherein the digital samples and the control signal are provided as digital signals, and wherein the bits of the control signal have a first value if corresponding digital samples are to be processed and have a second value otherwise.

10. A test head for testing a device under test—DUT—, comprising a test probe adapted to be electrically connected to the DUT,an analog sampling circuitry adapted to take analog samples of a signal at a first sampling rate,a digital sampling circuitry adapted to take digital samples of the signal at a second sampling rate, anda control circuit adapted to provide a control signal indicative of a timing of the analog samples.

11. The test head of claim 10, wherein the control signal comprises an indication of selected samples of the digital samples having a certain time relation with respect to the analog samples.

12. The test head of claim 11, wherein the selected samples of the digital samples are determined having same sampling times or sampling times falling within certain time windows around sampling times of the analog samples.

13. The test head of claim 10, wherein the analog sampling circuitry comprises a series connection of two diodes, wherein each diode is connected to a controllable current source, the sampling control unit is adapted for controlling the switching of the current sources of the analog sampling circuitry in order to capture an analog sample of an input signal from the DUT, and wherein a capacitance is provided for storing the analog samples.

14. The sampling circuitry of claim 13, wherein the analog sampling circuitry comprises an analog-to-digital converter for converting the analog sample into multi-bit digital values.

15. The test head of claim 10, wherein the digital sampling circuitry comprising a comparator for comparing an input voltage with a threshold voltage to be provided to a sampling Flip-Flop for capturing corresponding comparison results in response to a clock signal associated to the input signal.

16. The test head of claim 15, further comprising a clock recovery circuit adapted for recovering a clock signal providing a trigger signal to the sampling of the Flip-Flop.

17. The test head of claim 10, comprising a first interface to be coupled to a first analyzer for transmitting the analog samples to the first data analyzer for performing a waveform analysis, and a second interface to be coupled to a second analyzer for transmitting the digital samples together with the control signal to the second data analyzer for performing a bit error ratio analysis.

18. A test apparatus for testing a device under test, comprising the test head of claim 10,an analog data analyzer adapted for performing an analysis based an the analog samples, anda digital data analyzer adapted for performing an analysis based on the digital samples in conjunction with the control signal.