Patent Application
20150149800
Embodiments relate to power management of a system, and more particularly to power management of a multicore processor.
Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, Ultrabooks™, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology).
It is known that power consumption is reduced by lowering an operating frequency at which a core runs. However, not only does reduced frequency reduce power consumption, it further reduces performance. Furthermore, very complicated procedures are involved in changing frequencies in a processor.
In various embodiments, a processor or other integrated circuit (IC) that includes various constituent agents can have an operating frequency dynamically controlled for each such agent using a single base operating frequency generated within the processor. More specifically, embodiments enable a processor to be provided with a single phase lock loop (PLL) or other single clock control logic. In turn, the generated clock signal from this unit, which may be at a given operating frequency, can then be dynamically controlled in each agent of the processor, independently and individually, such that the need for multiple PLL's or other clock control logic is avoided.
Furthermore, given that the agents forming a processor all may operate using a single clock control logic, complex clock crossing circuitry may be avoided at interfaces between such different units. More specifically, embodiments provide a processor that avoids the presence of certain buffer circuitry, referred to herein as a bubble generator first in first out buffer (BGF), that otherwise would be present as an interface between certain agents.
In this way, embodiments enable a processor to be designed that consumes reduced real estate and further operates at lower power consumption levels. Still further, performance may be enhanced as certain latencies in data traversal through clock crossing structures can be avoided.
Referring now to
As seen, processor 110 may be a single die processor including multiple cores 120a-120n. In addition, each core may be associated with an individual voltage regulator 125a-125n. Accordingly, an integrated voltage regulator (IVR) implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual core. As such, each core can operate at an independent voltage and frequency, enabling great flexibility and affording wide opportunities for balancing power consumption with performance. However, understand that embodiments apply equally to processors that operate with cores of a single operating voltage domain. To enable dynamic clock control, embodiments may provide for a single phase lock loop (PLL) 139 to generate a processor clock signal at a given operating frequency, which may be provided to independent agents of the processor to allow individual and independent operating frequency control internally in the agent, avoiding the need for multiple PLLs.
Still referring to
Also shown is a power control unit (PCU) 138, which may include hardware, software and/or firmware to perform power management operations with regard to processor 110. In various embodiments, PCU 138 may include logic to determine that a reduction in an operating frequency for one more units of a processor is desired, and to instruct such units to perform a clock reduction operation with low latency by squashing or restricting communication of clock signals to circuitry of the units, as described herein. Still further, PCU 138 may also include logic to cause the independent units to dynamically change operating frequency without presence of agent internal PLLs, reducing complexity and increasing performance.
While not shown for ease of illustration, understand that additional components may be present within processor 110 such as uncore logic, and other components such as internal memories, e.g., one or more levels of a cache memory hierarchy and so forth. Furthermore, while shown in the implementation of
Although the following embodiments are described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or processors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to any particular type of computer systems, and may be also used in other devices, such as handheld devices, systems on chip (SoCs), and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatus′, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatus′, and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a ‘green technology’ future, such as for power conservation and energy efficiency in products that encompass a large portion of the US economy.
Note that the dynamic clock control techniques described herein may be independent of and complementary to an operating system (OS)-based mechanism, such as the Advanced Configuration and Platform Interface (ACPI) standard (e.g., Rev. 3.0b, published Oct. 10, 2006). According to ACPI, a processor can operate at various performance states or levels, namely from P0 to PN. In general, the P1 performance state may correspond to the highest guaranteed performance state that can be requested by an OS. In addition to this P1 state, the OS can further request a higher performance state, namely a P0 state. This P0 state may thus be an opportunistic or turbo mode state in which, when power and/or thermal budget is available, processor hardware can configure the processor or at least portions thereof to operate at a higher than guaranteed frequency. In many implementations a processor can include multiple so-called bin frequencies above the P1 guaranteed maximum frequency, exceeding to a maximum peak frequency of the particular processor, as fused or otherwise written into the processor during manufacture. In addition, according to ACPI, a processor can operate at various power states or levels. With regard to power states, ACPI specifies different power consumption states, generally referred to as C-states, C0, C1 to Cn states. When a core is active, it runs at a C0 state, and when the core is idle it may be placed in a core low power state, also called a core non-zero C-state (e.g., C1-C6 states), with each C-state being at a lower power consumption level (such that C6 is a deeper low power state than C1, and so forth). In general, the clock control techniques described herein may be performed while a processor operates in an active state, e.g., a C0 state.
Referring now to
In general, clock generation circuit 220 is configured to receive the incoming clock and distribute it to various functional unit blocks of the processor. In some embodiments, clock generation circuit 220 may process the incoming clock signal, e.g., to modify its operating frequency for distribution to certain functional unit blocks. Or in other embodiments, clock generation circuit 220 may generally operate to simply distribute this incoming clock signal to various processor circuitry. According to various embodiments, clock generation circuit 220 includes a clock restriction logic 222 that receives a clock restriction command, e.g., from a PCU or other source (not shown for ease of illustration in
As further seen, clock generation circuit 220 also includes a dynamic clock logic 224 that is configured to receive other commands, e.g., from a PCU or other source, to dynamically control core clock frequency. More specifically, dynamic clock logic 224 may cause an operating frequency of the core to be dynamically modified. For example, in an embodiment upon reset or powering up from a low power state the PCU or other controller issues a first clock frequency command to cause the core to begin operating at an operating frequency corresponding to the operating frequency of the PLL, which may drive other circuitry of the processor such as an interconnect. Then after the reset or power up sequence is further completed, a second clock frequency command is received to cause the core to operate at a different operating frequency, e.g., a given multiple of the interconnect operating frequency. Of course, understand that depending on a level of busyness, a variety of incoming clock frequency commands can be received and used to dynamically control the core clock frequency.
To provide an appropriate clock signal to each of multiple functional units (FUBs) 22501-225nn, clock generation circuit 220 outputs one or more versions of the incoming clock signal to a plurality of global drivers 2300-230n. In general, each functional unit corresponds to a portion of the processor circuitry such as various front end units, execution units, and back end units such as retirement logic. Although in the particular example shown in
Referring now to
Nevertheless, to enable lower power operation with reduced latency, thus avoiding the need for stopping a core or performing other synchronization operations, using a clock restriction command in accordance with an embodiment, incoming clock signal A can be restricted, e.g., by removing clock cycles before it is distributed to at least certain logic of the processor. Thus as seen in
Referring now to
A processor including core 1200 may be a general-purpose processor, such as a Core™ i3, i5, i7, 2 Duo and Quad, Xeon™, Itanium™, XScale™ or StrongARM™ processor, which are available from Intel Corporation. Alternatively, the processor may be from another company, such as a design from ARM Holdings, Ltd, MIPS, etc. Or the processor may be a special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. The processor may be implemented on one or more chips, and may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.
As shown in
As further seen, clock generation circuit 1208 is also coupled to receive an incoming core clock frequency command signal, e.g., from a PCU (shown as a dynamic clock command signal). This signal may be used by clock generation circuit 1208 to dynamically modulate a received incoming clock signal from the PLL and transform it to an instructed operating frequency, e.g., a given multiple of this incoming clock signal. Further understand that this incoming clock frequency command may dynamically be changed to cause different operating frequencies to be generated, e.g., responsive to exit from reset or a low power state and then to provide a different (e.g., higher) operating frequency during an active state in which the processor is executing instructions.
As seen in
Coupled between front end units 1210 and execution units 1220 is an out-of-order (OOO) engine 1215 that may be used to receive the micro-instructions and prepare them for execution. More specifically OOO engine 1215 may include various buffers to re-order micro-instruction flow and allocate various resources needed for execution, as well as to provide renaming of logical registers onto storage locations within various register files such as register file 1230 and extended register file 1235. Register file 1230 may include separate register files for integer and floating point operations. Extended register file 1235 may provide storage for vector-sized units, e.g., 256 or 512 bits per register.
Different resources may be present in execution units 1220, including, for example, various integer, floating point, and single instruction multiple data (SIMD) logic units, among other specialized hardware. For example, such execution units may include one or more arithmetic logic units (ALUs) 1222, among other such execution units. As seen, execution units 1220 may provide a stall signal to core activity monitor 1260 upon a stall that occurs in one or more of the execution units, e.g., due to a lack of data needed for performing an operation.
Results from the execution units may be provided to a retirement unit 1240 including a reorder buffer (ROB). This ROB may include various arrays and logic to receive information associated with instructions that are executed. This information is then examined by retirement unit 1240 to determine whether the instructions can be validly retired and result data committed to the architectural state of the processor, or whether one or more exceptions occurred that prevent a proper retirement of the instructions. Of course, retirement unit 1240 may handle other operations associated with retirement.
As shown in
To provide an interface between core 1200 and other agents of a processor, an interface 1290 is provided. In an embodiment, interface 1290 may provide a mechanism to enable communication of data to and from other agents. In some implementations interface 1290 may include one or more buffers to temporarily store information prior to its communication from the core. Note that because in the implementations described herein core 1200 operates at either a common operating frequency with or at a clock multiple of an interconnect, the need for clock crossing logic such as a BGF interposed between circuitry of the core and other processor agents is avoided. Thus such buffers are simply controlled at the given operating frequency of the core clock signal. Furthermore, by way of clock generation circuit 1208, the need for a core-internal PLL also can be avoided.
While shown at this high level in the embodiment of
Thus in an embodiment, the single PLL of a processor may be implemented within uncore circuitry to enable the PLL to operate independently of core logic. This single PLL may be controlled, e.g., via a PCU or other logic, to generate a clock signal for distribution at a given operating frequency. The different agents of the processor may receive this clock signal and perform dynamic clock frequency changes as described herein. In an embodiment, a single voltage plane may provide a common operating voltage to all cores and an interconnect structure (e.g., a ring interconnect). However, using dynamic clock frequency control as described herein these different agents can operate at different operating frequencies.
In an embodiment in which all cores operate in a single domain, the PCU may select a core operating frequency (Core_f) based on a maximum P-state requested by any of the cores. For core-intensive workloads, the interconnect frequency may be controlled to be equal to the core operating frequency (CLR_f=Core_f). Instead, for a graphics-intensive workload, the interconnect frequency may be controlled to be equal to a maximum of a multiple of the graphics operating frequency or the core operating frequency (e.g., CLR_f=max(1.2*Graphics_F(GR_F) and (core_f))).
By removing a BGF and PLL (e.g., one each per core or other computing agent), reductions in area, power and complexity can be realized. For example, a typical BGF has a number of cycles of latency in both directions, which can impact performance. Further, by removing a PLL and BGF, area gains, lower dynamic capacitance, and improved floor plan with lower power delivery requirements can be realized. This is due in part, to the various operating voltages to be provided to PLLs and BGFs, when present. Still further, simplified low power state transitions can occur without these structures.
Thus different agents such as different cores may be controlled to operate at lesser ratios than a PLL ratio (e.g., a core may be controlled to run at 1/16 ratio of the PLL ratio). This dynamic clock frequency control maintains the functionality of independent operating frequencies between different processor agents such as a core and a ring interconnect.
Embodiments thus enable a PCU or other control logic to digitally control core operating frequency, allowing much faster and simpler frequency transitions. And with these simpler transitions, a reduced latency is realized before the core transitions to a new operating frequency. This is so, at least in part because there is no PLL or BGF reset to occur within a core, given the lack of these structures. Instead, when a core is to exit from a low power state (or on reset), a core begins operation at a current operating frequency of the processor (namely at the PLL operating frequency, which may correspond to the interconnect operating frequency). In an embodiment, the PCU may instruct the core to begin operation at this frequency via a command to cause core startup microcode to operate. Then, later in the reset sequence, the PCU sends an operating frequency command to the core to cause the core, via the internal clock generation circuit, to operate at a desired operating frequency, as described herein.
Note that frequency control logic of a PCU may initiate an indication to a processor core or other logic of a processor to enter into a clock reduction operation. For example, power consumption metrics such as current consumption, operating temperature, instruction execution rate, and operating voltage among many others are received in a power controller, e.g., a PCU. If a given core is close to reaching (or has reached) a processor constraint such as a thermal constraint, a current constraint or other such constraint, the PCU logic can instruct the core to restrict clock signals to one or more functional units. In an embodiment, this clock restriction control information may be communicated to the core as a command to instruct the core to immediately begin a clock restriction operation. Although this command may take many forms, in an embodiment the command includes a command portion to indicate a clock reduction instruction and a data portion that indicates the measure of clock reduction to be performed. As an example, the logic can send this data portion with a value that corresponds to the number of clock cycles that are to be restricted from being delivered to the core functional units. For example, a value of “1” indicates that a single clock cycle is to be restricted for every active clock cycle. Stated another way, a value of “1” corresponds to a duty cycle of 50% with respect to the incoming clock signal. Instead a value of “2” would indicate that two clock cycles are to be restricted for every active clock cycle for a duty cycle of 33%, and so on. Of course different encodings are possible in other embodiments. In one embodiment, to effect near instantaneous adoption of the clock reduction, this command can be communicated directly to clock generation circuitry of the core such as shown above in
Referring now to
When this command is received, microcode of the processor core for performing a power up sequence may be executed. As part of this microcode or separately within logic of the clock generation circuitry, the core may begin to operate using a clock signal at the first operating frequency (block 320).
Next at block 330 sometime during the power up sequence the PCU may issue a dynamic clock update command. At block 340 this command causes the clock generation circuitry to provide the clock signal at the second operating frequency to core circuitry. At this point, the power up sequence has operated to sufficiently power up circuitry of the core to enable an active state in which instruction execution for a given process may occur. Understand that while shown at this high level in the embodiment of
Referring now to
With further reference to
The clock control techniques described herein can be used in many different circumstances. For example, the PCU may instruct a clock restriction command when a processor constraint has been reached or is within a threshold of a constraint, as discussed above. Such constraints may include a thermal constraint so that the clock reduction operations can be used for purposes of thermal throttling. Note that this thermal throttling realized by the clock restriction operation can be performed without the need for interrupt operations, intra-die interrupt stop or lock operations or so forth. Another such constraint may be a current consumption constraint such that an ICCmax protection mechanism can be realized without the need to similarly perform complex operations to change a core clock frequency.
Still other embodiments may perform dynamic clock control operations outside of a power up event. For example, embodiments may perform dynamic clock operations to enable greater power to be delivered to other processor circuitry such as one or more graphics processors. When an interconnect that couples both to cores and to graphics processors seeks to provide more bandwidth for graphics operations of the graphics processors, clock control may be performed to enable greater bandwidth to the graphics processors, without the need for a changing a clock frequency provided to a core. This is particularly so in instances in which one or more cores and one of more graphics processors operate in these same domain, and thus at a single voltage. By enabling dynamic control of operating frequency within a core using a dynamic clock control technique as described herein, embodiments enable greater bandwidth and higher operating frequency for a graphics processor that operates in the same domain as the core.
Another instance for enabling clock control operations is to provide for a faster exit latency for one or more cores in a low power state. For example, assume one core is active in a turbo mode and thus is operating at a turbo mode frequency while another core is in a low power state, e.g., a C6 state. Instead of causing the active core to exit the turbo mode and lower its operating frequency using a complex process before allowing the second core to begin the low power exit, embodiments enable concurrent low power exit by the second core while at the same time performing clock restriction operations in the first core to thus enable a faster exit latency for the second core.
Embodiments can be implemented in processors for various markets including server processors, desktop processors, mobile processors and so forth. Referring now to
With further reference to
Referring now to
In general, each core 510 may further include low level caches in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a shared cache memory formed of a plurality of units of a last level cache (LLC) 5400-540n. In various embodiments, LLC 540 may be shared amongst the cores and the graphics engine, as well as various media processing circuitry. As seen, a ring interconnect 530 thus couples the cores together, and provides interconnection between the cores, graphics domain 520 and system agent circuitry 550. In one embodiment, interconnect 530 can be part of the core domain. However in other embodiments the ring interconnect can be of its own domain.
As further seen, system agent domain 550 may include display controller 552 which may provide control of and an interface to an associated display. As further seen, system agent domain 550 may include a power control unit 555 which can include a frequency control logic 559 in accordance with an embodiment of the present invention to dynamically control an operating frequency of the cores and other portions of the processor.
As further seen in
Referring to
In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
Physical processor 1100, as illustrated in
As depicted, core 1101 includes two hardware threads 1101a and 1101b, which may also be referred to as hardware thread slots 1101a and 1101b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor 1100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 1101a, a second thread is associated with architecture state registers 1101b, a third thread may be associated with architecture state registers 1102a, and a fourth thread may be associated with architecture state registers 1102b. Here, each of the architecture state registers (1101a, 1101b, 1102a, and 1102b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 1101a are replicated in architecture state registers 1101b, so individual architecture states/contexts are capable of being stored for logical processor 1101a and logical processor 1101b. In core 1101, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 1130 may also be replicated for threads 1101a and 1101b. Some resources, such as re-order buffers in reorder/retirement unit 1135, ILTB 1120, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 1115, execution unit(s) 1140, and portions of out-of-order unit 1135 are potentially fully shared.
Processor 1100 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In
Core 1101 further includes decode module 1125 coupled to fetch unit 1120 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 1101a, 1101b, respectively. Usually core 1101 is associated with a first ISA, which defines/specifies instructions executable on processor 1100. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic 1125 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, decoders 1125, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders 1125, the architecture or core 1101 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions.
In one example, allocator and renamer block 1130 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 1101a and 1101b are potentially capable of out-of-order execution, where allocator and renamer block 1130 also reserves other resources, such as reorder buffers to track instruction results. Unit 1130 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 1100. Reorder/retirement unit 1135 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.
Scheduler and execution unit(s) block 1140, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.
Lower level data cache and data translation buffer (D-TLB) 1150 are coupled to execution unit(s) 1140. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.
Here, cores 1101 and 1102 share access to higher-level or further-out cache 1110, which is to cache recently fetched elements. Note that higher-level or further-out refers to cache levels increasing or getting further away from the execution unit(s). In one embodiment, higher-level cache 1110 is a last-level data cache—last cache in the memory hierarchy on processor 1100—such as a second or third level data cache. However, higher level cache 1110 is not so limited, as it may be associated with or includes an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder 1125 to store recently decoded traces.
In the depicted configuration, processor 1100 also includes bus interface module 1105 and a power controller 1160, which may perform power sharing control in accordance with an embodiment of the present invention. Historically, controller 1170 has been included in a computing system external to processor 1100. In this scenario, bus interface 1105 is to communicate with devices external to processor 1100, such as system memory 1175, a chipset (often including a memory controller hub to connect to memory 1175 and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus 1105 may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.
Memory 1175 may be dedicated to processor 1100 or shared with other devices in a system. Common examples of types of memory 1175 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 1180 may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.
Note however, that in the depicted embodiment, the controller 1170 is illustrated as part of processor 1100. Recently, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor 1100. For example in one embodiment, memory controller hub 1170 is on the same package and/or die with processor 1100. Here, a portion of the core (an on-core portion) includes one or more controller(s) 1170 for interfacing with other devices such as memory 1175 or a graphics device 1180. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, bus interface 1105 includes a ring interconnect with a memory controller for interfacing with memory 1175 and a graphics controller for interfacing with graphics processor 1180. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory 1175, graphics processor 1180, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.
Embodiments may be implemented in many different system types. Referring now to
Still referring to
Furthermore, chipset 690 includes an interface 692 to couple chipset 690 with a high performance graphics engine 638, by a P-P interconnect 639. In turn, chipset 690 may be coupled to a first bus 616 via an interface 696. As shown in
Embodiments can be implemented in processors for various markets including server processors, desktop processors, mobile processors and so forth. Referring now to
In the high level view shown in
Each core unit 810 may also include an interface such as a bus interface unit to enable interconnection to additional circuitry of the processor. In an embodiment, each core unit 810 couples to a coherent fabric that may act as a primary cache coherent on-die interconnect that in turn couples to a memory controller 835. In turn, memory controller 835 controls communications with a memory such as a dynamic random access memory (DRAM) (not shown for ease of illustration in
In addition to core units, additional processing engines are present within the processor, including at least one graphics unit 820 which may include one or more graphics processing units (GPUs) to perform graphics processing as well as to possibly execute general purpose operations on the graphics processor (so-called GPGPU operation). In addition, at least one image signal processor 825 may be present. Signal processor 825 may be configured to process incoming image data received from one or more capture devices, either internal to the SoC or off-chip. Other accelerators may also be present. In the illustration of
Each of the units may have its power consumption controlled via a power manager 840. Power manager 840 includes control logic to determine appropriate operating voltage and frequency for each of the domains (and in some embodiments, sub-units of the domains), e.g., based on an available power budget and request for given performance and/or low power state.
In some embodiments, SoC 800 may further include a non-coherent fabric coupled to the coherent fabric to which various peripheral devices may couple. One or more interfaces 860a-860d enable communication with one or more off-chip devices. Such communications may be according to a variety of communication protocols such as PCIe™ GPIO, USB, I2C, UART, MIPI, SDIO, DDR, SPI, HDMI, among other types of communication protocols. Although shown at this high level in the embodiment of
The following examples pertain to further embodiments.
In one example, a processor comprises: a core to execute instructions, where the core includes a clock generation circuit to receive and distribute a first clock signal at a first operating frequency provided from a phase lock loop of the processor to a plurality of units of the core. The clock generation circuit may further include a dynamic clock logic to receive a dynamic clock frequency command and to cause the clock generation circuit to distribute the first clock signal to at least one of the units at a second operating frequency.
In an example, the clock generation circuit further includes a restriction logic to receive a restriction command and to cause the clock generation circuit to reduce delivery of the first clock signal to at least one of the plurality of units. The reduced delivery of the first clock signal may be at a lower frequency than the first operating frequency. The plurality of units include, in an example, a first subset of units to receive the first clock signal with the reduced delivery and a second subset of units to receive the first clock signal without restriction.
In an example, an interconnect is coupled to the core, where the interconnect is to operate using the first clock signal at the first operating frequency. An interface may directly couple the core to a system agent logic of the processor without interposition of clock crossing logic. The interface may operate according to the first clock signal, and may include a buffer to receive data according to the first clock signal at the second operating frequency and to output the data according to the first clock signal at the second operating frequency.
In an example, the processor further comprises a power control unit to generate the dynamic clock frequency command. The power control unit may issue a restriction command responsive to a low power state exit request for a second core, where the clock generation circuit is to reduce delivery of the first clock signal to at least one of the plurality of units without stopping the core, the first clock signal at a turbo mode frequency. In turn, the second core may begin the low power state exit concurrently with the reduced delivery of the first clock signal.
Note that the above processor can be implemented using various means.
In an example, the processor comprises a SoC incorporated in a user equipment touch-enabled device.
In another example, a system comprises a display and a memory, and includes the processor of one or more of the above examples.
In another example, a method comprises: receiving, from a phase lock loop of a processor, a clock signal at a first operating frequency in a clock generation circuit of a core of the processor; receiving a dynamic clock frequency command in dynamic clock logic of the core; determining an operating frequency based on the dynamic clock frequency command; controlling the clock generation circuit according to the determined operating frequency to drive the clock signal to at least one functional unit of the core at the determined operating frequency different than the first operating frequency; and communicating, from the core of the processor, data generated by the at least one functional unit to an agent of the processor, without interposition of a clock crossing circuit.
In another example, a computer readable medium including instructions is to perform the method of any of the above examples.
In another example, an apparatus comprises means for performing the method of any one of the above examples.
In an example, the method further comprises operating the core with the clock signal at the first operating frequency and thereafter operating the core with the clock signal at the determined operating frequency, without stopping the core. The method may further include receiving a clock restriction command from a power controller, when the core is operating within at least a threshold of at least one processor constraint, and controlling the clock generation circuit responsive to the clock restriction command to drive a restricted clock signal to the at least one functional unit.
In an example, the method further includes receiving the dynamic clock frequency command during a low power state exit for a second core, and controlling the clock generation circuit to drive a restricted clock signal to the at least one functional unit concurrently with the second core exit from the low power state.
In another example, a system comprises: a processor including a core having an execution unit and a clock generation logic. The clock generation logic may be configured to receive a clock signal at a first operating frequency from a phase lock loop of the processor and to dynamically adjust the first operating frequency of the clock signal responsive to a control signal to provide a core clock signal to a plurality of functional units of the core at an adjusted operating frequency. The processor may further include a PCU coupled to the core and including a first logic to determine the adjusted operating frequency and to communicate the control signal, and the phase lock loop to generate the clock signal and to provide the clock signal to a plurality of agents of the processor including the core and the PCU. In addition, the system may further include a DRAM coupled to the processor.
The phase lock loop is a single phase lock loop for the processor, in an example. In an example, the core includes an interface to directly couple to an interconnect without a clock crossing circuit. The core and the interconnect may be configured to operate at different frequencies. The core may exit a low power state and begin execution using the core clock signal at the first operating frequency during a first portion of the low power state exit, where the first operating frequency corresponds to an operating frequency of the interconnect. The first logic may thereafter cause the clock generation logic to dynamically adjust the clock signal to provide the core clock signal at the adjusted operating frequency during a second portion of the low power state exit.
Understand that various combinations of the above examples are possible.
Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.
Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
