BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a principle of the present invention;
FIG. 2 is a circuit diagram showing a synchronous detection circuit 10 according to a first embodiment;
FIG. 3 is a timing chart of the synchronous detection circuit 10 according to the first embodiment (part 1);
FIG. 4 is a timing chart of the synchronous detection circuit 10 according to the first embodiment (part 2);
FIG. 5 is a timing chart of the synchronous detection circuit 10 according to the first embodiment (part 3);
FIG. 6 is a circuit diagram showing a phase adjuster circuit la according to a second embodiment;
FIG. 7 is a timing chart of the phase adjuster circuit la according to the second embodiment;
FIG. 8 is a circuit diagram showing a phase adjuster circuit 1b according to a third embodiment;
FIG. 9 is a timing chart of the phase adjuster circuit 1b according to the third embodiment;
FIG. 10 is a circuit diagram showing a phase adjuster circuit 1c;
FIG. 11 is a timing chart of the phase adjuster circuit 1c shown in FIG. 10;
FIG. 12 is a circuit diagram showing a chopping wave amplitude control circuit 3c; and
FIG. 13 is a circuit diagram showing a synchronous detection circuit 100 according to a related art.