The present invention relates to a phase adjustment circuit of a sine wave.
At present, the sine wave plays an important role. In communication, the sine wave may be used for generating a carrier wave, or the sine wave may be used as a clock. In the communication, the clock is used not only as the carrier wave, but also as a timing reference for determining data.
When the clock is used as the timing reference for such data determination, it is necessary to adjust the phase of the clock and perform data determination at an appropriate timing. As a method for performing the data determination at an appropriate timing, there is clock data recovery. As means for realizing clock data recovery, a configuration using a phase comparator and a phase adjustment circuit is known. In this configuration, phases are compared by some means, and a desired phase is generated on the basis of the comparison result.
In the related art, as the phase adjustment circuit, a configuration disclosed in NPL 1 is known. A configuration of the phase adjustment circuit of the related art is shown in
α in Equation (1) is as follows:
In the configuration of
The present invention is made to solve above problem, and an object thereof is to provide a phase adjustment circuit that can be used in a wide range of frequencies.
A phase adjustment circuit of embodiments of the present invention includes: a clock generation unit configured to generate a sinusoidal clock signal; a delay unit configured to delay a signal output from the clock generation unit; a first multiplying unit configured to output a signal obtained by multiplying an amplitude of the signal output from the clock generation unit by a first constant; a second multiplying unit configured to output a signal obtained by multiplying the amplitude of the signal output from the delay unit by a second constant; and an adding unit configured to add the signal output from the first multiplying unit and the signal output from the second multiplying unit.
I In one configuration example of the phase adjustment circuit of the present invention, the first multiplying unit includes a first transistor in which a first control signal or a signal of a negative phase side of the clock signal of a differential type is input to a base or a gate, and a signal of a positive phase side is output from a collector or a drain; a second transistor in which a second control signal or a signal of a positive phase side of the clock signal of a differential type is input to a base or a gate, and a signal of a negative phase side is output from a collector or a drain; a third transistor in which the first control signal or the signal of the negative phase side of the clock signal of the differential type is input to a base or a gate, and the signal of the negative phase side is output from a collector or a drain; a fourth transistor in which the second control signal or the signal of the positive phase side of the clock signal of the differential type is input to a base or a gate, and the signal of the positive phase side is output from a collector or a drain; a fifth transistor in which the signal of the positive phase side of the clock signal of the differential type or the second control signal is input to a base or a gate, and a collector or a drain is connected to an emitter or a source of the first and second transistor; a sixth transistor in which the signal of the negative phase side of the clock signal of the differential type or the first control signal is input to a base or a gate, and a collector or a drain is connected to emitters or sources of the third and fourth transistors; a seventh transistor in which a bias voltage is applied to a base or a gate; a first resistor which has one end connected to a power supply voltage, and the other end connected to the collector or the drain of the first and fourth transistors; a second resistor which has one end connected to the power supply voltage, and the other end connected to the collector or the drain of the second and third transistors; a third resistor which has one end connected to an emitter or a source of the fifth transistor, and the other end connected to a collector or a drain of the seventh transistor; a fourth resistor which has one end connected to an emitter or a source of the sixth transistor, and the other end connected to the collector or the drain of the seventh transistor; and a fifth resistor which has one end connected to an emitter or a source of the seventh transistor, and the other end connected to ground. The second multiplying unit includes an eighth transistor in which a third control signal or a signal of a negative phase side signal of the differential signal output from the delay unit is input to a base or a gate, and a signal of a positive phase is output from a collector or a drain; a ninth transistor in which a fourth control signal or a signal of a positive phase signal of the differential signal output from the delay unit is input to a base or a gate, and a signal of a negative phase is output from a collector or a drain; a tenth transistor in which the third control signal or the signal of the negative phase side signal of the differential signal output from the delay unit is input to a base or a gate, and the signal of the negative phase side is output from a collector or a drain; an eleventh transistor in which the fourth control signal or the signal of the positive phase signal of the differential signal output from the delay unit is input to a base or a gate, and the signal of the positive phase is output from a collector or a drain; a twelfth transistor in which the signal of the positive phase side of the differential signal output from the delay unit or the fourth control signal is input to a base or a gate, and a collector or a drain is connected to an emitter or a source of the eighth and ninth transistors; a thirteenth transistor in which the signal of the negative phase side of the differential signal output from the delay unit or the third control signal is input to a base or a gate, and a collector or a drain is connected to an emitter or a source of the tenth and eleventh transistors; a fourteenth transistor in which a bias voltage is applied to a base or a gate; a sixth resistor which has one end connected to the power supply voltage, and the other end connected to a collector or a drain of the eighth and eleventh transistors; a seventh resistor which has one end connected to the power supply voltage, and the other end connected to the collector or the drain of the ninth and tenth transistors; an eighth resistor which has one end connected to an emitter or a source of the twelfth transistor, and the other end connected to a collector or a drain of the fourteenth transistor; a ninth resistor which has one end connected to an emitter or a source of the thirteenth transistor, and the other end connected to the collector or the drain of the fourteenth transistor; and a tenth resistor which has one end connected to an emitter or a source of the fourteenth transistor, and the other end connected to ground.
Further, in one configuration example of the phase adjustment circuit of the present invention, the adding unit includes a fifteenth transistor in which the signal of the negative phase side of the differential signal output from the first multiplying unit is input to a base or a gate, and the signal of the positive phase side is output from a collector or a drain; a sixteenth transistor in which the signal of the positive phase side of the differential signal output from the first multiplying unit is input to a base or a gate, and the signal of the positive phase side is output from a collector or a drain; a seventeenth transistor in which the signal of the positive phase side of the differential signal output from the second multiplying unit is input to a base or a gate, and the signal of the negative phase side is output from a collector or a drain; an eighteenth transistor in which the signal of the negative phase side of the differential signal output from the second multiplying unit is input to a base or a gate, and the signal of the positive phase side is output from a collector or a drain; nineteenth and twentieth transistors in which a bias voltage is applied to a base or a gate; an eleventh resistor which has one end connected to the power supply voltage, and the other end connected to a collector or a drain of the fifteenth and eighteenth transistors; a twelfth resistor which has one end connected to the power supply voltage, and the other end connected to a collector or a drain of the sixteenth and seventeenth transistors; a thirteenth resistor which has one end connected to an emitter or a source of the fifteenth transistor, and the other end connected to a collector or a drain of the nineteenth transistor; a fourteenth resistor which has one end connected to an emitter or a source of the sixteenth transistor, and the other end connected to the collector or the drain of the nineteenth transistor; a fifteenth resistor which has one end connected to an emitter or a source of the seventeenth transistor, and the other end connected to a collector or a drain of the twentieth transistor; a sixteenth resistor which has one end connected to an emitter or a source of the eighteenth transistor, and the other end connected to the collector or the drain of the twentieth transistor; a seventeenth resistor which has one end connected to an emitter or a source of the nineteenth transistor, and the other end connected to ground; and an eighteenth resistor which has one end connected to an emitter or a source of the twentieth transistor, and the other end connected to ground.
Further, in one configuration example of the phase adjustment circuit of the present invention, the first and second multiplying units and the adding unit are configured to include a first transistor in which the first control signal or the signal of the negative phase side of the clock signal of the differential type is input to a base or a gate, and the signal of the positive phase side is output from a collector or a drain; a second transistor in which the second control signal or the signal of the positive phase side of the clock signal of the differential type is input to a base or a gate, and the signal of the negative phase side is output from a collector or a drain; a third transistor in which the first control signal or the signal of the negative phase side of the clock signal of the differential type is input to a base or a gate, and the signal of the negative phase side is output from a collector or a drain; a fourth transistor in which the second control signal or the signal of the positive phase side of the clock signal of the differential type is input to a base or a gate, and the signal of the positive phase side is output from a collector or a drain; a fifth transistor in which the signal of the positive phase side of the clock signal of the differential type or the second control signal is input to a base or a gate, and a collector or a drain is connected to emitters or sources of the first and second transistors; a sixth transistor in which the signal of the negative phase side of the clock signal of the differential type or the first control signal is input to a base or a gate, and a collector or a drain is connected to emitters or sources of the third and fourth transistors; a seventh transistor in which a bias voltage is applied to a base or a gate; an eighth transistor in which a third control signal or the signal of the negative phase side of the differential signal output from the delay unit is input to a base or a gate, and the signal of the positive phase side is output from a collector or a drain; a ninth transistor in which a fourth control signal or the signal of the positive phase side of the differential signal output from the delay unit is input to a base or a gate, and the signal of the negative phase side is output from a collector or a drain; a tenth transistor in which the third control signal or the signal of the negative phase side of the differential signal output from the delay unit is input to a base or a gate, and the signal of the negative phase side is output from a collector or a drain; an eleventh transistor in which the fourth control signal or the signal of the positive phase side of the differential signal output from the delay unit is input to a base or a gate, and the signal of the positive phase side is output from a collector or a drain; a twelfth transistor in which the signal of the positive phase side of the differential signal output from the delay unit or the fourth control signal is input to a base or a gate, and a collector or a drain is connected to the emitters or sources of the eighth and ninth transistors; a thirteenth transistor in which the signal of the negative phase side of the differential signal output from the delay unit or the third control signal is input to a base or a gate, and a collector or a drain is connected to the emitters or sources of the tenth and eleventh transistors; a fourteenth transistor in which a bias voltage is applied to a base or a gate; a first resistor which has one end connected to the power supply voltage, and the other end connected to the collectors or drains of the first, fourth, eighth and eleventh transistors; a second resistor which has one end connected to the power supply voltage, and the other end connected to the collectors or drains of the second, third, ninth and tenth transistors; a third resistor which has one end connected to an emitter or a source of the fifth transistor, and the other end connected to a collector or a drain of the seventh transistor; a fourth resistor which has one end connected to an emitter or a source of the sixth transistor, and the other end connected to the collector or the drain of the seventh transistor; a fifth resistor which has one end connected to an emitter or a source of the seventh transistor, and the other end connected to ground; a sixth resistor which has one end connected to an emitter or a source of the twelfth transistor, and the other end connected to a collector or a drain of the fourteenth transistor; a seventh resistor which has one end connected to an emitter or a source of the thirteenth transistor, and the other end connected to the collector or the drain of the fourteenth transistor; and an eighth resistor which has one end connected to an emitter or a source of the fourteenth transistor, and the other end connected to ground.
One configuration example of the phase adjustment circuit of the present invention includes a plurality of delay units having different delay amounts, and further includes a switch which is inserted between the plurality of delay units and the second multiplying unit and configured to select any one output of the plurality of delay units.
One example of the configuration of the phase adjustment circuit of the present invention further includes a level adjusting unit configured to perform an amplitude adjustment of the signal output from the adding unit.
According to embodiments of the present invention, by providing a clock generation unit, a delay unit, first and second multiplying units and an adding unit, it is not necessary to use a conventional Quadrature-VCO as a clock generation unit, and an LC-VCO made up of a general LC oscillator can be used as the clock generation unit. In addition, the present invention can be used in a wide range of frequencies, unlike a configuration in which a 90-degree hybrid is used as the clock generation unit.
Referring to the drawings, a description will be given of examples of the present invention.
In this example, by adding a sine wave sin ωt serving as a reference and a sine wave sin (ωt+φ) having a phase different by φ at an arbitrary magnification, an arbitrary waveform can be generated. That is, an output signal OUT of the adding unit 7 is expressed by the following Equation.
In Equation (3), ejωt represents a reference sin wave. It can be seen from Equation (3) that the sin wave having the reference frequency and the sin wave having the phase different by ρ from the reference phase can be generated, by adding the sin wave having the reference frequency and the sin wave having arbitrary phase different by φ.
A detailed description will be given below. Since the amount of change in the output phase may be calculated by calculating rejρ, when rearranging Equation (3), the following Equation is obtained.
From Equation (4), the phase angle ρ is given by Equation (5).
A value range when the phase angle ρ is controlled by the amplitudes A and B is considered. Although the range of the output amplitudes A and B on the circuit is finite with o as the center, since A and B are independent, x=A/BE [−∞,+∞], and an arbitrary real number can be selected as the amplitudes A and B. The sign of x can be determined by the combination of the signs of the amplitudes A and B, and the denominator B can be reduced as much as possible to increase the value of x.
Further, when y=x+cos (φ), y=(A/B)+cos (φ)∈[−∞,+∞] is clearly expressed. Therefore, ρ=arg (x+cos (φ)+j sin (φ))=arg (y+j sin (φ)) can take a value of 0 to π [rad] under conditions of sin (φ)≠0. It is also clear that ρ=arg (x+cos (φ)+j sin (φ))=arg (y+j sin (φ)) can take −π to 0 [rad], assuming that the polarity of B is reversed. That is, according to this example, a signal in which an input sine wave is adjusted to an arbitrary phase can be output.
Although there are many methods for realizing the delay unit 4, the delay unit 4 may be realized by, for example, propagation delay of wiring. In particular, a transmission line may be used as a wiring for realizing the delay unit 4 to cope with a high frequency. The type and structure of the transmission line are not limited. A coplanar line or a microstrip line may be used as the transmission line.
Further, as the delay unit 4, an arbitrary number of amplifiers may be cascade-connected. Further, the delay unit 4 may be realized by a lumped constant element. For example, the delay unit 4 can be realized by an LCR resonance circuit. Further, the delay unit 4 may be realized by combining the wiring, the amplifier, and the lumped constant element.
Although a sine wave sin (ωt+φ) having a phase different from that of the sine wave sin ωt by φ can be generated by the delay amount of the delay unit 4, in the case of φ=πn (n is an arbitrary integer), a phase adjustment cannot be realized because no phase difference occurs between sin ωt and sin (ωt+φ). That is, at the time of φ=π, the sign of B is only changed without the phase difference only by −sin.
Therefore, as shown in
The plurality of delay units 4-1 and 4-2 having different delay amounts may be realized by changing the length of a transmission line or by changing the number of stages of amplifiers cascade-connected.
Although the number of delay units 4-1 and 4-2 is two in the example of
In the range of 0<|φ|<π, it is apparent that a phase difference occurs between sin ωt and sin (ωt+Q). Therefore, by designing the delay unit 4 to satisfy 0<|φ|<π at the assumed maximum frequency of the sine wave to be a target of the phase adjustment in the phase adjustment circuit of this example, an arbitrary phase difference can be realized without switching the delay amount. When 0<|φ|<π is satisfied, since the delay amount of the delay unit 4 can be minimized, the circuit area, cost and power consumption can be reduced.
Gilbert cells can be used as the multiplying units 5 and 6. As shown in
An amplification factor (the amplitude A) of the multiplying unit 5 can be controlled by a voltage difference between the control signals IN1p and IN1n.
The configuration of the multiplying unit 6 is the same as that of the multiplying unit 5. In the case of the multiplying unit 6, differential signals IN2p and IN2n output from the delay unit 4 or the switch 8 are input to transistors Q5 and Q6. The amplification factor (the amplitude B) of the multiplying unit 6 can be controlled by the voltage difference between the control signals IN1p and IN1n.
In the Gilbert cell, (IN1p−In1n)×(IN2p−In2n) obtained by multiplying (IN1p−In1n) and (IN2p−In2n) becomes an output (OUT1p−OUT1n) in terms of the structure. Therefore, the differential signals output from the buffer unit 2, the delay unit 4 and the switch 8 are allocated to IN1p and IN1n, IN2p and IN2n may be used as control signals.
As the adding unit 7, a current mode logic (CML) block of a current addition base can be used. As shown in
Further, by combining the Gilbert cell and the CML, a configuration in which the multiplying units 5 and 6 and the adding unit 7 are integrated may be realized. This configuration includes, as shown in
The amplification factor (the amplitude A) of the multiplying unit 5 can be controlled by the voltage difference between the control signals IN1p and IN1n, and the amplification factor (the amplitude B) of the multiplying unit 6 can be controlled by the voltage difference between the control signals IN3p and IN3n. Further, as described in
With the configuration shown in
In the configurations of
Although an example in which a bipolar transistor is used as the transistors Q1 to Q27 is shown in
Further, a resistor or a capacitor for gain adjustment and frequency response adjustment may be inserted into the emitter or the source of the transistor, or both of the resistor and the capacitor may be inserted into the emitter or the source of the transistor. In addition, an arbitrary amplification circuit such as an emitter follower may be provided as necessary for level adjustment or the like.
Next, a description will be given of a second example of the present invention.
The output amplitude of the phase adjustment circuit according to the present invention changes in principle in accordance with the adjusted phase. For this reason, the level adjusting unit 9 may be provided to correspond to the varying output amplitude. As the level adjusting unit 9, there is a variable gain amplifier (VGA) capable of adjusting the output amplitude or an automatic gain control (AGC) circuit for automatically adjusting the output amplitude. The configuration of the VGA and the AGC circuit is not limited. When the AGC circuit is used, a peak detector or a power detector is connected to the output terminal (the output terminal of the adding unit 7) of the phase adjustment circuit, and the detection result is fed back to the amplifier to adjust the gain.
The present invention can be applied to the technique of adjusting the phase of a sine wave.
This application is a national phase entry of PCT Application No. PCT/JP2021/046504, filed on Dec. 16, 2021, which application is hereby incorporated herein by reference.
Filing Document | Filing Date | Country | Kind |
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PCT/JP2021/046504 | 12/16/2021 | WO |