Patent Grant
10999049
This disclosure relates to the phase and frequency control of an oscillator in a clock-data recovery circuit. More particularly, this disclosure relates to a structure and method for phase and frequency control of an injection-locked oscillator in a clock-data recovery circuit, which may be used in a receiver of a short-reach data link.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Short-reach data links are sometimes used for chip-to-chip communication when a reliable serial interface using low power at high speed is required. For example, as smaller semiconductor process nodes are developed, the cost of semiconductor devices increases. Therefore, there is an increasing prevalence of electronic devices that include multiple interconnected chips. In some cases, a more advanced process node is used only in an integrated circuit chip on which functions that require fast processing and high power consumption are implemented. Conversely, other less demanding features, such as legacy input/output features and other peripheral features, can be implemented on one or more integrated circuit chips at an older process node. The separate integrated circuit chips are then interconnected using one or more short-reach data links.
One advantage of a short-reach data link is low channel loss (˜−12 dB). With such low channel loss, injection-locked oscillator-based (ILO-based) clock-data recovery (CDR) is practical. However, for ILO-based CDR to function correctly, the ratio of the oscillator free-running frequency (FRF) to the data rate must be kept constant.
In accordance with implementations of the subject matter of this disclosure, a method of controlling at least one of phase and free-running frequency of an injection-locked oscillator in a clock-data recovery circuit includes, on occurrence of a first data pattern in an input data signal, measuring the input data signal at a first clock edge to determine a first data phase measurement value, measuring the input data signal at clock centers immediately preceding and immediately following the first clock edge to determine second and third data phase measurement values, and based on first predetermined relationships among the first, second and third data phase measurement values, adjusting a variable data path delay to correct phase.
In a first implementation of such a method, the first data pattern in the input data signal is indicative of saturation of inter-symbol interference in the input data signal.
A first variant of that first implementation may further include, on occurrence of a second data pattern in the input data signal, measuring the input data signal at a second clock edge to determine a first data frequency measurement value, measuring the input data signal at clock centers immediately preceding and immediately following the second clock edge to determine second and third data frequency measurement values, and based on second predetermined relationships among the first, second and third data frequency measurement values, adjusting the free-running frequency output of the injection-locked oscillator to correct frequency.
In that first variant, the second data pattern in the input data signal may be indicative of saturation of inter-symbol interference in the input data signal for a predetermined minimum duration. The first data pattern may include a first predetermined number of repetitions of data pulses all having a first bit value, followed by at least two data pulses both having a second bit value opposite the first bit value, and in the first predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, equal to the second bit value may indicate that adjusting the variable data path delay is unnecessary. In the first predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, equal to the first bit value may indicate that adjusting the variable data path delay is necessary according to the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge, and the variable data path delay is advanced when the input signal at the second clock edge and the input signal at the clock center immediately following the second clock edge have different bit values, and the variable data path delay is retarded when the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge both have the second bit value.
The second data pattern may include a second predetermined number of repetitions of data pulses all having a first bit value, followed by at least two data pulses both having a second bit value opposite the first bit value, and in the second predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, equal to the second bit value indicates that adjusting the free-running frequency output of the injection-locked oscillator is unnecessary. In the second predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, equal to the first bit value may indicate that adjusting the free-running frequency output of the injection-locked oscillator is necessary according to the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge, and the free-running frequency output of the injection-locked oscillator is advanced when the input signal at the second clock edge and the input signal at the clock center immediately following the second clock edge have different bit values, and the free-running frequency output of the injection-locked oscillator is retarded when the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge both have the second bit value. The second predetermined number of repetitions of data pulses all having the first bit value may be larger than the first predetermined number of repetitions of data pulses all having the first bit value.
In a second implementation of such a method, the first data pattern may include a first predetermined number of repetitions of data pulses all having a first bit value, followed by at least two data pulses both having a second bit value opposite the first bit value, and in the first predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, equal to the second bit value may indicate that adjusting the variable data path delay is unnecessary.
In a first variant of that second implementation, in the first predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, equal to the first bit value may indicate that adjusting the variable data path delay is necessary according to the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge, and the variable data path delay is advanced when the input signal at the second clock edge and the input signal at the clock center immediately following the second clock edge have different bit values, and the variable data path delay is retarded when the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge both have the second bit value.
A clock-data recovery circuit according to implementations of the subject matter of this disclosure includes a variable data path delay, an injection-locked oscillator having a free-running frequency, and circuitry for adjusting at least one of the variable data path delay and the free-running frequency, the circuitry for adjusting at least one of the variable data path delay and the free-running frequency including a counter configured to count repetitions of a bit value in an input data signal, the circuitry for adjusting the at least one of the variable data path delay and the free-running frequency further being configured to, on occurrence of a first data pattern in the input data signal, indicative of saturation of inter-symbol interference, measure the input data signal at a first clock edge to determine a first data phase measurement value, measure the input data signal at clock centers immediately preceding and immediately following the first clock edge to determine second and third data phase measurement values, and based on first predetermined relationships among the first, second and third data phase measurement values, adjust the variable data path delay to correct phase.
In a first implementation of such a clock-data recovery circuit, the circuitry for adjusting at least one of the variable data path delay and the free-running frequency may be further configured to, on occurrence of a second data pattern in the input data signal, the second data pattern being indicative of saturation of inter-symbol interference in the input data signal for a predetermined minimum duration, measure the input data signal at a second clock edge to determine a first data frequency measurement value, measure the input data signal at clock centers immediately preceding and immediately following the second clock edge to determine second and third data frequency measurement values, and based on second predetermined relationships among the first, second and third data frequency measurement values, adjust the free-running frequency output of the injection-locked oscillator to correct frequency.
In a first variant of the first implementation, the first data pattern may include a first predetermined number of repetitions of data pulses all having a first bit value, followed by at least two data pulses both having a second bit value opposite the first bit value, and the circuitry for adjusting at least one of the variable data path delay and the free-running frequency is further configured to not adjust the variable data path delay when in the first predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, is equal to the second bit value.
According to that first variant, in the first predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, equal to the first bit value may indicate that adjusting the variable data path delay is necessary according to the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge, and the circuitry for adjusting the at least one of the variable data path delay and the free-running frequency advances the variable data path delay when the input signal at the second clock edge and the input signal at the clock center immediately following the second clock edge have different bit values, and the circuitry for adjusting the at least one of the variable data path delay and the free-running frequency retards the variable data path delay when the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge both have the second bit value.
The second data pattern may include a second predetermined number of repetitions of data pulses all having a first bit value, followed by at least two data pulses both having a second bit value opposite the first bit value, and in the second predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, equal to the second bit value indicates that adjusting the free-running frequency output of the injection-locked oscillator is unnecessary. In the second predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, equal to the first bit value may indicate that adjusting the free-running frequency output of the injection-locked oscillator is necessary according to the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge, and the circuitry for adjusting the at least one of the variable data path delay and the free-running frequency advances the free-running frequency output of the injection-locked oscillator when the input signal at the second clock edge and the input signal at the clock center immediately following the second clock edge have different bit values, and the circuitry for adjusting the at least one of the variable data path delay and the free-running frequency retards the free-running frequency output of the injection-locked oscillator when the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge both have the second bit value. The second predetermined number of repetitions of data pulses all having the first bit value may be larger than the first predetermined number of repetitions of data pulses all having the first bit value.
In a second implementation of a clock-data recovery circuit, the first data pattern may include a first predetermined number of repetitions of data pulses all having a first bit value, followed by at least two data pulses both having a second bit value opposite the first bit value, and the circuitry for adjusting the at least one of the variable data path delay and the free-running frequency is further configured to not adjust the variable data path delay when in the first predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, is equal to the second bit value.
In that implementation, in the first predetermined relationships, a value of the input data signal, at the clock center immediately preceding the second clock edge, equal to the first bit value may indicate that adjusting the variable data path delay is necessary according to the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge, and the circuitry for adjusting the at least one of the variable data path delay and the free-running frequency advances the variable data path delay when the input signal at the second clock edge and the input signal at the clock center immediately following the second clock edge have different bit values, and the circuitry for adjusting the at least one of the variable data path delay and the free-running frequency retards the variable data path delay when the value of the input signal at the second clock edge and the value of the input signal at the clock center immediately following the second clock edge both have the second bit value.
Further features of the disclosure, its nature and various advantages, will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:
As noted above, short-reach data links are suitable for use between different integrated circuit chips under certain circumstances, such as when different parts of a system are implemented on different integrated circuit chips. As further noted above, low channel loss in a short-reach data link allows the use of ILO-based CDR. However, for ILO-based CDR to function correctly, the ratio of the free-running frequency (FRF) of the injection-locked oscillator to the data rate must be kept constant. Otherwise, large FRF error resulting from PVT drift (particularly temperature changes) will reduce tracking performance and make it difficult to support a data pattern with a long run of consecutive identical digits (CIDs).
Some known ILO-based CDR solutions use a phase-locked loop (PLL) along with the ILO for frequency tracking. However, such a solution requires substantial additional die area and increases power consumption.
Other known ILO-based CDR solutions use a phase detector (PD) to estimate the FRF error. The falling edge of the data is used for injection, and the rising edge of the data is used for FRF error sampling. However, the residual phase error sampled by the phase detector includes three components:
ΔPtot=ΔPFRF
where ΔPtot is the total phase difference, ΔPFRF_ERR is the integral of the FRF error, ΔPDCD is the duty cycle distortion of the data, plus the sampling setup time difference between the rising edge and the falling edge, and ΔPISI is the inter-symbol interference (ISI) between the injection data edge and the FRF error sampling data edge. Because the phase difference includes components other than the FRF error, poor FRF tracking accuracy may result from using phase detection to measure the FRF error. Such an implementation may be able to support, for example, a PRBS9 8-bit/10-bit pattern, but cannot support, for example, a random data pattern with a long run of CIDs.
In accordance with implementations of the subject matter of this disclosure, FRF error is more accurately measured by measuring not only the phase error at a data edge, but also the data before and after the edge. This makes use of an injection-locked oscillator in applications such as, but not limited to, a short-reach data link, practical.
Measuring phase error at the same edge eliminates the duty-cycle distortion portion of the phase error. Variation based on the inter-symbol interference portion of the phase error is reduced or eliminated by measuring phase error only when inter-symbol interference is saturated.
Specifically, phase updates are performed by measuring phase error only after a number, M, of identical data pulses—followed by at least two opposite data pulses (i.e., M zeroes followed by 2 ones or M ones followed by two zeroes). The number, M, depends on the channel characteristics and is set to ensure that inter-symbol interference is saturated. Frequency updates are performed by measuring phase error only after a larger number M+N, of identical data pulses—followed by at least two opposite data pulses (i.e., M+N zeroes followed by 2 ones or M+N ones followed by two zeroes).
According to implementations of the subject matter of this disclosure, three measurements are taken at the nominal location of a data edge in the input data signal, as determined by the injection-locked oscillator. The three measurements are taken on the nominal data edge (i.e., on the clock edge), and at the nominal centers of the preceding and following unit intervals. Based on the states of those three signals, the oscillator frequency is advanced or retarded.
An implementation of the subject matter of this disclosure is described with reference to
Two integrated circuit devices, each incorporating a respective transceiver 100, and connected by a short-reach data link incorporating implementations of the subject matter of the present disclosure are shown in
Receiver 101 receives an (N+1)-bit signal 123 on channel 103, and recovers data 121. Receiver 101 does not need a clock/frequency signal from clock standard circuit 112 because receiver 101 recovers the clock from signal 123 as part of the ILO-based CDR process.
An implementation 200, according to the subject matter of the present disclosure, of a receiver 101 is shown in
ILO 220 may in some implementations have the structure 300 seen in
As noted above, to achieve a stable lock for ILO-based CDR requires that the free-running frequency of the ILO 220 be kept as close as possible to the clock of the incoming data. Data sampler 221 and edge sampler 222 together function as a bang-bang phase detector (BBPD) whose outputs are used both to advance or retard ILO 220 to control frequency, and to advance or retard a variable data path delay 230 to control phase, as described below. In the implementation shown, data sampler 221 is actually a plurality of data samplers because there may be a plurality of parallel data inputs. Similarly, edge sampler 222 is actually a plurality of edge samplers. The outputs of data sampler 221 and edge sampler 222 are demultiplexed by demultiplexer 223 and input into Pattern Detection Phase/Frequency Control module 240. Data sampler 221 and edge sampler 222 are clocked, respectively, by data clock output 224 of ILO 220 and edge clock output 225 of ILO 220. Data clock output 224 also is divided at 226 to provide a system clock 227.
One possible implementation 400 of Pattern Detection Phase/Frequency Control module 240 is shown in
Phase control activation signal 411 activates phase control logic 402, which sends a phase control or update signal 412 to advance or retard variable data path delay 230 depending on the comparison of the value of DIN signal 211 at a clock edge and at the clock centers preceding and following that clock edge. If the M consecutive identical bits, followed by two opposite bits, are M zeroes followed by two ones, then phase control or update signal 412 is determined in this implementation as follows:
where:
If the M consecutive identical bits, followed by two opposite bits, are M ones followed by two zeroes, then phase control or update signal 412 is determined as follows:
Frequency control activation signal 421 activates frequency control logic 403, which sends a frequency control or update signal 413 via digital-to-analog converter 241 to advance or retard ILO 220 depending on the comparison of the value of DIN signal 211 at a clock edge and at the clock centers preceding and following that clock edge. If the M+N consecutive identical bits, followed by two opposite bits, are M+N zeroes followed by two ones, then frequency control or update signal 413 is determined as follows:
where:
If the M+N consecutive identical bits, followed by two opposite bits, are M+N ones followed by two zeroes, then frequency control or update signal 413 is determined as follows:
Either or both of phase control logic 402 and frequency control logic 403 may be a programmable device such as a microprocessor or microcontroller programmed to implement the logic described above. Alternatively, either or both of phase control logic 402 and frequency control logic 403 may be a look-up table or set of look-up tables in which the values of three inputs representing DC[K], DE[K] and DC[K+1] select the appropriate phase control or update signal 412 or frequency control or update signal 413 in accordance with the tables presented above.
One implementation 500 of a method of operation of Pattern Detection Phase/Frequency Control module 240 is diagrammed in
At 501, it is determined whether M zeroes have been detected. If not, flow returns to 501 until M zeroes have been detected. Once M zeroes have been detected at 501, then at 502, it is determined whether a one has been detected. If so, then at 503 it is determined whether a second one has been detected. If so, then at 504 phase is adjusted based on the values of DC[K], DE[K] and DC[K+1], according to Tables 1 and 2 above, and method 500 ends. If at 503 a second one is not detected, but rather a zero, then the required pattern for initiating phase adjustment has not been met and flow returns to 501 to again await detection of at least M zeroes.
If at 502 a one has not been detected after M zeroes, that means another zero has been detected. Flow continues to 505 where it is determined whether M+N zeroes have been detected. If not, then a string of more than M zeroes but fewer than M+N zeroes has been detected, which is a string of fewer than N zeroes followed by M zeroes, meaning that it is still the case the M zeroes have been detected.
At 506 it is determined whether a one has been detected. If not, then another zero has been detected and flow returns to 505 to determine whether M+N zeroes have been detected. If at 506 a one has been detected, meaning M zeroes (plus some number of zeroes fewer than N zeroes) have been followed by a one, then flow proceeds to 503 and continues as described above.
If at 505 it is determined that M+N zeroes have been detected, then flow proceeds to 507 to determine whether a one has been detected. If not, then a zero has been detected and flow returns to 505 to determine again that M+N zeroes have been detected (the answer will be “yes,” even though there are additional zeroes beyond M+N zeroes), and then proceeds again to 507 to determine whether a one has been detected and flow proceeds as above.
If at 507 a one has been detected, then at 508 it is determined whether a second one has been detected. If so, then at 509 frequency is adjusted based on the values of DC[K], DE[K] and DC[K+1], according to Tables 3 and 4 above, and method 500 ends. If at 509 a second one is not detected, but rather a zero, then the required pattern for initiating frequency adjustment has not been met and flow returns to 501 to again await detection of at least M zeroes.
Thus it is seen that phase and frequency control for an injection-locked oscillator has been provided. This allows an injection-locked oscillator to be used for clock-data recovery in a short-reach data link having low channel loss, keeping the ratio of the oscillator free-running frequency (FRF) to the data rate constant.
As used herein and in the claims which follow, the construction “one of A and B” shall mean “A or B.”
It is noted that the foregoing is only illustrative of the principles of the invention, and that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.
This disclosure claims the benefit of commonly-assigned U.S. Provisional Patent Application No. 62/653,388, filed Apr. 5, 2018, which is hereby incorporated by reference herein in its entirety.
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| Number | Date | Country | |
|---|---|---|---|
| 62653388 | Apr 2018 | US |
