Phase Comparator

Abstract

A phase comparator includes: first and second detecting units for detecting an amplitude value of a clock signal at falling timing or rising timing of a data signal; an edge comparing unit for identifying as to whether the first detecting unit detects an amplitude value under a rising state or a falling state to output a first identification result, and for identifying as to whether the second detecting unit detects an amplitude value under a rising state or a falling state to output a second identification result; first and second polarity inverting units for inverting a polarity of output of the first and second detecting units; and a signal selecting unit for selecting one of output values of the first and second polarity inverting units in response to a polarity of the data signal to output the selected output value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram for representing an arrangement of a phase comparator according to a first embodiment of the present invention;

FIG. 2 is a timing chart for indicating operations of the phase comparator according to the first embodiment of the present invention;

FIG. 3 is a block diagram for representing an arrangement of a phase comparator according to a second embodiment of the present invention;

FIG. 4 is a timing chart for indicating operations of the phase comparator according to the second embodiment of the present invention;

FIG. 5 is a block diagram for representing an arrangement of a phase comparator according to a third embodiment of the present invention;

FIG. 6 is a block diagram for showing the arrangement of a conventional clock data recovery circuit;

FIG. 7 is a block diagram for indicating the arrangement of the conventional phase comparator shown in FIG. 6;

FIG. 8 is a timing chart for indicating operations (full bit rate) of the conventional phase comparator;

FIG. 9 is a timing chart for indicating operations (half bit rate) of the conventional phase comparator;

FIG. 10 is a block diagram for showing another arrangement of the conventional phase comparator; and

FIG. 11 is a timing chart for indicating operations of the conventional phase comparator shown in FIG. 10.

Claims

1. A phase comparator, comprising: a first detecting means for detecting an amplitude value of a clock signal inputted at falling timing of an inputted data signal;a second detecting means for detecting an amplitude value of the clock signal at rising timing of the data signal;an edge comparing means for identifying as to whether the first detecting means detects an amplitude value under a rising state of the clock signal or an amplitude value under a falling state of the clock signal to output a first identification result, and for identifying as to whether the second detecting means detects an amplitude value under a rising state of the clock signal or an amplitude value under a falling state of the clock signal to output a second identification result;a first polarity inverting means for inverting a polarity of an output of the first detecting means in response to the first identification result derived from the edge comparing means;a second polarity inverting means for inverting a polarity of an output of the second detecting means in response to the second identification result derived from the edge comparing means; anda signal selecting means for selecting one of an output value of the first polarity inverting means and an output value of the second polarity inverting means in response to a polarity of the data signal to output the selected output value.

2. A phase comparator according to claim 1, wherein the edge comparing means comprises: a phase delaying means for delaying a phase of the clock signal;a first identifying means for identifying the delayed clock signal derived from the phase delaying means at the falling timing of the data signal to output the first identification result; anda second identifying means for identifying the delayed clock signal derived from the phase delaying means at the rising timing of the data signal to output the second identification result.

3. A phase comparator according to claim 2, wherein the phase delaying means delays the phase of the clock signal by a ¼ time period.

4. A phase comparator, comprising: a ring type oscillator for producing a first clock signal and a second clock signal by delaying a phase of the first clock signal;a first detecting means for detecting an amplitude value of the first clock signal produced from the ring type oscillator at falling timing of an inputted data signal;a second detecting means for detecting an amplitude value of the first clock signal produced from the ring type oscillator at rising timing of the inputted data signal;a first identifying means for identifying the second clock signal produced from the ring type oscillator at the falling timing of the data signal;a second identifying means for identifying the second clock signal produced from the ring type oscillator at the rising timing of the data signal;a first polarity inverting means for inverting a polarity of an output of the first detecting means in response to the first identification result derived from the first identifying means;a second polarity inverting means for inverting a polarity of an output of the second detecting means in response to the second identification result derived from the second identifying means; anda signal selecting means for selecting one of an output value of the first polarity inverting means and an output value of the second polarity inverting means in response to a polarity of the data signal to output the selected output value.

5. A phase comparator according to claim 4, wherein the ring type oscillator produces both the first clock signal and the second clock signal by delaying a phase of the first clock signal by a ¼ time period.