Patent Application
20240356495
In wireless communication devices, a radio frequency (RF) front end module processes modulated RF signals that are received from an antenna or to be transmitted by an antenna. In the transmission path, an RF front end module often has an RF power amplifier having one or more stages of power amplification that amplify the power of the RF signals to a level suitable for transmission. The performance of an RF power amplifier can be evaluated by a variety of metrics, such as gain, efficiency, linearity, and harmonic leakage.
The subject matter disclosed herein relates to techniques for improving the efficiency, e.g., power added efficiency (PAE), of a RF power amplifier, such as a Doherty power amplifier. An RF power amplifier implemented according to the disclosed techniques utilizes neutralization paths between a carrier path and a peak path of a Doherty amplifier to offset parasitic capacitance in the circuit and thereby achieve high gain at the output stage. The increased output stage gain can improve the overall PAE of the RF power amplifier such that fewer driver stages are needed. The reduced number of driver stages can lead to a reduced size of the RF power amplifier circuit.
In general, in some aspects, the subject matter of the present disclosure can be embodied in an electronic circuit, such as a power amplifier circuit of an RF front end circuit. The electronic circuit includes: a quadrature coupler arranged to receive an RF signal and configured to output a carrier path signal and a peak path signal; a carrier amplification circuit arranged to receive the carrier path signal and configured to generate an amplified carrier path signal; a peak amplification circuit arranged to receive the peak path signal and configured to generate an amplified peak path signal; a first neutralization circuit arranged between an input of the carrier amplification circuit and an output of the peak amplification circuit; a second neutralization circuit electrically arranged between an input of the peak amplification circuit and an output of the carrier amplification circuit; and a combiner circuit. The first neutralization circuit is configured to generate a first neutralizing signal and modify the amplified peak path signal based on the first neutralizing signal to obtain a neutralized peak path signal. The second neutralization circuit is configured to generate a second neutralizing signal and modify the amplified carrier path signal based on the second neutralizing signal to obtain a neutralized carrier path signal. The combiner circuit is configured to combine the neutralized carrier path signal and the neutralized peak path signal.
In some implementations, the quadrature coupler is configured to offset the carrier path signal from the peak path signal by +90° in phase, the first neutralization circuit includes a +90° phase shifter, and the second neutralization circuit includes a −90° phase shifter. Alternatively, the quadrature coupler is configured to offset the carrier path signal from the peak path signal by −90° in phase, the first neutralization circuit includes a −90° phase shifter, and the second neutralization circuit includes a +90° phase shifter.
In some implementations, the first neutralization circuit includes a first neutralization capacitor, and the second neutralization circuit includes a second neutralization capacitor.
In some implementations, a first capacitance value of the first neutralization capacitor and a second capacitance value of the second neutralization capacitor are determined according to at least one of: a frequency of the RF signal, a device size of the electronic circuit, an amplification gain of the electronic circuit, or a stability of the electronic circuit.
In some implementations, the combiner circuit includes a quarter-wave length phase shifter connected in series with either the peak amplification circuit or the carrier amplification circuit according to a type of combination, the type including at least one of voltage combination or current combination.
In some implementations, the electronic circuit further includes a driver circuit. The driver circuit includes an input matching circuit and at least one stage of power amplification. The input matching circuit is arranged to receive an input signal. The driver circuit is configured to generate the RF signal by amplifying the input signal using the at least one stage of power amplification.
In some implementations, wherein each stage of the at least one stage of power amplification includes a corresponding power amplifier and a corresponding interstage matching circuit connected in series.
In some implementations, the carrier amplification circuit includes one or more carrier amplification bipolar junction transistors (BJTs), and the peak amplification circuit includes one or more peak amplification BJTs.
In some implementations, the electronic circuit further includes an output matching circuit electrically coupled the combiner circuit.
In some aspects, the subject matter of the present disclosure can be embodied in a method for amplifying an RF signal. The method includes providing the RF signal to an input of a quadrature coupler. The method includes outputting, from the quadrature coupler, a carrier path signal and a peak path signal. The method includes amplifying the carrier path signal to provide an amplified carrier path signal and amplifying the peak path signal to provide an amplified peak path signal. The method includes generating a first neutralizing signal based on the carrier path signal and generating a second neutralizing signal based on the peak path signal. The method includes modifying the amplified peak path signal based on the first neutralizing signal to provide a neutralized peak path signal and modifying the amplified carrier path signal based on the second neutralizing signal to provide a neutralized carrier path signal. The method also includes combining the neutralized carrier path and peak path signals.
In some implementations, the carrier path signal leads the peak path signal by 90°. Generating the first neutralizing signal includes connecting a +90° phase shifter and a first neutralization capacitor in series to obtain a first neutralization circuit, and providing the carrier path signal to the first neutralization circuit to obtain the first neutralizing signal. Generating the second neutralizing signal includes connecting a −90° phase shifter and a second neutralization capacitor in series to obtain a second neutralization circuit, and providing the peak path signal to the second neutralization circuit to obtain the second neutralizing signal. Modifying the amplified peak path signal includes coupling the first neutralizing signal to the amplified peak path signal. Modifying the amplified carrier path signal includes coupling the second neutralizing signal to the amplified carrier path signal.
In some implementations, the peak path signal leads the carrier path signal by 90°. Generating the first neutralizing signal includes connecting a −90° phase shifter and a first neutralization capacitor in series to obtain a first neutralization circuit, and providing the carrier path signal to the first neutralization circuit to obtain the first neutralizing signal. Generating the second neutralizing signal includes connecting a +90° phase shifter and a second neutralization capacitor in series to obtain a second neutralization circuit, and providing the peak path signal to the second neutralization circuit to obtain the second neutralizing signal. Modifying the amplified peak path signal includes coupling the first neutralizing signal to the amplified peak path signal. Modifying the amplified carrier path signal includes coupling the second neutralizing signal to the amplified carrier path signal.
In some implementations, the method further includes determining a first capacitance value of the first neutralization capacitor and a second capacitance value of the second neutralization capacitor according to at least one of: a frequency of the RF signal, a device size, an amplification gain, or a circuit stability.
In some implementations, combining the neutralized carrier path signal and the neutralized peak path signal includes: phase-shifting, using a quarter-wave length phase shifter, either the neutralized carrier path signal or the neutralized peak path signal according to a type of combination, the type including at least one of voltage combination or current combination.
In some implementations, the method further includes: receiving an input signal; amplifying the input signal using a driver circuit including at least one stage of power amplification; and obtaining the RF signal from the driver circuit.
In some implementations, the method further includes: obtaining a combined RF signal; and providing the combined RF signal to an output matching circuit.
The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of these systems and methods will be apparent from the description and drawings, and from the claims.
For RF power amplifiers with multiple stages of power amplification, the last stage is an output stage, while the other stages are collectively referred to as driver stages. The output stage is usually where a large amount of amplification (e.g., gain) is achieved, while each of the driver stages, due to circuit design constraints, usually contributes less to the overall gain. For each stage of amplification, higher gain usually means higher efficiency of power amplification. In many applications of mobile technologies, such as mobile phones, it is desirable to have high power amplification efficiency because of limited power supply.
Many RF power amplifiers operate at a power level often referred to as the backoff power. The backoff power of an RF power amplifier is a power level below the saturation point of the RF power amplifier. Having the RF power amplifier operate at the backoff power instead of at the saturation point can help keep the RF power amplifier operating in the linear range even at occasions when the power of the input signal reaches a level (e.g., a peak level) that is higher than the average power level. However, the efficiency of an RF power amplifier tends to decrease when the RF power amplifier operates at a lower power level than the saturation point. Some communication technologies use signals whose power has high peak-to-average ratio, e.g., 10 dB for orthogonal frequency-division multiplexing (OFDM) signals. In these scenarios, the backoff power can be considerably lower than the saturation point, which leads to considerable decrease in average efficiency.
Doherty amplifiers can be effective in increasing power amplification efficiency at the backoff power, in particular at the output stage. A Doherty amplifier divides an RF signal into two paths with a phase difference of 90°, uses a main amplifier (also known as a carrier amplifier) and a peak amplifier to separately amplify the divided signals, and combine the two paths after amplification. While Doherty amplifiers can increase power amplification efficiency at the backoff power thanks to load modulation provided by the peak amplifier, Doherty amplifiers can experience extra power loss and reduced efficiency at the peak power due to parasitic capacitance associated with the transistors in each path.
As described in detail below, implementations of this disclosure utilize neutralization paths to modify the amplified signals on the carrier path and the peak path by effectively reducing or canceling the parasitic capacitance on each path. As a result of such neutralization, RF power amplifiers implemented according to this disclosure can, in some cases, have increased gain at the output stage, and, consequently, increased power efficiency of one or more stages of the power amplifier combined. With the increased output stage gain, the number of driver stages can, in some implementations, be reduced, resulting in smaller circuit size and lower manufacturing complexity and cost.
In the example of
In some implementations, the at least one WWAN with which the at least one base station 120 is associated can be a fifth generation (5G) network among other generations and types of networks. In these implementations, the at least one base station 120 can be a 5G base station that employs orthogonal frequency-division multiplexing (OFDM) and/or non-OFDM and a transmission time interval (TTI) shorter than 1 ms (e.g. 100 or 200 microseconds), to communicate with wireless devices, such as wireless device 110. For example, the at least one base station 120 can take the form of one of several devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a next (fifth) generation (NR) NodeB (gNB), a Home NodeB, a Home eNodeB, a site controller, an access point, a wireless router, a server, router, switch, or other processing entity with a wired or wireless network.
System 100 can use multiple channel access functionality, including for example schemes in which the at least one base station 120 and the wireless device 110 are configured to implement the Long Term Evolution wireless communication standard (LTE), LTE Advanced (LTE-A), and/or LTE Multimedia Broadcast Multicast Service (MBMS). In other implementations, the at least one base station 120 and wireless device 110 are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols can be utilized. In some examples, one or more such access schemes and wireless protocols can correspond to standards that impose RF power amplifier linearity requirements.
In addition, and as shown in
To communicate with one or both of the at least one base station 120 and the access point 130, the wireless device 110 can include singular or multiple transmitter and receiver components similar or equivalent to one or more of those described in further detail below with reference to
Although
The processor 240 can implement various processing operations of the wireless device 110. For example, the processor 240 can perform signal generation, signal coding, signal analysis, data processing, power control, input/output processing, or any other functionality enabling the wireless device 110 to operate in a communication system, such as system 100 (
The transmitter 210 can be configured to modulate data or other content, filter and amplify outgoing RF signals for transmission by at least one antenna 250A. In some implementations, the transmitter 210 can also be configured to amplify, filter and upconvert baseband or intermediate frequency (IF) signals to RFs signals before such signals are provided to the antenna 250A for transmission. The transmitter 210 can include any suitable structure for generating RF signals for wireless transmission. Additional aspects of the transmitter 210 are described in further detail below with reference to components 212-218 as depicted in
The receiver 220 can be configured to demodulate data or other content received in incoming RF signals by at least one antenna 250B. In some implementations, the receiver 220 can also be configured to amplify, filter and frequency down convert RF signals received via the antenna 250B either to IF or baseband frequency signals prior to conversion to digital form and processing. The receiver 220 can include any suitable structure for processing signals received wirelessly.
Each of the antennas 250A and 250B can include any suitable structure for transmitting and/or receiving wireless RF signals. In some implementations, the antennas 250A and 250B can be implemented by way of a single antenna that can be used for both transmitting and receiving RF signals.
One or multiple transmitters 210, one or multiple receivers 220, and one or multiple antennas 250 could be used in the wireless device 110. For example, in one implementation, device 110 includes at least three transmitters 210 and at least three receivers 220 for communicating via at least a personal area network such as Bluetooth®, a Wi-Fi network such as an IEEE 802.11 based network, and a cellular network. Each transmitter 210 may employ the concepts of the present disclosure. Although shown as separate blocks or components, at least one transmitter 210 and at least one receiver 220 could be combined into a transceiver. Each transceiver may employ the concepts of the present disclosure. Accordingly, rather than showing a separate block for the transmitter 210 and a separate block for the receiver 220 in
The wireless device 110 further includes one or more input/output devices 260. The input/output devices 260 facilitate interaction with a user. Each input/output device 260 includes any suitable structure for providing information to or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, and/or touch screen.
In addition, the wireless device 110 includes at least one memory 230. The memory 230 stores instructions and data used, generated, and/or collected by the wireless device 110. For example, the memory 230 could store software or firmware instructions executed by the processor(s) 240 and data used to reduce or eliminate interference in incoming signals. Each memory 230 includes any suitable volatile and/or non-volatile storage and retrieval device(s). Any suitable type of memory may be used, such as random access memory (RAM), read only memory (ROM), hard disk, optical disc, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, and the like.
In some implementations, the transmitter 210 can include signal processing circuitry 212, modulation circuitry 214, and RF front end circuitry 218. The signal processing circuitry 212 may include one or more circuits that are configured to process signals received as input (e.g. from processor 240). For example, the signal processing circuitry 212 may include a digital-to-analog converter (D/A), which converts a digital input (e.g. a digital signal from processor 240) into an analog signal, which is then provided to a low pass filter, which filters the analog signal and provides the filtered analog signal to the modulation circuitry 214. The modulation circuitry 214, in addition to receiving the filtered analog signal from the signal processing circuitry 212, can, in some implementations, also receive a signal from a local oscillator 216 for modulating or adjusting the frequency of the analog signal, e.g., from a first frequency to a second frequency that is higher than the first frequency. For instance, the modulation circuitry 214 can include a mixer that frequency up-converts the filtered analog signal from a relatively low frequency (e.g. baseband frequency, or an IF that is offset from the baseband frequency) to a relatively high frequency RF signal. Thus, a signal from the local oscillator 216 is used as a carrier signal in transmitter 210. Moreover, as shown in
The RF signal amplified by the power amplifier may be filtered again by at least one additional filter downstream of the power amplifier before being provided as an output of the transmitter 210 to the at least one antenna 250A for wireless transmission. Such filter or filters can alternatively be provided upstream from the power amplifier in which case the output of the power amplifier is provided to the at least one antenna 250A for wireless transmission.
As shown on the graph 300, the PAE of the amplifier is positively correlated to the output stage gain. For example, with the output stage gain increasing from 10 dB to 15 dB, the PAE increases from about 16.76% to about 20.40%. Such positive correlation indicates that the efficiency can be achieved by increasing the output stage gain.
The RF power amplifier circuit 500A is configured to receive an input RF signal from the input port 501 (which can be coupled to an input port of the RF front end circuitry 218), amplify the RF signal, and output the amplified RF signal via the output port 570. To achieve the amplification, the RF power amplifier circuit 500A has a driver circuit 510 with one or more driver stages, and an output stage arranged between the driver circuit 510 and the output port 570.
Each driver stage includes a power amplifier 512 with an output coupled to an interstage matching circuit 513. The power amplifier 512 can have a BJT-based structure similar to that of the circuit 400. Alternatively or additionally, the power amplifier 512 can have a different structure, such as a Field-Effect Transistor (FET)-based structure, with different components from the circuit 400. The interstage matching circuit 513 provides impedance matching between two consecutive driver stages and between the last driver stage and the output stage. The driver circuit 510 also has an input matching circuit 511 that provides impedance matching between the input port 501 and the first driver stage. The interstage matching circuits 513 and the input matching circuit 511 together facilitate the propagation of RF signals from the input port 501 through the driver circuit 510 to the output stage.
The output stage of the RF power amplifier circuit 500A includes a quadrature coupler 520, a carrier amplification circuit 530, a peak amplification circuit 532, and a combiner circuit 550A. The quadrature coupler 520, carrier amplification circuit 530, peak amplification circuit 532, and combiner circuit 550A, along with the connections therebetween, form a basic structure of a Doherty amplifier. The quadrature coupler 520 receives an RF signal 512 from the driver circuit 510 and splits the RF signal 512 into a carrier path signal 521 and a peak path signal 522. In addition, the quadrature coupler 520 offsets the carrier path signal 521 from the peak path signal 522 by −90° in phase. In other words, the carrier path signal 521 lags behind the peak path signal 522 by 90° in phase. In some other implementations, the quadrature coupler 520 can instead offset the carrier path signal 521 from the peak path signal 522 by +90° in phase, causing the carrier path signal 521 to lead the peak path signal 522 by 90° in phase.
The carrier path signal 521 and the peak path signal 522 are input to the carrier amplification circuit 530 and the peak amplification circuit 532, respectively, for amplification. Each of the carrier amplification circuit 530 and the peak amplification circuit 532 can have a BJT-based structure similar to that of the circuit 400. Alternatively or additionally, each of the carrier amplification circuit 530 and the peak amplification circuit 532 can have a different structure, such as a Field-Effect Transistor (FET)-based structure, with different components from the circuit 400.
The combiner circuit 550A combines the amplification outputs from the carrier amplification circuit 530 and the peak amplification circuit 532 and provide the combination outcome to the output port 570. The combination provided by the combiner circuit 550A can be considered of a type of current combining, where the current from the carrier path and the current from the peak path are added (e.g., via an RF coupler) at node C. An output matching circuit 560 can be arranged between the combiner circuit 550A and the output port 570 to provide impedance matching between the two.
The combiner circuit 550A can include a quarter-wave length phase shifter 552 (e.g., a transmission line with impedance set to provide a +90° phase shift) connected in series with the carrier amplification circuit 530. For example, in implementations where the carrier path signal 521 lags behind the peak path signal 522 by 90° in phase, the quarter-wave length phase shifter 552 can be connected in series with the carrier amplification circuit 530 to compensate for the −90° phase difference imposed by the quadrature coupler 520 between the carrier path signal 521 and the peak path signal 522. With the phase compensation, the currents on the two paths are again in phase when combined at node C.
The output stage of the RF power amplifier circuit 500A further includes two neutralization circuits. A first neutralization circuit is arranged between an input 523 of the carrier amplification circuit 530 and an output 526 of the peak amplification circuit 532. A second neutralization circuit is arranged between an input 524 of the peak amplification circuit 532 and an output 525 of the carrier amplification circuit 530. The first neutralization circuit includes a first neutralization capacitor 541 and a first phase shifter 543, connected in series. The second neutralization circuit includes a second neutralization capacitor 542 and a second phase shifter 544, connected in series. Although
In implementations where the carrier path signal 521 lags behind the peak path signal 522 by 90° in phase, the first phase shifter 543 is a −90° phase shifter and the second phase shifter 544 is a +90° phase shifter. As such, when a branch of the carrier path signal 521 flows through the first neutralization circuit, the first phase shifter 543 imposes an additional −90° phase shift to the branch. As a result, the first neutralization circuit generates a first neutralizing signal 548 that differs from the peak path signal 522 by 180° in phase. Likewise, when a branch of the peak path signal 522 flows through the second neutralization circuit, the second phase shifter 544 imposes an additional +90° phase shift to the branch. As a result, the second neutralization circuit generates a second neutralizing signal 546 that differs from the carrier path signal 521 by 180° in phase.
In alternative implementations where the carrier path signal 521 leads the peak path signal 522 by 90° in phase, the first phase shifter 543 is a +90° phase shifter and the second phase shifter 544 is a −90° phase shifter. With the phase shift provided by the first and second phase shifters 543 and 544, the first and second neutralizing signals 548 and 546 in these implementations also differ from the peak path signal 522 and the carrier path signal 521, respectively, by 180° in phase.
The first and second neutralizing signals 548 and 546 are provided to the peak path and the carrier path, respectively, to neutralize (e.g., cancel or reduce) the parasitic capacitance associated with amplifying transistors of the carrier amplification circuit 530 and the peak amplification circuit 532. Taking the first neutralizing signal 548 as an example, the first neutralizing signal 548 is coupled with an amplified peak path signal output by the peak amplification circuit 532 at output 526. The coupling can modify the amplified peak path signal to generate a neutralized peak path signal 528. Similarly, the second neutralizing signal 546 is coupled with and thereby modifies an amplified carrier path signal to generate a neutralized carrier path signal 527.
Compared with Doherty amplifiers that do not have neutralization circuits, a Doherty RF power amplifier modified in accordance with circuit 500A can, by way of modifying the amplified carrier path and peak path signals, neutralize the parasitic capacitance associated with amplifying transistors of the carrier amplification circuit 530 and the peak amplification circuit 532 on each path. The neutralization can be attributed to the impedance introduced by the neutralization capacitors and the phase shifters of the neutralization circuits.
The tuning of the capacitance of the first and second neutralization capacitors 541 and 542 can consider a number of factors or constraints, such as the frequency of the RF signal 515, the size of RF power amplifier circuit 500A (or, separately, the size of the output stage), the gain of the RF power amplifier circuit 500A (or, separately, the target gain of the output stage), and the stability of the RF power amplifier circuit 500A. Similarly, the tuning of the characteristic impedance of the first and second phase shifters 543 and 544 can consider a number of factors or constraints with a goal of achieving the needed neutralization effect while reducing unwanted impact to Doherty load modulation.
Different from the combiner circuit 550A that combines currents from the carrier path and the peak path, the combiner circuit 550B uses a RF transformer 554 for voltage combining. In voltage combining, two signals with a phase difference of 180° are input to the “+” and “−” input ports of the transformer 554, whose output port, in some implementations, can be coupled to a matching circuit and further to amplifier output. This type of voltage combining also uses a quarter-wave length phase shifter 552 (e.g., a transmission line with optimized impedance set to provide a +90° phase shift). For example, in implementations where the carrier path signal lags behind the peak path signal by 90° in phase, the quarter-wave length phase shifter 552 can be connected in series with the peak amplification circuit such that the signals at the “+” and “−” input ports of the transformer 554 are 180° different in phase.
As shown in the graphs 600A and 600B, Doherty load modulation can be maintained with proper tuning of Zm and Zp, which can be adjusted by tuning the impedance of the neutralization circuits. This comparison shows that implementations described herein can be applied to Doherty power amplifiers without significant compromises to the proper functioning thereof.
At 802, the method 800 involves providing the RF signal to an input of a quadrature coupler (e.g., the quadrature coupler 520).
At 804, the method 800 involves outputting, from the quadrature coupler, a carrier path signal (e.g., the carrier path signal 521) and a peak path signal (e.g., the peak path signal 522).
At 806, the method 800 involves amplifying (e.g., using the carrier amplification circuit 530) the carrier path signal to provide an amplified carrier path signal.
At 808, the method 800 involves amplifying (e.g., using the peak amplification circuit 532) the peak path signal to provide an amplified peak path signal.
At 810, the method 800 involves generating a first neutralizing signal (e.g., the first neutralizing signal 548) based on the carrier path signal.
At 812, the method 800 involves generating a second neutralizing signal (e.g., the second neutralizing signal 546) based on the peak path signal.
At 814, the method 800 involves modifying the amplified peak path signal based on the first neutralizing signal to provide a neutralized peak path signal (e.g., the neutralized peak path signal 528).
At 816, the method 800 involves modifying the amplified carrier path signal based on the second neutralizing signal to provide a neutralized carrier path signal (e.g., the neutralized carrier path signal 527).
At 818, the method 800 involves combining (e.g., using the combiner circuits 550A or 550B) the neutralized carrier path signal and the neutralized peak path signal.
While features described above are primarily implemented by wireless devices, these features can likewise be implemented by access nodes, base stations, or other types fixed or portable wireless communication equipment and/or infrastructure. For example, a base station in communication with a cellular phone can have RF front end circuitry that implements the above-described features with respect to thermally adjustable DC bias circuit.
While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations of particular inventions. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.
In addition, techniques, systems, subsystems, and methods described and illustrated in the various implementations as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and could be made without departing from the spirit and scope disclosed herein.
For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.
Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results.
