Patent Grant
8466713
The present invention relates to a phase detection method and a phase detector according to the preamble parts of claims 1 and 10, respectively. Such a method and phase detector are described in J. D. H. Alexander, “Clock Recovery from Random Binary Data”, Elect. Lett., vol. 11, pp. 541-542, October 1975, later referred to as Alexander75.
This invention relates to timing or clock recovery utilizing pulse shape features. In particular the invention improves clock recovery for optical high-speed data transmission systems using optical duo-binary (ODB) or chirp managed laser (CML) modulation formats in the presence of significant residual dispersion.
Timing recovery is a critical receiver function in high-speed communication systems. The receiver clock must be continuously adjusted in its frequency and phase to optimize the sampling instants of the received data signal and to compensate for frequency drifts between the oscillators used in the transmitter and receiver clock circuits. Usually, a clock synchronizer should perform both functions. In some cases an additional phase adjustment is needed. Background Art for timing recovery is described e.g. in W. R. Bennett, “Statistics of regenerative digital transmission”, Bell. Syst. Tech. J., vol. 37, pp. 1501-1542, November 1958; Y. Takasaki, “Timing extraction in baseband pulse transmission”, IEEE Trans. Commun., vol. COM-20, pp. 877-884, October 1972; and L. E. Franks and J. P. Bubrouski, “Statistical properties of timing jitter in a PAM timing recovery system”, IEEE Trans. Commun., vol. COM-22, pp. 913-920, July. 1974.
In some older systems, a specific carrier corresponding to the sampling frequency was transmitted, providing frequency and phase information for sampling. However, most modern systems do not provide a carrier; it is therefore important to accurately recover the symbol timing using only the received signal which is referred to as self-timing.
A crude distinction can be made between two classes of clock recovery methods applied to pulse amplitude modulation (PAM) signals:
The second class of methods, to which this invention belongs, exploits some feature of the pulse shape characteristics (cf. B. R. Saltzberg, “Timing recovery for synchronous binary data transmission”, Bell. Syst. Tech. J., vol. 46, pp. 593-622, March 1967). The most frequently used synchronizers of this class locate the threshold crossings of the received base-band signal. The mean location of the crossings is estimated and the optimum sampling instant and maximum eye opening are assumed to be halfway between these crossings (cf. Alexander75 and C. R. Hogge, “A Self-Correcting Clock Recovery Circuit”, IEEE J. Lightwave Tech., vol. 3, pp. 1312-1314, December 1985). Similar disclosures are comprised in US 2003/0219090 A1 and WO 2006/128114 A1. A synchronizer described in K. H. Mueller and M. Müller, “Timing recovery in digital synchronous data receivers”, IEEE Trans. Commun., vol. COM-24, pp. 516-531, May. 1976 uses the receiver decisions for the timing function. This method requires the derivation of a timing error estimate that gives timing information at the arrival of each data symbol. This yields relatively high variance estimates of the timing error that is avoided in the method explained in A. Jennings and B. R. Clarke, “Data-Sequence Selective Timing Recovery for PAM Systems”, IEEE Trans. Commun., vol. COM-33, pp. 729-731, July. 1985. Some interesting ideas can be found in M. Arai, M. Yamaguchi and T. Ogata, “DIGITAL SIGNAL RECEIVING CIRCUIT WITH MEANS FOR CONTROLLING A BAUD RATE SAMPLING PHASE BY A POWER OF SAMPLED SIGNALS”, U.S. Pat. No. 5,048,060, Sep. 10, 1991; J. Ragnar, O. Sverrir and B. Elias, “TIMING RECOVERY FOR A HIGH SPEED DIGITAL DATA COMMUNICATION SYSTEM BASED ON ADAPTIVE EQUALIZER IMPULSE RESPONSE CHARACTERISTICS”; PCT, No. WO 00/19655, Apr. 6, 2000; and B. Joseph, H. Syang-Myau and R. Roopa, “SYMBOL TIMING RECOVERY METHOD FOR LOW RESOLUTION MULTIPLE AMPLITUDE SIGNALS”, PCT, No. WO 02/30035 Apr. 11, 2002, that use either an autocorrelation function, equalizer outputs or over-sampled signals for timing extraction, respectively.
PCT/US03/05515 teaches that two versions of the clock being shifted by 90° (VCO_I, VCO_Q) are sampled upon rising or falling edges in the data signal.
The best timing phase for a given system depends on the overall impulse response and thus on the characteristics of the communication channel. The main problems are caused by noise, distortion and unknown delay. These disturbances can severely limit the performance of synchronizer.
Our objective was to design a robust clock synchronizer that will be able to cope with the serious distortions present in optical transmission systems. Besides noise, most of the problems affecting the performance of timing recovery circuits are caused by distortions such as chromatic dispersion, polarization mode dispersion, self-phase modulation and cross-phase modulation. None of the well-known synchronizers used in current practical systems is able to cover such a wide spectrum of distortion as the synchronizers described in this innovation report. We will limit the explanation of the method to the application to binary optical transmissions. However, this fact does not limit the application of the synchronizer in any binary and multilevel PAM transmission system.
The physical interface 31 performs an optical-to-electrical (O/E) conversion. The physical interface 31 uses either a pin diode or an avalanche photo diode to convert the incident optical power to an electrical current. A transimpedance amplifier (TIA) is used to amplify and convert the photo-current to a voltage.
The analog serial signal data at the output of physical interface 31 is amplified by a high-gain high-dynamic, low-noise AGC or VGA circuit 32. The output signal of AGC 32 is designated {tilde over (r)}(t).
The ADC 33 digitizes the analog signal {tilde over (r)}(t) and outputs quantized data yt, s. Index t refers to a time slot and index s refers to different sampling phases. Index s may assume the values 1 to S for S-fold oversampling. S may be 2. The ADC 33 receives a sampling clock from SPA circuit 35 which in turn receives a sampling clock from clock recovery subsystem 34. The SPA circuit 35 operates as an adjustable delay in order to optimize the phase of the clock e.g. in terms of overall bit-error rate (BER), which is to say to optimize the sampling times of ADC 33. The SPA circuit 35 may or may not be present.
The quantized data yt, s are input into MLSE 38. MLSE 38 may implement a Viterbi algorithm (VA) and outputs the most likely sequence designated detected data ut to FEC decoder 39. In a typical optical receiver, with a powerful FEC code used, the bit error rate at the output of MLSE 38 ranges e.g. from 10−2 to about 104. The subsequent FEC decoder 39 further reduces bit error rate to a range between 10−9 and 10−16 which is required for data transmission. FEC decoder 39 outputs decoded data x, for further processing. MLSE 38 and/or FEC 39 may obtain BER estimates and provide same to control node 36.
Control node 36 receives a loss-of-signal (LOS) signal from physical interface 31 and may receive counter values or event frequency information bt from channel model unit 37 in order to obtain pre-processed statistics data for controlling the AGC/VGA circuit 32, CR 34 and SPA circuit 35.
The clock recovery (CR) circuit 34 extracts frequency and phase information from the received signal and generates a local sampling clock at equidistant points in time, with some fixed phase relation to the transmitted symbol stream. Instead of using the analog signals after the AGC, the clock recovery circuit 34 can also use the quantized samples yt,2 directly from the ADC 33.
After an optical-to-electrical conversion, a typical non-return-to-zero (NRZ) electrical signal s(t) that corresponds to a binary unit conveyed over an undistorted optical channel may have a shape as presented in
Two samples corresponding to the current symbol (n-th sent symbol) are denoted as sA(n,τ) and sB(n,τ). The sample sA(n,τ) is obtained at time instant (n−1)T+τ and the sample sB(n,τ) is located at time instant (n−1)T+T/2+τ. The symbol period is denoted by T.
A variant of an early-late detector, the Alexander phase detector 10 described e.g. in Alexander75, uses three samples 1, 2 and 3 to derive phase information. The algorithm is described in
The input signal 51 passes limiter 11 which receives an offset from a voltage source 12. Samples are taken and stored by clocked D-type monostables 13, 14, 15 and 16 such that three successive samples 1, 2 and 3 designated variables a, b and c by Alexander75 can be examined simultaneously. Clocks C, CM and CC are at the nominal data rate. CM is arranged to be near to the mid-bit instant whilst CC occurs at the changeover time. Complimentary squarewave clock waveforms of CM and CC and edge triggered monostables ensure exactly interleaved sampling.
The logic control signals P and Q may control an oscillator which may be designed to operate either of three frequencies: f0 if P=0, fo+fx if P=1 and Q=0, and fo−fx if P=1 and Q=1. Alternatively, a 3-valued variable A may be generated by XOR-gates 19 and 20, and subtractor 21. A is 0, when the signal transition is not detected or when the transitions are not “clear” (010 or 101 sample combinations). However, A is −1 with a late transition (001 or 110), and A is 1 with an early transition (011 or 100).
According to H. Meyr, M. Moeneclaey, and S. A. Fechtel, “Digital Communication Receivers”, John Wiley & Sons, Inc., chap. 2.3, pp. 89-111, 1998, phase detectors can be analyzed in a unified way by studying:
The TEDC models the useful error feedback signal in a phase locked loop (PLL). The zeroes of this function with positive slope are equilibrium points. The TEDC is defined as the averaged phase detector output as a function of the phase difference between the received signal and reference signal, assuming a constant phase difference. Note that this is not the same as the instantaneous output of the phase detector at a given phase difference; the latter can be understood as a noisy version of the TEDC value. The graph of TEDC can be obtained experimentally by displaying the phase detector output under a small frequency difference.
There are channels e.g. optical signal-to-noise ratio (OSNR)=14 dB, a residual dispersion (RD) of 2200 ps/nm and non return to zero (NRZ) waveform for which the phase detector TEDC is very weak. For this channel, the CR is not able to generate a stable clock, due to the lack of a strong enough phase error feedback.
The TEDCMAX is a figure of merit for the comparison of phase detectors with similar TEDC shape. It is related to the TEDC slope used in the analytical study of phase detector performance. Reduced TEDCMAX values (and with it reduced TEDC slopes) lead to the decrease of phase detector performance over a wide range of distortions. NRZ TEDCMAXs of Alexander phase detector between RD of 2000 and 3000 ps/nm does not seem to be large enough for the clock extraction. In this region simulations show that the Alexander phase detector fails, and that is observed experimentally as well.
The linearized timing error deviation (LTED) indicates the amount of jitter expected at a certain sampling point. NRZ LTED's for the Alexander phase detector at the equilibrium point also indicate that clock recovery problems arise in the range of RD between 2000 and 3000 ps/nm. Such increased phase jitter of the Alexander phase detector is easily observed experimentally.
The same problems exist with other modulation formats (e.g. return-to-zero (RZ), ODB and CML). The critical RD range just depends on the modulation format and the channel characteristics. The presence of polarization mode dispersion (PMD) additionally impacts on the CR performance.
It is the object of this invention to provide an enhanced phase detection method and phase detector.
This object is achieved by the subject matter of the independent claims.
Preferred embodiments of the invention are the subject matter(s) of the dependent claims.
In the following preferred embodiments of this invention are described referring to the accompanying drawings.
While the present invention is described with reference to the embodiments as illustrated in the following detailed description as well as in the drawings, it should be understood that the following detailed description as well as the drawings are not intended to limit the present invention to the particular illustrative embodiments disclosed, but rather the described illustrative embodiments merely exemplify the various aspects of the present invention, the scope of which is defined by the appended claims.
The Alexander phase detector uses three samples (hard decisions) for detecting transitions. It evaluates both rising and falling transitions. When a transition is detected, the Alexander phase detector generates “early/late” timing error information (+1 or −1) that is used for phase (or frequency) adjustment. The best performance, in jitter and lock-in behavior, is achieved in a PLL when the rising and falling transitions are at the same position in a unit interval T. The worst performance is obtained when the difference between these two positions is equal to T/2. One solution is to discard one of the transitions and work either with a falling or with a rising transition. However, in this case the timing information of one type of transition is lost.
Let us consider two TEDCs, namely TEDCR and TEDCF that correspond to two separate phase detectors that evaluate the rising and falling transitions, respectively.
It is obvious to skilled persons that a PDR may be implemented for example by supplementing the Alexander logic shown in
When the TEDC zero crossings, which are TEDC equilibrium points, are not at the same location in a unit interval, the overall TEDC (TEDCR+TEDCF) can be weak as is shown in
However, by applying a suitable differential delay, i.e. by advancing the local clock signal for PDR and delaying the local clock signal for PDF by the same amount of τ0/2, we can effectively shift the two TEDCs being added so that they have the same equilibrium positions. The equivalent TEDC (TEDCR(τ+τ0/2)+TEDCF(τ−τ0/2)) is also shown in
As shown by example, differentially adjusting the phases of the signals seen by rising and falling phase detectors in order to achieve identical equilibrium phases improves the performance. A block diagram of a clock recovery circuit using this differential phase control concept is presented in
Adjustable phase shifter 54 delays the clock phase by φ/2 and provides a delayed clock to PDF 55. Adder 57 adds the phase control signals outputted by PDR 52 and PDF 55 for providing a single phase control signal to filter 58. The differential phase control (DPC) block 60 comprises a subtractor 61 and an ideal integrator 62 which has a gain of K at unity frequency. The integrator 62 controls the speed of the differential phase adjustment for subtracting the phase control signal of PDF 55 from the phase control signal of PDR 52 and integrating this difference.
The DPC 60 estimates the difference between two equilibrium points and outputs a signal that is used as an error signal for the adjustment of the differential phase φ until the shifted TEDCs match. The VCO steady-state phase φVCO is between two equilibrium points. The PDR sampling clock has a phase of φVCO−φ/2, while the PDF samples at phase φVCO+φ/2.
We propose two DPC realizations
The first approach uses two phase detectors 52 and 55 and estimates the difference between the equilibrium points in their outputs. The algorithm has low complexity and provides almost the same results as the second DPC method. The advantage of the second method is that the 4-PD DPC always keeps the VCO clock on a well-defined side of the rising PD equilibrium point (i.e. the sign of the difference between VCO clock and the closest PD equilibrium is well-defined). For reasons not explained in detail, this helps to avoid a 0.5 UI sampling phase ambiguity, which is important in equalizing receivers using some a priori knowledge about a sampling phase dependent channel model for detection, such as a blind MLSE receiver.
As a model for understanding, let us suppose that the TEDCs are sinusoidal functions, which is very close to reality in the presence of noise, i.e. as
TEDCR(θ)=sin(θ+φ/2)
TEDCF(θ)=sin(θ−φ/2). (1)
TEDCR(θ) is the averaged output of rising phase detector 52 at sampling phase θ. Likewise, TEDCF(θ) is the averaged output of falling phase detector 55.
Then the differential phase control signal (DPCS) is equal to
DPCS(θ,φ)=TEDCR(θ)−TEDCF(θ)=2 cos(θ)sin(φ/2) (2)
The DPCS is shown in
To avoid this sampling phase ambiguity, we propose the 4-PD DPC that is shown in
In addition, LPFs may be provided at the outputs of the I-PDR and I-PDF for reducing noise resulting in sampling phase jitter.
The PDR 52 and PDF 55 are also present in
Then, the TEDCs, namely TEDCRI(θ) TEDCRQ(θ) TEDCFI(θ) TEDCFQ(θ) of the phase detectors I-PDR 52, Q-PDR 69, I-PDF 55 and Q-PDF 70, respectively, are:
TEDCRI(θ)=sin(θ+φ/2)
TEDCRQ(θ)=sin(θ+φ/2+π/2)
TEDCFI(θ)=sin(θ−φ/2)
TEDCFQ(θ)=sin(θ−φ/2+π/2). (3)
The differential phase control signal DPCS is equal to (cf.
DPCS(θ,φ)=TEDCRI(θ)TEDCFQ(θ)−TEDCRQ(θ)TEDCFI(θ)=sin(φ). (4)
It can be noticed that the differential phase control signal DPCS does no longer depend on the sampling phase θ, see
Another advantage of the 4-PD eliminating the sampling phase dependent term cos(θ) is that it aids in the initial lock-in of the DPC control loop, when the PLL is still unlocked, which can be experimentally observed. In the presence of a frequency difference (i.e. when sampling phase is approximately linear in time) the expected DPCS of the 2-PD is zero, because the time average over the cos(θ) term is zero. Note that the DPC (for φ) must lock prior to and independent of the lock-in of the PLL (for θ).
In one preferred embodiment, the 4-PD is used for lock-in, and is switched to 2-PD operation after the PLL has locked, in order to avoid the noisy multiplication in nodes 63 and 64. This can be achieved by switching the Q inputs to constant sources.
Still another advantage of the 4-PD setup is that a low-pass filtered sum of the quadrature PD output signals can be used as a loss-of-lock detector for the PLL. To this end a LOL circuit as shown in
When the PLL shown in
When the PLL is unlocked, the phase error changes over time at a speed given by the frequency difference between VCO frequency and the frequency of the incoming data. The averaged output both of Q-PD and of I-PD is “0” in this case, because both PD signals show a noisy version of their sinusoidal TEDC as a function of time.
The lock detector idea is then to make a threshold decision for averaged Q-PD output:
To this end an adder 81 is provided which adds the outputs of quadrature phase detectors 69 and 70 and outputs the Q-PD signal. A low-pass filter 82 has a cut-off frequency of 1 MHz, which may be switched to 10 MHz. Consequently, the low-pass filter 82 removes the clock frequencies of the VCO 59 signal and the incoming data signal, harmonics and sum frequencies. A sign circuit 83 amplifies and limits the output of the low-pass filter 82. The sign circuit 83 may be implemented by an amplifier with about 50 dB amplification. The output range of the amplifier may be chosen between a logical −1 and 1. In case of a lock, the sign circuit 83 outputs −1. In case of loss-of-lock, the sign circuit outputs a square wave switching between 1 and −1. The frequency of the square wave is equivalent to the difference between the VCO frequency and the bit rate of the incoming data signal.
Then the adder 84 and the offset generator 85 shift the output signal of the sign circuit 83 by 0.5. Consequently the output of offset generator 85 is either 1.5 or −0.5. The output of the adder 84 is again low-pass filtered by low-pass filters 86 and 88 and digitized by Schmitt-Triggers 87 and 89 with hysteresis, respectively, in order to avoid toggling. The low-pass filter 86 has a cut-off frequency of 0.1 MHz, which may be customized. The low-pass filter 88 has a cut-off frequency of 1 MHz, which may be switched to 10 MHz. Therefore Schmitt-Trigger 87 outputs a slow LOL signal, which declares LOL “reliably”. The fast LOL signal output by Schmitt-Trigger 89 is less reliable and is used during lock acquisition as a signal to declare that lock has (probably) been achieved. The difference is only the amount of averaging applied. The LPF 86 is reset-able to ensure that it “restarts” with LOL clear when the PLL is locked.
Although the circuit of
So far, we have talked about early-late phase detectors that use only three samples to derive the timing information. The timing information can be improved when more than three samples are used. In principle, we can define arbitrary transitions at which the PDs generate information. In general, a selective transitions phase detector can be described by the vector defining the distance between samples (distance sample vector, DSV) and by the PD generator function (PDGF). When n samples are used the DSV is
DSV(d1=0,d2, . . . ,dn) (5)
The first sample is placed at a location d1=0, the next sample is taken from the location d1+d2=d2, and the third one is located at d2+d3, and so on. For example, the DSV of the Alexander PD is defined as DSV(0,T/2,T/2) (cf.
The concept of selective transitions may be considered as a generalization of the Alexander phase detector rule shown in
The strong rising and falling phase detector rules shown in
It is easy to explain, phase detectors evaluating strong transitions work well for dispersive channels. Strong ones, i.e. “11” and strong zeros, i.e. “00” are affected less by dispersion than isolated ones and isolated zeros. Consequently, phase detection based on strong transitions is more reliable. On the other hand, experiments and simulations show that alternating ones and zeros result in jitter, when using an Alexander PD.
A corner frequency of low-pass filter 116 of 0.2 times the symbol frequency has a similar effect: it reduces the influence of alternating ones and zeros and increases the influence of transitions between a sequence of ones and a sequence of zeros on the phase adjustment.
Early-late phase detectors suffer from a TEDC bias which shifts the whole TEDC function, thereby moving the equilibrium point. This bias very often cannot be removed even if more then three samples are used for timing information. The TEDC DC component can cause an additional jitter, and in some cases the VCO fails. The bias can be so high that a TEDC equilibrium point does not exist. This situation can be avoided by introducing so-called symmetry into the TEDC. Let us define offset TEDCs as
TEDCoR(θ)=DCR+sin(θ+φ/2)
TEDCoF(θ)=DCF+sin(θ−φ/2), (6)
where DCR and DCF correspond to the offset of the rising and falling TEDCs, respectively. The TEDC offset can be combatted by doubling the number of PDs and adding an adder for each pair of PDs and a delay circuit 92 as presented in
TEDCR of SPDR 112 and TEDRF of SPDR 115 can then be written as
TEDCsR(θ)=[DCR+sin(θ+φ/2)]−[DCR−sin(θ+φ/2)]=2 sin(θ+φ/2)
TEDCsF(θ)=[DCF+sin(θ−φ/2)]−[DCF−sin(θ−φ/2)]=2 sin(θ−φ/2) (7)
The advantage of a symmetrical PD (SPD) concept can be shown in
The CR performance in dispersive channels can be improved by implementing a low-pass filter 116 in front of the PD as shown in
An enhanced CR concept summarizing innovative steps mentioned so far is shown in
We demonstrate the strength of the proposed method by presenting some simulation results. In
The simulation results are presented in
Comparing Alexander phase detector and Alexander phase detector-DPC we can see that the Alexander phase detector-DPC is superior. However, its performance is inferior for the ODB modulation format with RD between 7000 and 8000 ps/nm. The Sym-Alexander phase detector-DPC shows best performance. Introducing the TEDC symmetry improves CR performance in the critical RD regions of the Alexander phase detector-DPC. This is particularly important for the aforementioned critical ODB region, and for the CML modulation format at RD greater than 10000 ps/nm.
Further modifications and variations of the present invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the present invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 09160054 | May 2009 | EP | regional |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP2010/055985 | 5/3/2010 | WO | 00 | 10/26/2011 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2010/130596 | 11/18/2010 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5592125 | Williams | Jan 1997 | A |
| 6538475 | Johansen et al. | Mar 2003 | B1 |
| 6822483 | Fu et al. | Nov 2004 | B1 |
| 7068086 | Takeda | Jun 2006 | B2 |
| 20030219090 | Baba | Nov 2003 | A1 |
| 20090074123 | Hsueh et al. | Mar 2009 | A1 |
| Number | Date | Country |
|---|---|---|
| 1494413 | Jan 2005 | EP |
| 03079554 | Sep 2003 | WO |
| 2006128114 | Nov 2006 | WO |
| Entry |
|---|
| International Preliminary Report on Patentability and Written Opinion in counterpart International Application No. PCT/EP2010/055985, mailed Nov. 24, 2011. |
| International Search Report dated Jul. 23, 2010 in corresponding PCT/EP2010/055985. |
| Alexander, “Clock Recovery from Random Binary Signals”, Electronics Letters, IEE Stevenage, GB, vol. 11, No. 22, Oct. 30, 1975. |
| Number | Date | Country | |
|---|---|---|---|
| 20120068748 A1 | Mar 2012 | US |
