Patent Grant
7425856
1. Field of the Invention
The present invention relates to electronics, and, in particular, to phase interpolator circuits that generate a selected phase-interpolated output clock signal from two phase-offset input clock signals.
2. Description of the Related Art
Table I shows the different phases of output clock Z for different weighting values w when input clocks A and B are offset by 90 degrees (in particular, when the phase of clock A is 0 degrees, and the phase of clock B is 90 degrees). Greater numbers of different interpolated phase values between 0 and 90 degrees can be achieved by connecting additional, appropriately sized switch/current source pairs on each side of phase interpolator 100 and using weight values having a corresponding additional number of bits.
In one embodiment, the present invention is a phase interpolator adapted to generate a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, wherein interpolation angle of the output clock signal Z is based on an applied weight value W, the phase interpolator comprising A-side circuitry and B-side circuitry connected to the A-side circuitry. The A-side circuitry is adapted to receive the input clock signal A, the B-side circuitry is adapted to receive the input clock signal B, and the output clock signal Z is presented at an output node of the phase interpolator. Each of the A-side circuitry and the B-side circuitry comprises (1) a current source array comprising a plurality of parallel current sources, (2) a switch block comprising a plurality of switches, each switch connected in series to a corresponding current source, and (3) an encoder adapted to control the switches in the switch block based on the weight value W, such that total current through the phase interpolator varies with the interpolation angle of the output clock signal Z.
In another embodiment, the present invention is a method for generating a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B using such a phase interpolator. The method comprises (1) applying the input clock signal A to the A-side circuitry, (2) applying the input clock signal B to the B-side circuitry, and (3) receiving the output clock signal Z at an output node of the phase interpolator.
Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements.
As described above in reference to prior-art phase interpolator 100 of
Z=√{square root over (α2+(1−α)2)}, (1)
where α is the normalized interpolation angle (i.e., the interpolation angle in degrees divided by 90). The results plotted in
Z=√{square root over (sin2(α)+cos2(α))}{square root over (sin2(α)+cos2(α))}. (2)
The bottom portion of phase interpolator 300 is represented in
Unlike prior-art phase interpolator 100 of
Although it is possible for some values of W, in general, the individual bit values of weight value W are not directly applied to control different individual switches in switch blocks 306 and 308 for all values of W, as is the case in prior-art phase interpolator 100 of
According to Equation (1) and as indicated in
In order to implement the linear amplitude correction scheme, the encoders, switch blocks, and current mirror arrays of phase interpolator 300 of
If, instead of applying the linear amplitude correction scheme of
Other amplitude correction schemes, besides the linear scheme of
No matter what amplitude correction scheme is selected to reduce output amplitude variation with interpolation angle, such a scheme can be implemented by designing the encoders, switch blocks, and current mirror arrays of phase interpolator 300 of
Although the present invention has been described in the context of phase interpolator 300 of
The present invention may be implemented as (analog, digital, or a hybrid of both analog and digital) circuit-based processes, including possible implementation as a single integrated circuit (such as an ASIC or an FPGA), a multi-chip module, a single card, or a multi-card circuit pack. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing blocks in a software program. Such software may be employed in, for example, a digital signal processor, micro-controller, or general-purpose computer.
Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range.
It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims.
The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.
It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments of the present invention.
Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.
Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.”
| Number | Name | Date | Kind |
|---|---|---|---|
| 6335697 | Guyot et al. | Jan 2002 | B1 |
| 6359486 | Chen | Mar 2002 | B1 |
| 6597212 | Wang et al. | Jul 2003 | B1 |
| 6943606 | Dunning et al. | Sep 2005 | B2 |
| 7009431 | Panikkar et al. | Mar 2006 | B2 |
| 7298195 | Freyman et al. | Nov 2007 | B2 |
| Number | Date | Country | |
|---|---|---|---|
| 20080001644 A1 | Jan 2008 | US |
