Claims
- 1. An apparatus comprising:
a plurality of differential amplifiers each having inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines; and a biasing circuit switchably coupled to each of the differential amplifiers, the biasing circuit including a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.
- 2. The apparatus of claim 1 wherein each transistor of the first plurality of biasing transistors is responsive to a respective bit of a first digital control value to enable or disable a component current flow within a selected one of the first set of differential amplifiers.
- 3. The apparatus of claim 2 wherein each transistor of the second plurality of biasing transistors is responsive to a respective bit of a second digital control value to enable or disable a component current flow within a selected one of the second set of differential amplifiers.
- 4. The apparatus of claim 3 wherein the second digital control value is a complement of the first digital control value.
- 5. The apparatus of claim 1 further comprising a first plurality of switches coupled between the first set of the differential amplifiers and the biasing circuit, and a second plurality of switches coupled between the second set of differential amplifiers and the biasing circuit.
- 6. The apparatus of claim 5 further comprising a select circuit to output a plurality of control signals to the first plurality of switches and the second plurality of switches, the first plurality of switches being responsive to the control signals to switchably couple a selected differential amplifier of the first set to the biasing circuit, and the second plurality of switches being responsive to the control signals to switchably couple a selected differential amplifier of the second set to the biasing circuit.
- 7. The apparatus of claim 1 wherein at least one of the plurality of differential amplifiers comprises:
a first transistor having a first terminal coupled to a first output signal line of the pair of output signal lines, a second terminal switchably coupled to the biasing circuit, and a control terminal coupled to receive a first clock signal of the pair of clock signals; and a second transistor having a first terminal coupled to a second output signal line of the pair of output signal lines, a second terminal switchably coupled to the biasing circuit and to the second terminal of the first transistor, and a control terminal coupled to receive a second clock signal of the pair of clock signals.
- 8. The apparatus of claim 7 wherein at least one of the first transistor and the second transistor is a bipolar junction transistor.
- 9. The apparatus of claim 7 wherein at least one of the first transistor and the second transistor is a metal oxide semiconductor (MOS) transistor.
- 10. The apparatus of claim 1 wherein the biasing circuit further includes a current source coupled in series with the first plurality of biasing transistors and the second plurality of transistors, the current source being biased by a steady-state bias voltage to establish a maximum current through the biasing circuit.
- 11. The apparatus of claim 1 further comprising:
a control signal generator to generate a first control signal; a first resistive element coupled to receive the first control signal and coupled between a first reference voltage and a first output signal line of the pair of output signal lines, the first resistive element having a variable resistance value according to the first control signal; and a second resistive element coupled to receive the first control signal and coupled between the first reference voltage and a second output signal line of the pair of output signal lines, the second resistive element having a variable resistance value according to the first control signal.
- 12. The apparatus of claim 1 wherein the biasing circuit further includes a slew-rate control circuit coupled in series with the first plurality of transistors and the second plurality of transistors, the slew rate control circuit being biased to draw a current according to a desired slew rate of output clock signals generated on the output signal lines.
- 13. The apparatus of claim 12 further comprising:
a plurality of delay elements coupled in series to generate respective, incrementally delayed clock signals, each of the delayed clock signals having a slew rate according to a first bias voltage; a phase detector coupled to receive a selected pair of the delayed clock signals from the plurality of delay elements and adapted generate a phase adjust signal indicative of which of the selected pair of the delayed clock signals leads the other; and a bias control circuit to adjust the first bias voltage in response to the phase adjust signal, the first bias voltage being output to the slew rate control circuit to control the slew rate of the clock signals generated on the output signal lines.
- 14. The apparatus of claim 13 wherein the bias voltage generator includes a first current source to generate a first current according to a slew control word, and a second current source to generate a second current in proportion to a frequency of a reference clock signal, the first bias voltage being proportional to a sum of the first current multiplied by N and the second current multiplied by M, where N and M are nonzero values.
- 15. The apparatus of claim 14 wherein the reference clock signal has substantially the same frequency as the clock signals generated on the output signal lines.
- 16. The apparatus of claim 14 wherein the clock signals generated on the output signal lines is substantially equal to the frequency of the reference clock signal multiplied by a non-unity value.
- 17. The apparatus of claim 13 further comprising resistive elements coupled between the output signal lines and a reference voltage line, the resistive elements each having a resistance value that is substantially inversely proportional to the first bias voltage.
- 18. A method of operation within an integrated circuit device, the method comprising:
summing a phase count value and an offset value to generate a phase control word; switchably coupling a selected pair of differential amplifiers to a biasing circuit, the selected pair of differential amplifiers being selected from a bank of differential amplifiers in response to the phase control word; and switching selected transistors of a first set of transistors within the amplifier biasing circuit from a substantially non-conducting state to a conducting state to establish a first bias current within a first one of the differential amplifiers of the selected pair, each of the selected transistors of the first set being switchably coupled in series with the first one of the differential amplifiers and being switched to the conducting state by a respective bit of the phase control word.
- 19. The method of claim 18 further comprising switching selected transistors of a second set of transistors within the amplifier biasing circuit from a substantially non-conducting state to a conducting state to establish a second bias current within a second one of the differential amplifiers of the selected pair, each of the selected transistors within the second set being switchably coupled in series with the second one of the differential amplifiers and being switched to the conducting state by a respective bit within a complemented phase control word.
- 20. The method of claim 19 further comprising complementing the phase control word to generate the complemented phase control word.
- 21. The method of claim 18 wherein switchably coupling the selected pair of differential amplifiers to the biasing circuit comprises switchably coupling a first selected differential amplifier to the first set of transistors, and switchably coupling a second selected differential amplifier to the second set of transistors.
- 22. The method of claim 18 wherein switchably coupling the selected pair of differential amplifiers to the biasing circuit comprises outputting a plurality of select signals to a corresponding plurality of switch elements, each of the switch elements being coupled between the biasing circuit and a respective differential amplifier within the bank of differential amplifiers.
- 23. The method of claim 22 wherein outputting a plurality of select signals comprises asserting select signals on a subset of select lines coupled to the plurality of switch elements, and deasserting select signals on others of the select lines
- 24. The method of claim 18 wherein summing a phase count value and an offset value to generate a phase control word comprises generating a phase control word that includes a range select value and an interpolation weight value, the range select value indicating one of a plurality of phase ranges bounded by clock signals coupled to inputs of the differential amplifiers.
- 25. The method of claim 24 wherein switchably coupling the selected pair of differential amplifiers to the biasing circuit in response to the phase control word comprises switchably coupling the selected pair of differential amplifiers to the biasing circuit according to the range select value.
- 26. The method of claim 24 wherein switching selected transistors of the first set of transistors to a conducting state comprises outputting constituent bits of the interpolation weight value to respective control terminals of the first set of transistors.
- 27. The method of claim 26 wherein outputting constituent bits of the interpolation weight value to respective control terminals of the first set of transistors comprises:
storing the interpolation weight value in a storage circuit in response to a timing signal transition; and outputting the constituent bits of the interpolation weight value from the storage circuit to the respective control terminals of the first set of transistors.
- 28. A phase mixing circuit comprising:
a plurality of differential amplifiers each having inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines; and a first resistive element coupled between a first reference voltage and a first output signal line of the pair of output signal lines, the first resistive circuit having a variable resistance value according to a first control signal.
- 29. The phase mixing circuit of claim 28 wherein the first resistive element comprises at least one load transistor coupled between the first reference voltage and the first output signal, the load transistor having a control terminal coupled to receive the first control signal.
- 30. The phase mixing circuit of claim 28 further comprising a control signal generator to generate the control signal.
- 31. The phase mixing circuit of claim 28 further comprising a second resistive element coupled between the first reference voltage and a second output signal line of the pair of output signal lines, the second resistive circuit having a variable resistance value according to the first control signal.
- 32. The phase mixing circuit of claim 28 further comprising a biasing circuit switchably coupled to each of the differential amplifiers.
- 33. The phase mixing circuit of claim 28 further comprising:
a plurality of delay elements coupled in series to generate respective, incrementally delayed clock signals, each of the delayed clock signals having a slew rate according to a first bias voltage; a phase detector coupled to receive a selected pair of the delayed clock signals from the plurality of delay elements and adapted generate a phase adjust signal indicative of which of the selected pair of the delayed clock signals leads the other; and a bias control circuit to adjust the first bias voltage in response to the phase adjust signal, the first bias voltage being output to the first biasing circuit to control a maximum selectable bias current within the first biasing circuit.
- 34. The phase mixing circuit of claim 33 wherein the incrementally delayed clock signals constitute respective pairs of complementary clock signals, each pair of complementary clock signals being the pair of clock signals received at the inputs of a respective one of the plurality of differential amplifiers.
- 35. A locked loop circuit comprising:
a reference loop to generate a plurality of incrementally delayed clock signals and a slew control signal, the reference loop being adapted to adjust the level of the slew control signal as necessary to maintain a predetermined phase relationship between a selected pair of the incrementally delayed clock signals; and a phase mixer including a plurality of differential amplifiers having inputs to receive the incrementally delayed clock signals, the phase mixer further including a biasing circuit to generate first bias current to be drawn from a first selected one of the differential amplifiers, the biasing circuit being coupled to receive the slew control signal from the reference loop and being adapted to generate the first bias current based, at least in part, on the slew control signal.
- 36. The locked loop circuit of claim 35 wherein the first selected one of the plurality of differential amplifiers comprises:
a first transistor having a first, second and third terminals, the first terminal being coupled to a first output signal line, the second terminal being switchably coupled to the biasing circuit, and the third terminal being coupled to receive a first clock signal of the incrementally delayed clock signals; and a second transistor having a first, second and third terminals, the first terminal being coupled to a second output signal line, the second terminal being switchably coupled to the biasing circuit, and the third terminal being coupled to receive a second clock signal of the incrementally delayed clock signals.
- 37. The locked loop circuit of claim 36 wherein the second clock signal is a complement of the first clock signal.
- 38. The locked loop circuit of claim 36 wherein the second terminal of the second transistor is coupled to the second terminal of the first transistor.
- 39. The locked loop circuit of claim 35 wherein the reference loop comprises a phase detector coupled to receive the selected pair of the incrementally delayed clock signals, the phase detector being adapted to output a phase adjust signal that indicates which clock signal of the selected pair leads the other clock signal of the selected pair.
- 40. The locked loop circuit of claim 35 wherein the reference loop further comprises:
a bias signal generator coupled to receive the phase adjust signal from the phase detector and adapted to adjust the level of the slew control signal according to the phase adjust signal; and a plurality of delay elements coupled in series to generate the plurality of incrementally delayed clock signals, each delay element introducing a signal propagation delay according to the level of the slew control signal.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Application No. 60/408,063, filed Sep. 3, 2002, U.S. Provisional Application No. 60/408,101 filed Sep. 3, 2002, and U.S. Provisional Application No. 60/436,745 filed Dec. 27, 2002. Each of U.S. Provisional Application Nos. 60/408,063, 60/408,101 and 60/436,745 is hereby incorporated by reference in its entirety.
Provisional Applications (3)
|
Number |
Date |
Country |
|
60408063 |
Sep 2002 |
US |
|
60408101 |
Sep 2002 |
US |
|
60436745 |
Dec 2002 |
US |