Patent Application
20090189653
The present invention relates generally to clock distribution circuitry, and more particularly, to reducing power and space requirements associated with phase lock loops of high speed serial links.
The ability to perform high speed digital data transmissions is expected in any computing environment. In most cases, the transmission of digital data over long distances is accomplished by sending the data in a high speed serial format (i.e., one single bit after another) over a communication link designed to handle computer communications. In this fashion, data is transferred from one computer system to another, even if the computer systems are geographically remote.
In order for high speed serial transmission to occur, the digital data signal from inside the computer must be transformed from the parallel format into a serial format prior to transmission of the data over the serial communication link. This transformation is generally accomplished by processing the computer's internal data signal through a piece of computer equipment known as a serial link transmitter, or serializer. The function of the serializer is to receive a parallel data stream as input. By manipulating the parallel data stream, the serializer outputs a serial form of the data capable of high-speed transmission over a suitable communication link. Once the serialized data arrives at the desired destination, a deserializer converts the incoming data from the serial format to a parallel format for use within the destination computer system.
For high speed serializer/deserializer (HSS) link pairs, a phase lock loop (PLL) is used to create a phase lock based on the incoming signal. In one sense, the PLL keeps time for the serializer/deserializer pair. The PLL is internal to each device and is required to lock to the input clock frequency, perform the correct multiplication factor and maintain its output with minimal jitter. Jitter is the deviation in, or displacement of, some aspect of the pulses in a high frequency digital signal. A PLL is used because of its inherent feedback path that allows constant correction if a minor change is seen in the input signal edge position or period.
As shown in
The analog circuitry 22 shown in
CML buffers 28 are used to process the clock signal because they are relatively insusceptible to noise. However, CML buffers 28 require a large amount of space on the microchip. That is, the CML buffers 28 are relatively large. A CML buffer 28 generally includes, for example, a differential transistor pair, a biasing transistor and a pair of load transistors. Each CML buffer 28 may occupy 2500 square microns of scarce space on a microchip. Component layout and space requirement considerations are especially critical in HSS design layouts.
Relatedly, the HSS reference clock distribution must be placed and routed amongst the regular chip logic, resulting in additional strains on the physical design for the microchip. Size limitations require that CML buffers 28 be positioned separate from and adjacent to the PLL 12.
CML buffers 28 additionally require relatively large amounts of power. For instance, each CML buffer 28 may consume around 11 mW of power. A typical distribution may contain at least 15 CML buffers, compounding the above space and power requirements.
For the above reasons, what is needed is a clock distribution circuit with decreased space and power requirements.
The present invention provides an improved clock distribution circuit comprising a power source configured to generate a power signal, a phase lock loop circuit including regulating circuitry configured to regulate the power signal, a clock circuit configured to generate a clock signal, and a buffer circuit powered by the regulated power signal and configured to buffer and output the clock signal. In one embodiment, the buffer circuit comprises a CMOS (complementary metal oxide semiconductor) buffer.
According to an aspect of the invention, the buffer circuit is located within the phase lock loop circuit. In another or the same embodiment, another buffer circuit may be located within the phase lock loop circuit.
Embodiments may include another phase lock loop circuit configured to receive the buffered clock signal from the buffer circuit. Where desired, another phase lock loop circuit may be connected in series to the phase lock loop circuit and configured to receive the buffered clock signal from the buffer circuit. Alternatively, another phase lock loop circuit may be connected in a tree configuration to the phase lock loop circuit and may be configured to receive the buffered clock signal from the buffer circuit.
Aspects of the invention may include another phase lock loop configured to receive the buffered clock signal from the buffer circuit and may have substantially the same circuitry as the phase lock loop circuit. Another phase lock loop circuit may be configured to buffer and output another clock signal, and the clock signals may be either synchronous or asynchronous.
Another aspect of the invention includes an improved method of buffering a clock signal. The method comprises generating the clock signal, regulating a power signal within a phase lock loop circuit, powering a buffer circuit using the regulated power signal and buffering the clock signal using the buffer circuit. Where desired, the buffer circuit may comprise a CMOS buffer powered by the regulated power signal.
Embodiments may position the buffer circuit within the phase lock loop circuit. Where so configured, another buffer circuit may be positioned within the phase lock loop circuit. The buffered clock signal may be received at another phase lock loop. In one specific instance, the buffered clock signal may be received at another phase lock loop connected in series to the phase lock loop. Aspects of the invention may include receiving the buffered clock signal at another phase lock loop circuit connected in a tree configuration to the phase lock loop circuit. Other aspects may include configuring another phase lock loop circuit having substantially the same circuitry as the phase lock loop circuit, wherein the second phase lock loop circuit receives the buffered clock signal. Embodiments may further include buffering another clock signal using another phase lock loop circuit, wherein the clock signals are asynchronous. Alternatively, aspects may buffer another clock signal using another phase lock loop, wherein the clock signals are synchronous.
These and other advantages and features that characterize the invention are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the Drawings and to the accompanying descriptive matter in which there are described exemplary embodiments of the invention.
In one respect, embodiments consistent with the invention may capitalize on the quiet, regulated power supply inherent to the PLL to drive a CMOS buffer. In this manner, the CMOS buffer may distribute the reference clock in a manner that minimizes the power and space consumption plaguing conventional clock distribution processes.
In many high HSS I\O intensive microchip designs, the HSS, or PHY macros, will be brick-walled in the microchip floor plan. The PLL's that exist in the PHY may each have a low noise, internally regulated power supply. Simple CMOS buffers that receive their power from the PLL regulated supply may be used to buffer the reference clock from PLL to PLL. The CMOS distribution performance may surpass that of conventional CML clock distribution schemes. The power supply noise reduction from the PLL regulator provides the CMOS clock buffer with superior deterministic and random jitter characteristics relative to CML buffer versions of clock distribution for HSS/PHY/PLL reference clocks.
In one configuration, a clock signal enters a microchip and is distributed among a number of PLL's. Each PLL typically drives a PHY. The PHY may perform the actual HSS logic. In this manner, the PLL provides a clock to the PHY. The PHY may drive data in the clocks over to the other PHY's on other chips. The reference clock signal needs to be free of noise. For this reason, the CMOS buffers typically receive power from built-in voltage and/or amperage regulators configured to isolate, filter and otherwise minimize noise and jitter.
In the embodiment of
The CMOS buffer 75 may include a CMOS circuit. The CMOS buffer 75 typically comprises a cascade of two CMOS inverters, each of which may include a NMOS transistor and a PMOS transistor.
As shown in
As shown in
The circuit 80 is configured to receive and distribute a reference clock signal from the intermediate frequency (IF) PLL 96. The reference clock signal may then be passed on, e.g., in daisy-chained fashion, between the serially connected PLL buffers 98, 100, 102, 104, 106, 108, 110 for the PLL's. That is, reference clock signal 1 may be processed by the PLL 98 to generate reference clock signal 2, which may then be supplied as an input to PLL 100, and so on, until reference clock signal “n” is provided to the last PLL 110 in the circuit 80. As shown, the circuit 80 of PHY's 82, 84, 86, 88, 90, 92, 94 may be suited for inclusion within the design plan for the PLL clock circuit 30 of
In one sense, the clock referenced signal may be distributed throughout the PLL's 122, 124, 126, 128, 130, 132, and 134 and the associated CMOS buffers 136 in an h-tree distribution pattern. This configuration may have particular application where the clock signal must be synchronized as between the respective PLL's 122, 124, 126, 128, 130, 132, 134. That is, the embodiment shown in
Because some of the CMOS buffers 136 connect to two CMOS buffers 136, while others connect to only one, dummy receiver loads 140 may be used in addition to reference clock receivers 138 to help balance the distribution process. In this manner, embodiments consistent with the invention may balance the loads to each of the PLL's 122, 124, 126, 128, 130, 132, 134.
In
While the present invention has been illustrated by a description of various embodiments and while these embodiments have been described in considerable detail, it is not the intention of the Applicants to restrict, or in any way limit the scope of the appended claims to such detail. For instance, because HSS applications are well understood and documented, many aspects of the invention have been described in terms of HSS based concepts. However, the HSS based concepts are used principally for ease of explanation. The invention is not limited to interactions with a HSS environment. Moreover, while CMOS buffers are advantageous in many embodiments, one skilled in the art will recognize that other buffers may be connected to the internal power supply of the PLL to achieve other desirable results. The invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative example shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of Applicants' general inventive concept.
This invention was made with United States Government support under Agreement No. HR0011-07-9-0002 awarded by DARPA. The Government has certain rights in the invention.
