PHASE LOCK LOOP FOR RAPID LOCK-IN AND METHOD THEREFOR

Abstract

A phase-locked loop (PLL) for rapid lock-in applicable to digital, analog, or hybrid digital-analog PLL circuits is provided. Besides the units for basic operation, including a phase-frequency detector (PFD), a charge pump, a loop filter, and/or a voltage/current/digital-controlled oscillator (VCO/ICO/DCO), an additional lock-in actuator circuit is provided for providing lock-in signals, achieving the purpose of rapid lock-in through operational processes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from the detailed description given herein below for illustration only, and which thus is not limitative of the present invention, and wherein:

FIG. 1 is a system block diagram of a conventional digital PLL;

FIG. 2 is a diagram of frequency to period of the reference signal;

FIG. 3 is a system block diagram of an analog PLL for rapid lock-in;

FIG. 4 is a diagram of frequencies of a reference voltage signal and a phase-locked output signal;

FIG. 5 is a diagram of frequency to period of the reference signal;

FIG. 6 is a diagram of frequency to period of the reference signal;

FIG. 7 is a system block diagram of a digital PLL for rapid lock-in; and

FIG. 8 is a system block diagram of a hybrid digital-analog PLL for rapid lock-in.

Claims

1. An analog PLL, comprising: a phase frequency detector (PFD), for receiving a reference signal and a feedback signal, and generating a phase difference signal accordingly to the reference signal and the feedback signal;a loop filter, coupled to a charge pump, for generating a reference voltage signal according to the phase difference signal;a voltage/current-controlled oscillator (VCO/ICO), for generating a phase-locked output signal according to the reference voltage signal; anda lock-in actuator circuit, for activating a lock-in signal, wherein the lock-in signal is output to at least the loop filter or/and the VCO/ICO, to set the analog PLL in a lock-in state.

2. The analog PLL as claimed in claim 1, wherein the lock-in signal is generated according to the reference signal and/or the phase-locked output signal.

3. The analog PLL as claimed in claim 2, wherein the lock-in signal is generated by interpolation or extrapolation according to a plurality of voltage values provided by the reference signal and a plurality of corresponding frequency values provided by the phase-locked output signal.

4. The analog PLL as claimed in claim 1, wherein the lock-in signal is generated by look-up tables and/or pre-calculations of provided parameters.

5. The analog PLL as claimed in claim 1, further comprising: a divider, coupled to the VCO/ICO and the PFD, for dividing the phase-locked output signal, wherein the divided phase-locked output signal is the feedback signal.

6. The analog PLL as claimed in claim 5, wherein the lock-in actuator circuit controls the dividing of the phase-locked output signal.

7. The analog PLL as claimed in claim 1, wherein the lock-in state is set from an initial state or from a first lock-in state.

8. A digital PLL, comprising: a phase frequency detector (PFD), for receiving a reference signal and a feedback signal, and generating a level signal according to the reference signal and the feedback signal;a digital-controlled oscillator (DCO), coupled to the PFD, for generating a phase-locked output signal according to a lock-in signal or/and the level signal; anda lock-in actuator circuit, for activating the lock-in signal, wherein the lock-in signal is used to set the digital PLL in a lock-in state.

9. The digital PLL as claimed in claim 8, wherein the lock-in signal is generated according to the reference signal and/or the phase-locked output signal.

10. The digital PLL as claimed in claim 8, wherein the level signal is generated according to the magnitude of phase difference of the reference signal and the feedback signal.

11. The digital PLL as claimed in claim 8, wherein the lock-in signal is generated by interpolation or extrapolation according to a plurality of voltage values provided by the reference signal and a plurality of corresponding frequency values provided by the phase-locked output signal.

12. The digital PLL as claimed in claim 8, wherein the lock-in signal is generated by look-up tables and/or pre-calculations of provided parameters.

13. The digital PLL as claimed in claim 8, further comprising: a phase difference quantizer, for receiving the reference signal and the feedback signal, and generating a count signal according to the reference signal and the feedback signal.

14. The digital PLL as claimed in claim 8, further comprising: a divider, coupled to the DCO and the PFD, for dividing the phase-locked output signal, wherein the divided phase-locked output signal is the feedback signal.

15. The digital PLL as claimed in claim 14, wherein the lock-in actuator circuit controls the dividing of the phase-locked output signal.

16. The digital PLL as claimed in claim 8, wherein the DCO includes: a controller, for generating a phase control signal according to the lock-in signal or/and the level signal; anda phase switching unit, for receiving the phase control signal and generating the phase-locked output signal.

17. The digital PLL as claimed in claim 16, wherein the lock-in signal includes at least a frequency control word (FCW) or/and a period control word (PCW).

18. The digital PLL as claimed in claim 8, wherein the lock-in state is set from an initial state or from a first lock-in state.

19. A hybrid PLL, comprising: a digital PLL, for generating a first phase-locked output signal in response to a second phase-locked output signal;an analog PLL, for generating the second phase-locked output signal in response to the first phase-locked output signal; anda lock-in actuator circuit, for activating a lock-in signal, wherein the lock-in signal is used to control the digital PLL or/and the analog PLL in order that the hybrid PLL is set in a lock-in state.

20. The hybrid PLL as claimed in claim 19, wherein the lock-in signal is generated according to a reference signal and/or the first phase-locked output signal and/or the second phase-locked output signal.

21. The hybrid PLL as claimed in claim 19, wherein the lock-in signal is generated by interpolation or extrapolation according to a plurality of voltage values provided by the reference signal and a plurality of corresponding frequency values provided by the phase-locked output signal.

22. The digital PLL as claimed in claim 19, wherein the lock-in signal is generated by look-up tables and/or pre-calculations of provided parameters.

23. The hybrid PLL as claimed in claim 19, further comprising: a divider, coupled to the digital PLL and the analog PLL, for dividing the first phase-locked output signal or the second phase-locked output signal.

24. The hybrid PLL as claimed in claim 23, wherein the lock-in actuator circuit controls the dividing of the first phase-locked output signal or the second phase-locked output signal.

25. The hybrid PLL as claimed in claim 19, wherein the lock-in state is set from an initial state or from a first lock-in state.

26. A method applicable to a PLL for rapid lock-in, comprising: measuring a temporal feature of a reference signal or/and a phase-locked output signal; andproviding a lock-in signal according to the temporal feature, wherein the lock-in signal is used to set the PLL in a lock-in state.

27. The method for rapid lock-in as claimed in claim 26, wherein the lock-in signal is generated by interpolation or extrapolation according to a plurality of voltage values and a plurality of corresponding frequency values provided by the temporal feature.

28. The method for rapid lock-in as claimed in claim 26, wherein the temporal feature provides a upper frequency limit and a lower frequency limit of the frequency when the PLL is in a lock-in state.

29. The method for rapid lock-in as claimed in claim 28, wherein the initial lock-in frequency is the average value of the upper frequency limit and the lower frequency limit respectively weighted.

30. The method for rapid lock-in as claimed in claim 26, wherein the lock-in signal is generated by look-up tables and/or pre-calculations of provided parameters.