This application is a continuation of application Ser. No. 08/300,608, filed Sep. 2, 1994 now abandoned.
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Entry |
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A. Efendovich, Y. Afek, C. Sella, Z. Bikowsky, "Multi-Frequency Zero-Jitter Delay-Locked Loop", pp. 27.1.1-27.1.4, IEEE 1993, Custom Integrated Circuits Conference. |
T. Lee, K. Donnelly, J. Ho, J. Zerbe, M. Johnson, T. Ishikawa, "A 2.5V Delay-Locked Loop for an 18 Mb 500 MB/s DRAM", IEEE International Solid-State Circuits Conference, ISSCC94/Session 18/High-Performance Logic and Circuit Techniques/Paper FA 18.6, 1994. |
A. Waizman, "A Delay Line Loop for Frequency Synthesis of De-Skewed Clock", IEEE International Solid-State Circuits Conference, ISSCC94/Session 18/High-Performance Logic and Circuit Techniques/Paper FA 18.5, 1994. |
Number | Date | Country | |
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Parent | 300608 | Sep 1994 |